JP3655258B2 - Display device for video scaling - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device that scales and displays input video.
[0002]
[Prior art]
There are cases where it is desired to display a video created by a computer on another display device such as a liquid crystal projector. In such a case, a video signal corresponding to the resolution of the display device needs to be created on the computer side. In this specification, “resolution” means the number of dots in the horizontal direction (number of pixels) and the number of lines in the vertical direction (number of scanning lines). The number of dots in the horizontal direction is called “horizontal resolution”, and the number of lines in the vertical direction is called “vertical resolution”.
[0003]
[Problems to be solved by the invention]
The resolution and the number of gradations of video that can be generated by a computer are limited by the capacity of a video RAM (VRAM) in the computer. That is, there is a relationship that the number of gradations decreases when displaying with a large resolution (that is, a large screen size), and the resolution decreases when the number of gradations is increased. For this reason, when the screen size of the display device is large, the resolution of the video signal generated by the computer may not be matched with the resolution of the display device. Such a problem is the same when a video other than the computer (for example, a television video) is displayed on a display device other than the television.
[0004]
The present invention has been made to solve the above-described problems in the prior art, and an object of the present invention is to convert the video into the resolution of the display device and display it regardless of the resolution of the input video.
[0005]
[Means for solving the problems and their functions and effects]
  In order to solve at least a part of the above-described problems, a video scaling device according to the present invention includes a resolution determination table that stores a relationship between a frequency and a resolution of a synchronization signal of a video signal,
  Resolution determining means for determining the resolution of the video signal to be scaled based on the relationship between the frequency and resolution of the synchronization signal stored in the resolution determination table;
  When the video signal is read from the frame memory, the video represented by the video signal is enlarged by a non-integer multiple in the vertical and horizontal directions so that the resolution of the video signal matches the resolution of the display device. Scaling means to convert;
With
  The resolution determination table stores a case where a plurality of different frequencies correspond to the same resolution,
  The vertical and horizontal ranges of the read address when reading the video signal from the frame memory are set according to the resolution of the video signal,
The scaling means includes
  The reciprocal of the horizontal magnification and the reciprocal of the vertical magnification determined by the ratio of the resolution of the display device and the resolution of the video signalMeans for calculating;
  The reciprocal of the horizontal magnification and the reciprocal of the vertical magnification,Values multiplied by the horizontal and vertical read addresses at the same magnification displayMeans for generating horizontal and vertical read addresses for enlarged display, respectively,
WithIt is characterized by that.
[0006]
Since the resolution of the display device is known, the input video signalresolutionTheUsing resolution determination tableIf discriminated, the video signalresolutionAnd display deviceresolutionCan be obtained. Therefore, if the image is enlarged or reduced at this ratio,resolutionDisplay device'sresolutionCan be displayed in accordance with.
[0007]
The resolution determining means may determine the resolution of the video signal based on the frequency and period width of the synchronization signal, and the resolution of the video signal based on the frequency of the synchronization signal and the presence / absence of interlace. May be determined.
[0008]
If the resolution of the video signal is determined based not only on the frequency of the synchronization signal but also on the period width of the synchronization signal and the presence or absence of interlacing, errors in determining the resolution can be reduced.
[0014]
As the video signal, a computer generated video signal, a television video signal, or the like can be applied.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described based on examples. FIG. 1 is a block diagram showing the configuration of the liquid crystal projector according to the first embodiment of the present invention. This liquid crystal projector is a device that projects an image generated by the personal computer 100 onto a large-size screen (not shown), and includes a CPU 20, a main memory 22, an input panel 24 as input means, an A / A A D converter 32, a frame memory 34, a video scaler 36, an LCD driver 38, an LCD panel (liquid crystal display panel) 40, and a light source 42 are provided. The frame memory 34 has three memory planes for storing RGB signals.
[0016]
The CPU 20 has a function as a frequency determination unit 26 that determines the frequency of the synchronization signal SYNC given from the personal computer 100 and a function as a resolution determination unit 28 that determines the resolution corresponding to the frequency of the synchronization signal SYNC. These functions are realized by the CPU 20 executing a software program stored in the main memory 22.
[0017]
The A / D converter 32 A / D converts the video signal VPC given from the personal computer 100 to generate a digital video signal DPC, and inputs this to the video scaler 36. The video scaler 36 is supplied with the digital video signal DPC and the synchronization signal SYNC from the personal computer 100. In this specification, the “video signal” may mean a narrowly defined video signal that does not include a synchronization signal, or a broadly defined video signal that includes a synchronization signal.
[0018]
The video scaler 36 writes the input digital video signal DPC into the frame memory 34, reads out the video signal from the frame memory 34, and supplies it to the LCD driver 38. At this time, the video scaler 36 adjusts the resolution of the video signal so as to match the standard resolution of the LCD panel 40 by enlarging or reducing the video. The LCD driver 38 displays the video provided from the video scaler 36 on the LCD panel 40. The image displayed on the LCD panel 40 is projected on the screen by the light source 42.
[0019]
FIG. 2 is an explanatory diagram showing the function of the video scaler 36. As shown on the left side of FIG. 2, video generated by a personal computer has various resolutions (640 dots × 400 lines, 640 dots × 480 lines, 800 dots × 600 lines, 1024 dots × 768 lines, 1600 dots × 1200 lines). On the other hand, the standard resolution of the LCD panel 40 is constant, and is 800 dots × 600 lines in the example of FIG. Therefore, the video scaler 36 generates a video signal having the standard resolution of the LCD panel 40 by enlarging or reducing the input video signal VPC. In this way, if the video signal VPC generated by the personal computer 100 is input to the liquid crystal projector, the video can be displayed on the full screen of the LCD panel 40. That is, the resolution in the liquid crystal projector is independent of the resolution of the input video signal VPC. Therefore, an image having a desired resolution and gradation can be generated on the personal computer 100 side, and the image can be displayed on the entire screen of the LCD panel 40.
[0020]
FIG. 3 is a block diagram showing the internal configuration of the video scaler 36. The video scaler 36 includes a first color converter 50, a write synchronization signal generator 52, an input FIFO buffer 54, a DRAM controller 56, an address controller 58, a CPU access controller 60, and an output Two FIFO buffers 61 and 62, a filter unit 64, a second color conversion unit 66, and a readout synchronization signal generation unit 68 are provided. As shown in FIG. 3, in this embodiment, the frame memory 34 is composed of a dynamic RAM. The DRAM controller 56 is a circuit that controls writing of the video signal to the frame memory 34 and reading of the video signal from the frame memory 34.
[0021]
The digital video signal DPC generated by the A / D converter 32 of FIG. 1 is given to the first color conversion unit 50, and color conversion into RGB signals is performed as necessary. For example, when the input digital video signal DPC is a YCrCb signal, the color converter 50 converts it into an RGB signal.
[0022]
The synchronization signal SYNC given from the personal computer 100 includes a horizontal synchronization signal HSYNC1 and a vertical synchronization signal VSYNC1. The write synchronization signal generator 52 generates the dot clock signal DCK1 by multiplying the frequency of the horizontal synchronization signal HSYNC1 or the vertical synchronization signal VSYNC1 by N0 by an internal PLL circuit (not shown). This dot clock signal DCK1 is a signal indicating the update timing of the dot position in the horizontal direction. The dot clock signal DCK1 is supplied to the address controller 58 together with the horizontal synchronization signal HSYNC1 and the vertical synchronization signal VSYNC1.
[0023]
The video signal converted by the first color conversion unit 50 is temporarily stored in the FIFO buffer 54 and written into the frame memory 34 by the DRAM controller 56. The FIFO buffer 54 is used for adjusting the write timing. The write operation to the frame memory 34 is performed in synchronization with the write synchronization signal {DCK1, HSYNC1, VSYNC1} given from the write synchronization signal generator 52. That is, each dot position (horizontal address) is updated in synchronization with the dot clock signal DCK1, the scanning line position (vertical address) is updated in synchronization with the horizontal synchronization signal HSYNC1, and each frame (each field) is vertical. It is updated in synchronization with the synchronization signal VSYNC1. The DRAM controller 56 also performs control to read out video signals stored in the frame memory 34 and write them alternately in the FIFO buffers 61 and 62. The read operation from the frame memory 34 is performed in synchronization with the read synchronization signal {DCK2, HSYNC2, VSYNC2} generated by the read synchronization signal generator 68. The read synchronization signal {DCK2, HSYNC2, VSYNC2} is also supplied to the LCD driver 38 and used as a display synchronization signal on the LCD panel 40. The address controller 58 is a circuit that generates a write address and a read address and supplies the address to the DRAM controller 56, and includes a scaling unit 70 that enlarges / reduces the video.
[0024]
Video signals for one line read from the frame memory 34 are alternately written in the two FIFO buffers 61 and 62 for output. At this time, the video signal is read from the buffer that has not been written and is supplied to the filter unit 64. The filter unit 64 is a circuit that performs various kinds of filtering processing such as γ correction (input / output gradation conversion), video horizontal reversal, vertical reversal, and the like. The video signal that has been subjected to the filtering process is subjected to color conversion in the color converter 66 as necessary, and is converted into an output video signal DOUT. The output video signal DOUT is supplied to the LCD driver 38 (FIG. 1).
[0025]
The CPU 20 in FIG. 1 can access each part in the video scaler 36 via the CPU access controller 60 in FIG. When determining the frequency of the synchronization signal SYNC corresponding to the input video signal VPC, the CPU 20 receives a signal from the write synchronization signal generator 52 via the CPU access controller 60. First, the CPU 20 functions as the frequency determination unit 26 (FIG. 1) and measures the frequencies of the horizontal synchronization signal HSYNC1 and the vertical synchronization signal VSYNC1 input to the write synchronization signal generation unit 52, respectively. Next, it functions as the resolution determination unit 28 and determines the resolution of the input video signal VPC based on these frequencies.
[0026]
FIG. 4 is a resolution determination table showing the relationship between resolution and frequency. In this resolution determination table, the relationship between various resolutions (number of dots × number of lines) and the frequency of the horizontal synchronization signal and the vertical synchronization signal is registered. The resolution determination table is stored in the main memory 22. Since the frequency of the operation clock of the CPU 20 is several tens of MHz, the frequency of the horizontal synchronizing signal is several tens of kHz, and the frequency of the vertical synchronizing signal is several tens of Hz, the function of the frequency determining unit 26 is executed by software processing. Can be measured with sufficient accuracy. For example, if the CPU 20 counts up at a constant period and obtains the count number between the edges (eg, the falling edge) of the horizontal synchronization signal HSYNC1, the frequency of the horizontal synchronization signal HSYNC1 can be obtained from the count number. it can. The same applies to the vertical synchronization signal VSYNC1. Thus, when the frequencies of the synchronization signals HSYNC1 and VSYNC1 are determined, the resolution determination unit 28 refers to the resolution determination table (FIG. 4) and determines the corresponding resolution.
[0027]
By the way, as illustrated in FIG. 4, there may be several types of frequencies of the synchronization signal even at the same resolution. Therefore, it is preferable to register as many relations as possible between the resolution and frequency used in many commercially available devices in the resolution determination table. However, there may be a case where a video signal having a frequency not registered in the resolution determination table is input. In this case, the CPU 20 displays on the LCD panel 40 (or the display unit of the input panel 24) that the frequency of the input video signal VPC has not been registered. Then, when the user sets the resolution (number of dots × number of lines) of the input video signal VPC using the input panel 24, the relationship between the frequency and the resolution is registered in the resolution determination table. In order to realize this processing, it is preferable to store the resolution determination table in a writable memory such as a RAM or a flash memory.
[0028]
When determining the resolution of the input video signal VPC, the resolution may be determined based not only on the frequency of the horizontal synchronizing signal and the vertical synchronizing signal but also on their period widths HH and HV and the presence / absence of interlace. . FIG. 5 is an explanatory diagram for explaining the period widths HH and HV of the horizontal synchronizing signal and the vertical synchronizing signal. However, for convenience of illustration, FIG. 5 shows the waveform of the composite video signal. If the resolution of the input synchronization signal is determined based not only on the frequency of the synchronization signal but also on their period widths HH and HV and the presence or absence of interlace, errors in determining the resolution can be reduced.
[0029]
The horizontal resolution and the vertical resolution determined by the resolution determination unit 28 are given to the address controller 58 via the CPU access controller 60 (FIG. 3). The scaling unit 70 in the address controller 58 executes enlargement / reduction of the image as described with reference to FIG. 2 in order to convert these resolutions into the standard resolution of the LCD panel 40.
[0030]
FIG. 6 is a block diagram illustrating an internal configuration of the scaling unit 70. The scaling unit 70 includes a PLL circuit 142, a frequency divider 144, a horizontal address formation unit 146, a vertical address formation unit 148, a 3-state buffer unit 160, and an inverter 162. A data latch 164 shown in FIG. 6 is a circuit in the DRAM controller 56. The horizontal address forming unit 146 includes a latch failure removal circuit 150, a first counter 152, and a first latch 154. The vertical address forming unit 148 includes a second counter 156 and a second latch 158.
[0031]
The PLL circuit 142 generates a second dot clock signal DCKX having a frequency N times that from the horizontal synchronizing signal HSYNC2 for reading. The frequency divider 144 generates the line increment signal LINCX by dividing the dot clock signal DCK2 for reading by 1 / M. The setting values N and M in the PLL circuit 142 and the frequency divider 144 are values for converting the resolution of the input video signal VPC to the resolution of the LCD panel 40, and are set by the CPU 20, respectively. A method for determining these set values N and M will be described later.
[0032]
FIG. 7 is a timing chart showing the operation of the vertical address forming unit 148. The second counter 156 counts the number of pulses of the line increment signal LINX after being reset by the vertical synchronization signal VSYNC2 for reading (FIG. 7A). Further, the count value HC (FIG. 7D) of the second counter 156 is latched in accordance with the rising edge of the horizontal synchronization signal HSYNC2, and is given to the 3-state buffer 160 as the vertical address VADD. In the example of FIG. 7E, the value of the vertical address VADD is updated as 0, 1, 1, 2,.
[0033]
FIG. 8 is an explanatory diagram showing a state of video enlargement. FIG. 8A shows video data stored in the frame memory 34, and FIG. 8B shows enlarged video data. Further, the numbers described in the respective frames in these figures are the values of the video data. In the timing chart of FIG. 7E, the image on the scan line with VADD = 0 is read once, the image on the scan line with VADD = 1 is read twice, the image on the scan line with VADD = 2 is read twice, and so on. Thus, the video data is read from the frame memory 34. Therefore, the read video is enlarged in the vertical direction as shown in FIG. The vertical magnification MV2 is given by the ratio of the frequency fHSYNC2 of the horizontal synchronization signal HSYNC2 to the frequency fLINCX of the line increment signal LINCX. Therefore, by adjusting the setting value M of the frequency divider 144 (FIG. 7), it is possible to enlarge the video image at an arbitrary magnification in the vertical direction. If the value of the magnification MV2 is set to 1 or less, it can be reduced in the vertical direction.
[0034]
FIG. 9 is a timing chart showing the operation of the horizontal address forming unit 146. The latch failure removal circuit 150 (FIG. 6) generates a third dot clock signal DCKXX (FIG. 9 (e)) in response to the first and second dot clock signals DCK2 and DCKX (FIG. 9 (b), (d)). Is generated.
[0035]
FIG. 10 is a block diagram showing an internal configuration of the latch failure removal circuit 150. As shown in FIG. The latch failure elimination circuit 150 includes a delay unit 170, an EXNOR circuit 172, and a D-type flip-flop 174. The output signal DKFF of the EXNOR circuit 172 is an inverted signal obtained by taking an exclusive OR of the first dot clock signal DCK2 and a signal obtained by delaying the dot clock signal DCK2 by a predetermined time. Therefore, this signal DKFF is a signal indicating the rising and falling timings of the first dot clock signal DCK2, as shown in FIG. 9C.
[0036]
The output signal DKFF of the EXNOR circuit 172 is given to the clock input terminal of the flip-flop 174. A second dot clock signal DCKX is supplied to the D input terminal of the flip-flop 174. Therefore, the third dot clock signal DCKXX, which is the output of the flip-flop 174, is the same as the second dot clock signal DCKX at the rising edge of the output signal DKFF of the EXNOR circuit 172, as shown in FIG. This is a signal indicating the level. The third dot clock signal DCKXX has a frequency equal to that of the second dot clock signal DCKX. Further, since the output signal DKFF of the EXNOR circuit 172 rises after a predetermined delay time from the edge of the first dot clock signal DCK2, the timing of the level change of the third dot clock signal DCKXX is also the first dot clock signal DCKXX. Delayed from the edge of the clock signal DCK2 by a predetermined delay time. The reason why such a third dot clock signal DCKXX is generated by the latch failure removal circuit 150 is to prevent the horizontal address value latched by the first latch 154 from becoming unstable. Will be further described later.
[0037]
The first counter 152 (FIG. 6) of the horizontal address forming unit 146 counts up the number of pulses of the third dot clock signal DCKXX generated by the latch miss removal circuit 150 after being reset by the pulse of the horizontal synchronization signal HSYNC2. Then, the count value DC (FIG. 9 (f)) is supplied to the first latch 154. Incidentally, since the third dot clock signal DCKXX has the same frequency as the second dot clock signal DCKX, the count value DC of the first counter 152 is substantially the pulse of the second dot clock signal DCKX. Shows the number. The first latch 154 latches the count value DC in synchronization with the first dot clock signal DCK2, and provides it to the three-state buffer 160 as the horizontal address HADD (FIG. 9 (g)). That is, the horizontal address HADD is a value indicating the number of pulses of the second dot clock signal DCKX, and the value is updated according to the rising edge of the first dot clock signal DCK2. Therefore, it is possible to set how to update the value of the horizontal address HADD by adjusting the frequency fDCK2 of the first dot clock signal DCK2 and the frequency fDCKX of the second dot clock signal DCKX. In the example of FIG. 9G, it can be seen that the value of the horizontal address HADD changes as 0, 0, 1,.
[0038]
FIGS. 8A and 8B described above illustrate how the video is enlarged in accordance with the update of the horizontal address HADD in FIG. 9G. The timing chart shown in FIG. 9 corresponds to the address generation timing in the horizontal direction on the uppermost scanning line where the vertical address VADD is zero. As shown in FIG. 9G, the horizontal address HADD is updated to 0, 0, 1,. Therefore, on this scanning line, the video data of the pixel with the horizontal address HADD = 0 is read twice, and then the video data of the pixel with HADD = 1 is once in the order of the video data of each pixel. The data is sequentially read from the memory 34.
[0039]
Thus, the horizontal address HADD depends on the frequency relationship between the two dot clock signals DCK2 and DCKX. Therefore, by adjusting the frequency of these dot clock signals DCK2 and DCKX, the video can be enlarged / reduced in the horizontal direction. That is, the horizontal magnification MH2 of the video at the time of reading is given by the ratio between the frequency fDCK2 of the first dot clock signal DCK2 and the frequency fDCKX of the second dot clock signal DCKX, as shown in the lower part of FIG. It is done. Therefore, by adjusting the setting value N of the PLL circuit 142, it is possible to enlarge / reduce the video image at an arbitrary magnification in the horizontal direction.
[0040]
The reason why the signal DCKXX is generated by the latch failure removal circuit 150 is as follows. As shown in FIG. 9 (f), the count value DC of the first counter 152 is equal to the third dot clock signal DCKXX (FIG. 9) after the horizontal synchronization signal HSYNC2 (FIG. 9 (a)) returns to the H level. It changes in synchronization with the rising edge of (e)). On the other hand, as described above, the edge of the third dot clock signal DCKXX is delayed by a predetermined time from the edge of the first dot clock signal DCK2, so that the latch timing in the first latch 154 is the count value DC. Therefore, the horizontal address HADD does not become unstable.
[0041]
As described above, by adjusting the setting value N of the PLL circuit 142 and the setting value M of the frequency divider 144 shown in FIG. 6, the horizontal magnification MH2 and the vertical magnification MV2 are respectively set as shown in the lower part of FIG. It can be set independently. Accordingly, the horizontal magnification MH2 is set equal to (horizontal resolution of the LCD panel 40) / (horizontal resolution of the input video signal VPC), and the vertical magnification MV2 is set to (vertical resolution of the LCD panel 40) / (input video signal). If it is set equal to the vertical resolution of the VPC), it is possible to display an image on the full screen of the LCD panel 40.
[0042]
FIG. 11 is a block diagram showing a configuration of a down converter as a second embodiment of the present invention. This down-converter adds a video signal selection unit 200 to the input unit of the liquid crystal projector shown in FIG. 1, replaces the LCD driver 38 with a video encoder 202, and replaces the LCD panel 40 and the light source 42 with various output devices (TVs). John 204, video player 206, andWritable compact disc device208).
[0043]
The video signal selection unit 200 is a selector that receives two types of video signals STV1 and STV2 for television in addition to the video signal {VPC, SYNC} generated by the personal computer and selects one of them. is there. Note that the television video signals STV1 and STV2 are composite video signals including a synchronization signal. When selecting a composite video signal, a component video signal VIN and a synchronization signal SYNC are generated from the composite video signal by a decoder (not shown) in the video signal selection unit 200.
[0044]
The video encoder 202 generates a composite video signal from the digital video signal DOUT output from the video scaler 36 and the readout synchronization signal (DCK2, HSYNC2, VSYNC2). This composite video signal is supplied to the television 204 and the video player 206.Writable compact disc device 208When the video is written to the video encoder, the video encoder does not generate the composite video signal, but directly uses the digital video signal DOUT and the readout synchronization signal.Writable compact disc device208 is supplied. Since the video scaler 36 can change the video to a desired resolution, the video can be output at a desired resolution according to various output devices by the user setting the resolution. The reason why the apparatus of FIG. 11 is called a “down converter” has the meaning that various input video signals can be converted into various output video signals in this way.
[0045]
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.
[0046]
(1) The functions of the frequency determination unit 26 and the resolution determination unit 28 (FIG. 1) realized by software processing in the above embodiment can be realized by a hardware circuit.
[0047]
(2) In the above embodiment, the enlargement / reduction is performed when the image is read from the frame memory 34. However, the enlargement / reduction may be performed when the image is written to the frame memory 34. is there.
[0048]
(3) As a method of enlarging / reducing, it is possible to apply a method other than the frequency control described above. For example, it is possible to change the address by multiplying the read address or the write address by a coefficient, thereby enlarging or reducing the address. FIG. 12 is an explanatory diagram showing a method of enlarging / reducing an image by multiplying the read address by a coefficient K. FIG. 12A shows images stored in the frame memory 34, and FIGS. 12B1 to 12B3 show images that are enlarged and reduced. Di, j indicates image data written at an address (i, j) in the frame memory 34.
[0049]
In FIG. 12, when the memory resolution is Mx (dot) × My (line) and the display resolution is Nx (dot) × Ny (line), the coefficient K (Kx, Ky) to be multiplied by the address is expressed by the following equation: Given in.
[0050]
Kx = Mx / Nx (1a)
Ky = My / Ny (1b)
[0051]
A read address (XADD, YADD) for reading image data from the frame memory 34 is converted into a new read address (XADD ', YADD') by the following equation.
[0052]
XADD ′ = INT (Kx × XADD) (2a)
YADD ′ = INT (Ky × YADD) (2b)
[0053]
Here, the operator INT () represents an operation that takes an integer part in parentheses.
[0054]
FIG. 12B1 is an example of an image displayed when the coefficients Kx and Ky are larger than 1.0 (for example, when Kx = Ky = 2.0). When the original horizontal address XADD increases by 1, 0, 1, 2,..., The converted horizontal address XADD ′ changes to 0, 2, 4,... According to (2a) above. The same applies to the vertical address YADD. Since the image data is read from the frame memory 34 in accordance with the read addresses XADD ′ and YADD ′, the image is reduced and displayed as shown in FIG. 12 (B1). At this time, the horizontal magnification and the vertical magnification are equal to 1 / Kx and 1 / Ky, respectively.
[0055]
As shown in FIG. 12B2, when the coefficients Kx and Ky are equal to 1.0, the image in the frame memory 34 is displayed at the same magnification.
[0056]
FIG. 12B3 is an example of an image displayed when the coefficients Kx and Ky are smaller than 1.0 (for example, when Kx = Ky = 0.7). When the original horizontal address XADD increases by 1 such as 0, 1, 2, 3,..., The converted vertical address XADD ′ changes to 0, 0, 1, 2,. The same applies to the vertical address YADD. Since the image data is read from the frame memory 34 in accordance with the read addresses XADD ′ and YADD ′, the image is enlarged and displayed as shown in FIG. 12 (B3).
[0057]
Note that the values of Kx and Ky can be set to arbitrary values independently of each other.
[0058]
(4) If a high-speed read / write memory such as a synchronous DRAM is used as the frame memory 34, the image signal can be read / written at high speed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a liquid crystal projector according to a first embodiment of the invention.
FIG. 2 is an explanatory diagram showing functions of the video scaler 36;
3 is a block diagram showing an internal configuration of a video scaler 36. FIG.
FIG. 4 is an explanatory diagram showing the contents of a resolution determination table.
FIG. 5 is an explanatory diagram showing a waveform of a composite video signal.
6 is a block diagram showing an internal configuration of a scaling unit 70. FIG.
FIG. 7 is a timing chart showing a vertical address forming operation.
FIG. 8 is an explanatory diagram showing a state of video enlargement.
FIG. 9 is a timing chart showing a horizontal address forming operation.
10 is a block diagram showing an internal configuration of a latch failure removal circuit 150. FIG.
FIG. 11 is a block diagram showing a configuration of a down converter as a second embodiment of the present invention.
FIG. 12 is an explanatory diagram showing a method for enlarging / reducing an image by multiplying a read address by a coefficient K.
[Explanation of symbols]
20 ... CPU
22 ... Main memory
24 ... Input panel
26: Frequency determining unit
28: Resolution determination unit
32 ... A / D converter
34 ... Frame memory
36 ... Video Scaler
38 ... LCD driver
40 ... LCD panel
42 ... Light source
50: Color conversion unit
52. Write synchronization signal generator
54 ... FIFO buffer
56 ... DRAM controller
58 ... Address controller
60 ... CPU access controller
61, 62 ... FIFO buffer
64: Filter section
66 ... color conversion unit
68. Read synchronization signal generator
70: Scaling unit
100: Personal computer
142 ... PLL circuit
144: Frequency divider
146: Horizontal address forming section
148 ... Vertical address forming section
150 ... Latch miss elimination circuit
152 ... Counter
154 ... Latch
156 ... Counter
158 ... Latch
162: Inverter
164: Data latch
170 ... delay part
172 ... EXNOR circuit
174 ... D-type flip-flop
200 ... Video signal selection section
202 ... Video encoder
204 ... Television
206: Video player
208 ... CD-RAM

Claims (5)

A resolution determination table for storing the relationship between the frequency of the synchronizing signal of the video signal and the resolution;
Resolution determination means for determining the resolution of the video signal to be scaled based on the relationship between the frequency and resolution of the synchronization signal stored in the resolution determination table;
When the video signal is read from the frame memory, the video represented by the video signal is enlarged in the vertical and horizontal directions at a non-integer multiple magnification so that the resolution of the video signal matches the resolution of the display device. Scaling means to convert;
With
The resolution determination table stores a case where a plurality of different frequencies correspond to the same resolution,
The vertical and horizontal ranges of the read address when reading the video signal from the frame memory are set according to the resolution of the video signal,
The scaling means includes
Means for calculating a reciprocal of horizontal magnification and a reciprocal of vertical magnification determined by a ratio between the resolution of the display device and the resolution of the video signal ;
By multiplying the reciprocal of the horizontal magnification and the reciprocal of the vertical magnification by the readout addresses in the horizontal direction and the vertical direction at the same magnification display, respectively, the values are converted into integers, so that the horizontal and vertical readout addresses for enlarged display are displayed. Each of which generates
Video scaler, characterized in that it comprises a. The video scaling device according to claim 1, comprising:
The video scaling device, wherein the resolution determining means determines a resolution of a video signal based on a frequency and a period width of the synchronization signal. The video scaling device according to claim 1, comprising:
The video scaling device, wherein the resolution determination means determines the resolution of the video signal based on the frequency of the synchronization signal and the presence or absence of interlace. A light source;
The video scaling device according to any one of claims 1 to 3,
Display device with.   The display device according to claim 4, wherein the display device is a projector.

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