JPH1195728A - Liquid crystal display controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to display a video signal of high resolution with a satisfactory picture quality, by reading out data of the video signal stored in a frame memory for every liquid crystal panel at a speed readable data equivalent to one frame in one cycle of a converted vertical synchronizing signal and supplying them to corresponding data driving circuits. SOLUTION: An STN interface controller 0103 performs the conversion of a digital video signal and stores display data to be included in the digital video signal in a frame memory 0108. Then, the controller 0103 converts a captured vertical synchronizing signal into a vertical synchronizing signal having a frequency being N times the frequency of the vertical synchronizing frequency and supplies the converted synchronizing signal to two scanning driving circuit commonly. Moreover, the controller 0103 reads out data of the video signal stored in the memory 0108 every liquid crystal display panel data at the speed capable of reading out data equivalent to one frame of the converted vertical synchronizing signal to supply them to the corresponding data driving circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display control device which takes in a video signal and a synchronizing signal, converts them, and displays them on a liquid crystal panel. The present invention relates to a liquid crystal display control device for displaying a video signal that is not performed.

[0002]

2. Description of the Related Art As a technique for causing a simple matrix type liquid crystal panel to display a video signal that does not correspond to the liquid crystal display section, there is a technique disclosed in, for example, JP-A-8-87247. . As shown in FIG. 17, the image display device described in this publication has a liquid crystal display unit 1709 having a simple matrix type liquid crystal panel and a driving circuit therefor.
And a frequency conversion circuit 1702 that converts the synchronization signal S1 and the display data S2 supplied from the electronic device 1703 and outputs the converted data to the liquid crystal display unit 1709.

The frequency conversion circuit 1702 comprises a FIFO memory 1704, a write control circuit 1705, a clock generation circuit 1706, a display timing generation circuit 1707, and a read control circuit 1708. The write control circuit 1705 writes the input display data S2 into the FIFO memory 1704 according to the input synchronization signal S1. In parallel with this, as shown in FIG. 18, the display timing generation circuit 1707 generates a synchronization signal S5 (100 to 300 Hz) having a higher frequency than the input synchronization signal S1 (including a vertical synchronization signal of 40 to 70 Hz). The read control circuit 1708 also sequentially reads the display data of the FIFO memory 1704 at a frequency higher than the writing speed in response to the synchronization signal S5, and outputs it as display data S7.

The driving circuit of the liquid crystal display section 1709 performs display on a simple matrix type liquid crystal panel according to the synchronization signal S5 and display data S7 output from the frequency conversion circuit 1702. At this time, the drive circuit sequentially applies a selection pulse to each scanning line of the liquid crystal panel according to the horizontal synchronization signal included in the synchronization signal S5, and applies a gradation voltage corresponding to the video signal S7 to the data line. Then, the display for one screen is performed at the cycle of the vertical synchronization signal included in the synchronization signal S5. Thus, a high-contrast image can be displayed on the liquid crystal panel.

[0005]

However, in the above prior art, a simple matrix type liquid crystal panel is used in one screen configuration, and all the scanning lines of the liquid crystal panel are selected in one cycle of the speeded-up vertical synchronizing signal. . For this reason, if the number of scanning lines of the liquid crystal panel is increased in order to cope with high-resolution (large-capacity) display, there is a problem that the selection time of each scanning line cannot be sufficiently secured and the image quality deteriorates.

Further, in order to increase the speed of all synchronization signals including the data clock, the frequency conversion circuit and the driving circuit have many portions that operate at a high frequency, and a complicated delay design is required. For this reason, the realization cost increases.

Therefore, the present invention provides a liquid crystal display control device which converts a high-resolution video signal which does not correspond to the liquid crystal display section by a configuration which does not include many high-frequency operation parts, and displays it with good image quality. The purpose is to:

[0008]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention captures a video signal consisting of a group of synchronization signals including a vertical synchronization signal, a horizontal synchronization signal, and a data synchronization signal, and an image signal, and converts the image into an image. A liquid crystal display control device for displaying, comprising two liquid crystal panels of a simple matrix type arranged adjacent to each other, two sets of a scanning drive circuit and a data drive circuit for individually driving each of the liquid crystal panels, and a captured image. An interface controller that converts a signal and supplies the data to the scan drive circuit and the data drive circuit; and a frame memory into which data of the captured image signal is sequentially written. Is converted to a vertical synchronization signal having a frequency N times (N is a real number of 2 or more) of the vertical synchronization signal, and the converted vertical synchronization signal is converted. Means for supplying commonly to said two scan driving circuits No., data of the stored video signal to said frame memory, 1 of the converted vertical synchronization signal
A liquid crystal display control device comprising: means for reading data for each liquid crystal panel at a speed at which data can be read for one frame in a cycle, and supplying the read data to a corresponding data drive circuit.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display system according to an embodiment of the present invention. This liquid crystal display system is an example in which an active matrix digital video signal 0102 is converted and displayed on an STN liquid crystal panel 0109 having a two-screen configuration. The image quality is improved by setting the frame rate at the time of display (the speed at which the display of one screen is repeated) at least twice the video signal 0102.

In FIG. 1, reference numeral 0101 denotes a system main body such as a computer, etc., 0103 denotes an STN interface controller for converting a digital video signal,
06 is an FRC in which gradation data for gradation control is stored.
A setting memory 0108 is a frame memory for storing display data included in the digital video signal, and 0109 is an STN liquid crystal panel having a two-screen configuration (upper screen, lower screen).

The above components other than the system main unit 0101 constitute a liquid crystal display control device. Among them, the STN interface controller 0101 is realized by a one-chip LSI (large-scale integrated circuit). Also, FRC
The setting memory 0106 is realized by a flash memory. Of course, all of the above components including the system main unit 0101 may be arranged in one housing.

The system main unit 0101 outputs an active matrix type TFT digital video signal 0102. The TFT digital video signal 0102 includes an input synchronization signal (vertical synchronization signal, horizontal synchronization signal, and data synchronization signal) in addition to the display data.

STN interface controller 0
103 captures the TFT digital video signal 0102, converts it into an STN digital video signal 0104 suitable for an STN liquid crystal panel 0109 having a two-screen configuration, and outputs it. The STN digital video signal 0104 includes an output synchronization signal (vertical synchronization signal, horizontal synchronization signal, data synchronization signal), and display data and a display period signal corresponding to each screen of the liquid crystal panel 0109. As shown in FIG. 2, the STN interface controller 0103 converts the XGA mode video signals (1024 × 76) having different resolutions into TFT digital video signals 0102.
8 pixels) and an SVGA mode video signal (800 × 60
0 pixels) can be displayed.

As shown in FIG. 19, the STN liquid crystal panel 0
The upper screen 1900 of the 109 is driven by the scanning driver 1902 and the data driver 1904. Lower screen 1
901 is driven by a scan driver 1903 and a data driver 1905. Each data driver receives a plurality of levels of grayscale voltages from a power supply circuit (not shown) and applies grayscale voltages at levels corresponding to the acquired display data to the data lines. Each scan driver applies a selection pulse to a scan line to be displayed.

STN interface controller 0
Reference numeral 103 denotes a mode setting circuit 1910 for performing mode setting as a main functional block as shown in FIG.
And a vertical synchronization control circuit 1 for generating a vertical synchronization signal
920, a horizontal synchronization control circuit 1930 for generating a horizontal synchronization signal, a display access control circuit 1940 for accessing a frame memory, and an FRC access control circuit 1950 for accessing an FRC setting memory.
And an FRC control circuit 1960 for controlling the gradation display of the display data, and a display division control circuit 1970 for responding to a change in the number of lines of the display data.

The vertical synchronization control circuit 1920 generates and outputs a vertical synchronization signal at a higher speed than the received vertical synchronization signal based on the input synchronization signal received from the system main unit 0103. The vertical synchronizing signal is commonly supplied to various drivers of the liquid crystal panel 0109. In the present embodiment, the speed of the vertical synchronization signal generated by the mode setting data or the like captured by the mode setting circuit 1910 is:
It becomes one of twice, 2.5 times and 3 times the accepted vertical synchronizing signal. Therefore, even on the display of the liquid crystal panel 0109,
The frame rate becomes one of 2 times, 2.5 times, and 3 times, and high-quality display is performed.

The horizontal synchronization control circuit 1930 generates and outputs a horizontal synchronization signal having a speed higher than that of the received horizontal synchronization signal based on the input synchronization signal received from the system main unit 0103. The horizontal synchronizing signal is also commonly supplied to various drivers of the liquid crystal panel 0109. The speed of the generated horizontal synchronizing signal is one or more times the speed of the received horizontal synchronizing signal due to the mode setting data and the like fetched by the mode setting circuit 1910. 2 frame rates
In the case of double, the speed of the horizontal synchronizing signal becomes one time. When the frame rate becomes 2.5 times or 3 times, the speed of the horizontal synchronizing signal becomes higher than 1 time. The speeding up of the horizontal synchronizing signal is realized by shortening the retrace period (a period during which valid display data is not output).

Here, the data synchronization signal received from the system main unit 0103 is used as a reference clock for driving a circuit in the STN interface controller 0103. Each data driver of the liquid crystal panel 0109 is also supplied with a data synchronization signal having the same speed as this as a data transfer timing signal. Even when the horizontal synchronizing signal is speeded up, all the valid display data can be displayed in one frame period without speeding up the data synchronizing signal in order to shorten the retrace period.

The FRC control circuit 1960 holds the gradation pattern data read from the FRC setting memory 0106 by the FRC access control circuit 1950 in an internal register, and according to a pattern designated by the gradation pattern data.
By changing the value of the display data received from the system main body 0103, the display of the intermediate gradation is performed. Specifically, display of one input display data is performed in a plurality of frames, and at least two display data corresponding to the display data are selectively output. Thereby, for example, the number of gradation levels of input display data is
Even when the number of gradation levels (the number of gradation voltage levels) that can be displayed by normal driving of the liquid crystal panel 0109 is larger, display of an intermediate gradation corresponding to input display data can be performed. Note that this function can also be used as a function for correcting the display characteristics of the liquid crystal panel 0109.

The display access control circuit 1940 uses the FRC
The display data subjected to the gradation control by the control circuit 1960 is sequentially stored in the frame memory 0 for one frame for each scanning line.
Write to 108. In parallel with this operation, the display data of the upper screen and the display data of the lower screen are individually read from the frame memory 0108 according to the output synchronization signal, and the corresponding data drivers 1904 and 1905 are read.
Output to Here, the reading of each display data of the upper screen and the lower screen is started from a predetermined start address for each of the upper screen and the lower screen. The start address of the lower screen is obtained by adding the capacity of all the display data of the upper screen to the start address of the upper screen. Display period control circuit 1
970 detects the number of effective display lines of the TFT digital video signal 0102 from the input synchronization signal, and when the number of effective display lines changes, calculates the display periods of the upper screen and the lower screen in one frame by calculation. Then, a display period signal for designating each display period is output to each data driver of the upper screen and the lower screen.

A mode setting circuit 1910 provides an address signal to an address terminal of the frame memory 0108,
Connected to the terminal of SI0103, and when the system starts up,
Various setting data are fetched from the terminal and held in an internal register. Thereafter, the terminal is opened for outputting the address signal. The mode setting data held in the register is supplied to the corresponding component. The mode setting data includes a display mode (XGA, SVGA) and a double speed mode for specifying how many times the frame rate is to be increased.

Next, the operation of the liquid crystal display control device will be described.

When the system is started, the mode setting circuit 191 is set in the STN interface controller 0103.
The mode setting data is taken in by 0. As a result, the gradation pattern data is read from the FRC setting memory 0106l by the FRC access control circuit 1950, and is written in the table in the FRC control circuit 1960.

Thereafter, the TFT digital video signal 0102
Is started, the vertical synchronizing control circuit 1920 and the horizontal synchronizing control circuit 1930 generate a vertical synchronizing signal and a horizontal synchronizing signal forming an output synchronizing signal based on the input synchronizing signal of the TFT digital video signal 0102. , STN
Output to various drivers of the liquid crystal panel 0109. Here, when the double speed mode is designated by the mode setting,
The speed of the vertical synchronizing signal is doubled, and the speed of the horizontal synchronizing signal remains unchanged. According to the supplied output synchronization signal,
Upper and lower screen scan drivers 1902 and 1
903 sequentially scans the scanning line from top to bottom at the same timing, and repeats this.

On the other hand, the display data included in the TFT digital video signal 0102 is subjected to gradation display control by the FRC control circuit 1960, and then the display access control circuit 1940.
Are sequentially written into the frame memory 0108. In parallel with this, the display access control circuit 1940
Reads the upper screen display data and the lower screen display data of the STN liquid crystal panel 0109 individually from the frame memory 0108 in accordance with the output synchronization signal. This display data
Corresponding screen data drivers 1904 and 1905
Is output to

The display data is transferred to the data driver 190
4 and 1905 are fetched in accordance with the supplied output synchronization signal and held in line units. Then, a gray scale voltage corresponding to the display data of the scan line selected by the scan driver is applied to the data lines all at once. As a result, display is simultaneously performed on one scanning line of the upper screen 1900 and the lower screen 1901 of the liquid crystal panel. The lines to be displayed are sequentially shifted, so that the output vertical synchronizing signal 1
In the cycle, as shown in FIG.
9 is displayed on the entire surface.

Here, when the TFT video signal 0102 is changed from the SVGA mode to the XGA mode, for example,
The display period control circuit 1970 detects a change in the number of effective display lines (768 → 600 lines), and subtracts the total number of display lines on the upper screen from the number of effective display lines as the number of display lines on the lower screen. . Then, a display period corresponding to each display line number is designated to the data driver by the display period signal. Accordingly, the image is not separated between the upper screen and the lower screen as shown in FIG. 9B, and the invalid display data of the frame memory 0108 is not displayed, and the image shown in FIG. In this way, continuous display can be performed. As described above, in the liquid crystal display control device of the present embodiment, it is possible to perform display with good image quality by using the data synchronization signal as the reference clock without changing the speed.
Since it is not necessary to increase the speed of the data synchronization signal, there is no need to operate the internal circuits and various drivers at a high speed corresponding to the frame rate, and there is no need for complicated delay design.
Thereby, the liquid crystal display control device can be realized at low cost.

When the number of lines of the input video signal 0102 changes, the display periods of the upper screen and the lower screen are obtained by calculation, and display control is performed individually for each screen.
Normal display can be performed according to the change in the number of lines of the input video signal.

The STN interface controller (LSI) 0103 outputs an address signal,
Since the mode setting data can be fetched at a common terminal, the total number of terminals can be reduced. This is LS
The size of I0103 can be reduced.

Further, the STN interface controller 0103 realizes all the functions described above by the operation of a pure hardware circuit. For this reason, compared to the case where the above-described various functions are realized by program control,
Processing delay can be reduced, and it can be realized easily and inexpensively.

Hereinafter, a more specific method of realizing the main part will be described.

First, the principle of speeding up the output synchronizing signal in this embodiment will be described.

As a video signal for a liquid crystal display device, XG
The A mode and the SVGA mode are mainstream. The period of the input synchronization signal is the total number of horizontal clocks (horizontal synchronization signal 1).
It is the product of the total number of clocks of the data synchronization signal per cycle) and the total number of vertical lines (the total number of clocks of the horizontal synchronization signal per one cycle of the vertical synchronization signal). As shown in FIG. In the dot period, the SVGA mode is a 1040 × 666 dot period. However, the number of valid display data is 1024 × 768 dots in the XGA mode and 800 × 600 dots in the SVGA mode. Each remaining period is a retrace period. The number in the parentheses in the figure indicates the number of clocks when the display data is transferred in pairs.

Here, for example, if two dot periods (clocks) are reduced per one cycle of the horizontal synchronizing signal, XGA, S
In each mode of the VGA, as shown in the following expression, [one vertical line period + approximately 300 clock periods] can be set as an idle period. In the present embodiment, such an empty period is used as a period for displaying the next frame ahead of time.

XGA mode: (806 × 2) ÷ 1326 ≒ 1.26 → 1 horizontal line period + 286 clock periods (Equation 1) SVGA mode: (666 × 2) ÷ 1038 ≒ 1.28 → 1 horizontal (Line period + 294 clock period) (Equation 2) However, realizing the operation of the above equation by a circuit is not realistic because the circuit scale becomes enormous. Therefore, in the present embodiment, the output horizontal cycle (the cycle of the horizontal synchronization signal of the output synchronization signal) is obtained by the following equivalent equation, and the output synchronization signal is generated based on the obtained output horizontal cycle.

Output horizontal period = [(total number of input horizontal clocks−α) + (total number of input lines−input number of display lines−β)] ÷ double speed mode γ (Equation 3) The cycle is recalculated only when the number of lines in one input frame fluctuates so that the cycle is always stable even if the input horizontal cycle fluctuates. This is to prevent display unevenness due to variation in the selection / non-selection period of the STN liquid crystal driver due to the fluctuation of the output horizontal cycle. Further, α and β in the above equation are fixed values due to securing of the retrace period and circuit operation restrictions. In the present embodiment, α is set to 10 and β is set to 4. By subtracting (the total number of input lines−the number of input display lines) in the above equation, the input retrace period is converted into the number of output horizontal clocks, and the retrace period of the output synchronization signal is compressed. Further, the double speed mode γ in the above equation takes values of 1, 1.25, and 1.5, respectively, corresponding to the double speed mode, the 2.5 speed mode, and the triple speed mode specified by the mode setting.
The reason why the value is set to half the value of each double speed mode is that the double speed is already performed by the STN interface because the upper and lower two screens are simultaneously scanned.

FIG. 3 shows a schematic configuration of the horizontal synchronization control circuit 1930.

In FIG. 3, reference numeral 0301 denotes a line number mismatch detecting function unit for each input one frame period, and 0302 denotes an input 1
Clock number detection function unit during horizontal period, 0303 is input 1
A vertical blanking period detection function unit during a frame period, 0304 is an output horizontal period calculation clock generation function unit, 0305 is an output horizontal period calculation circuit 1 function unit, 0306 is the same calculation circuit 2 function unit, and 0307 is the output horizontal period function unit. The output horizontal synchronizing signal generation function units for generating a horizontal synchronizing signal based on the operation results of the arithmetic circuit 1 function unit 0305 and the arithmetic circuit 2 function unit 0306 are shown.

An outline of the operation of the horizontal synchronization control circuit 1930 is as follows.
This will be described with reference to the timing chart of FIG. First, the line number mismatch detection function unit 0301 determines the number of lines in one input frame (IVTIME) input for each frame, and 1
The previous frame line number (A) is compared, and if the comparison result (B) does not match, the line number of the current frame is latched and at the same time, the input horizontal cycle detection function unit 0302 is latched.
And outputs a line number mismatch signal for one frame period. With this mismatch signal, the input horizontal cycle detection unit 0302
The number of input horizontal clocks from the input horizontal counter is latched (D) and held for one frame period during which the mismatch signal is valid. Based on this latched input horizontal clock number (D),
The arithmetic processing according to the above equation 3 is performed by hardware.

In this calculation process, first, the number of clocks α (10 in this example) for securing the output retrace period is subtracted from the number of input horizontal clocks (D). Output. Vertical blanking period detection function unit 03
03, the number of lines in one input frame (IVTIME)
Is subtracted from the input horizontal cycle detection function unit 0302 to the result obtained by subtracting the fixed value β (4 in this example) due to the circuit operation constraint from the result obtained by subtracting the number of input display lines (LIVDSPCNT) from (ie, the vertical blanking period). The value is added, and the result obtained by doubling or quadrupling the value is output to the output horizontal period calculation circuit 1 function unit 0305. Here, whether to select the result of 2 times or 4 times depends on the setting of the double speed mode at the time of starting the system. In the 2.5 × speed mode, 4 × is selected, and in the 3 × speed mode, 2 × is selected. Using this data,
Hereinafter, the arithmetic processing is performed. In the present embodiment, the arithmetic method based on the pull-back method using the subtraction is used. In other words, the output horizontal cycle calculation circuit 1 function unit 0305 latches the doubled or quadrupled input data at the same timing as the horizontal cycle, and thereafter, the output horizontal calculation clock generation function unit 03
A shift circuit that shifts data at the timing of the horizontal operation clock (J) output from the buffer circuit 04 is configured. The output horizontal cycle calculation circuit 2 function unit 0306 performs a subtraction process on the upper 4-bit data (K) from the output horizontal calculation circuit 1 function unit 0305 by “5” or “3”. In the subtraction processing, an addition circuit using two's complement is used. When the carry output (L) of the addition circuit is “1”, the subtraction result is positive, and when the carry output (L) is “0”, the subtraction result is negative. Indicates that Whether the subtraction process is performed at “5” or “3” is determined by the double speed mode setting at the time of starting the system. The subtraction process is performed by “5” in the 2.5 × speed mode and “3” in the 3 × speed mode. When the carry output (L) of the adder circuit is “1”, the remainder data after the subtraction is output to the output horizontal operation circuit 1.
The data is returned to the shifter circuit of the function unit 0305 and reflected in the next operation. If the carry output (L) is “0”, no data is returned. Do only. Output horizontal period calculation circuit 2 function unit 030 at the time when this shift is completed
The latch data (M) of No. 6 becomes the final output horizontal cycle setting value, which is output to the output horizontal synchronizing signal generation function unit 0307. In the output horizontal synchronization signal generation function unit 0307,
The output horizontal counter (OUTHSYNCP) is generated by comparing the latch data (M) with the output (N) of the output horizontal counter and clearing the output horizontal counter with the coincident timing signal (O).

As described above, in the 2.5 × speed mode, γ
The division by (= 1.25) is performed by quadrupling and division by “5”. In the triple speed mode, γ
Division by (= 1.5) is performed by doubling and division by "3".

When the double speed mode is the double speed mode, since the double speed is realized only by simultaneous scanning of the upper and lower screens, the input horizontal cycle is used as it is as the output horizontal cycle without using the arithmetic circuit. That is, the input horizontal counter
With the clear signal (INHCNTCLRP), clear control of the output horizontal counter of the output horizontal synchronization signal generation function unit 0307 is performed.

Next, the vertical synchronization control circuit 1920 will be described.

Table 1 shows the number of lines in one output frame and the method of processing the remaining lines in this embodiment for each double speed mode.

[0046]

[Table 1]

As shown in Table 1, in the double speed mode, the number of lines in one output frame is set to a value obtained by dividing the number of input lines in one input frame by two in order to make the input horizontal cycle equal to the output horizontal cycle. The remaining lines are assigned to the output second frame, and the input / output is completed for each frame.
Therefore, when the number of lines in one input frame is odd, the output second frame is one line more than the output first frame.

In the triple speed mode, as in the double speed mode,
Input / output is a complete operation for each frame, and the remaining lines are allocated to the third frame, which is the final output frame. However,
The number of lines in one output frame is determined by calculating the number of lines in the output horizontal cycle based on the output horizontal cycle calculation result in one input frame, and dividing the obtained number of lines by "3" into the output one frame. The number of lines in the middle.

In the 2.5.times. Speed mode, when performing the completion control for each frame, division by "2.5" is required. Therefore, the input 2 frame completion operation is performed, and division by "5" is performed. In this case, five output frames are generated for two input frames. However, if the remaining line is allocated to the fifth frame, which is the last frame, the generation cycle of the fifth frame to which the remaining line is allocated becomes two input frames. Since the cycle is longer every time, and the number of remaining lines becomes as large as 4 lines at the maximum, display quality is adversely affected. In order to avoid this problem, in the 2.5 × speed mode, the remaining lines are dispersed. That is, as shown in Table 1, the output frame to which the output frame is allocated is switched according to the number of remaining lines, and the fifth frame which is the last frame when the remaining is one line, and the second and fifth frames when the remaining is two lines. By allocating one line to the second frame when the frame has three lines, and two lines to the fifth frame when the remainder is three lines, and two lines to each of the second and fifth frames when the remainder is four lines, This suppresses the adverse effect on the display image quality due to the extra lines in the 2.5 × speed mode.

FIG. 5 shows a schematic configuration of the vertical synchronization control circuit 1920. 5, reference numeral 0501 denotes a line number mismatch detection function unit which is the same circuit as the line number mismatch detection function unit 0301 described in FIG. 3, and 0502 denotes a line number detection function unit which detects the number of output horizontal cycle lines in one input frame. ,
Reference numeral 0503 denotes an output vertical operation clock generation function unit;
Reference numeral 4 denotes a function unit of the output vertical cycle calculation circuit 1; 0505, a function unit of the output vertical cycle calculation circuit 2; 0506, a remaining line distribution circuit function unit which functions when the 2.5 × speed mode is set;
Reference numeral 507 denotes an output vertical synchronization signal generation function unit.

In the vertical synchronization control circuit 1920, first, like the output horizontal synchronization signal generation function unit described above, the line number mismatch detection function unit 0501 determines whether the number of input lines does not match (B).
= “L”, the line number detection function unit 0502
And outputs a line number capture signal (C). With this signal as a trigger, the output line number count value (E) in one input frame output from the output line number counter is newly fetched (G). The fetched output line number count value (G) in one input frame is selected at the time of setting the double speed mode and the triple speed mode, and the input line number count value (IVTIME) of the input one frame is set at the time of setting the double speed mode. select. The line number count value selected in accordance with the double speed mode setting is incremented by +1. When the double speed mode and the triple speed mode in which each frame is completed are set, they are doubled in the case of the 2.5 frame mode setting in which two frames are completed. Output vertical period operation circuit 1 function unit 050 as operation data (H)
4 is output. For the following calculation, using the method by the pullback method similar to the output horizontal synchronization signal generation function unit,
This is performed at the timing of the operation clock (O) output from the output vertical operation clock generation function unit 0503. In addition, division control of the remaining lines is performed. For this, at the end of the calculation indicating the number of remaining lines, the output vertical period calculation circuit 1 functional unit 0
This is performed by outputting the latch data (P) of 504 to the remaining line distribution circuit function unit 0506. The extra line distribution circuit function unit 0506 controls the extra line distribution for the output second frame when the 2.5 × speed mode is set. Therefore, the distribution of the remaining lines to the last frame in all the double speed modes shown in Table 1 is determined by the output synchronization signal selection switching signal (Y) output from the output vertical operation clock generation function unit 0503, and the next input vertical Synchronous signal (W)
Is output as an output vertical synchronization signal (OUTVSYNCP) (input / output synchronization). The distribution control of the remaining lines for the output second frame in the setting of the 2.5 × speed mode is performed by comparing the latch data (P) with “2”, “3” and “4”. Therefore, if it matches “2” or “3”, the output vertical cycle calculation value (S) output from the output vertical cycle calculation circuit 2 functional unit 0505 at the timing of the output second frame is “1”. The output vertical synchronization signal generation function unit 05
At step 07, the value obtained by adding "1" is compared with the count value (T) of the output vertical counter, and an output vertical synchronization signal (OUTVSYNCP) is output at the same timing. If the total number of remaining lines matches "4", "2" is added to the output vertical cycle calculation value (S) at the timing of the output second frame. In this way,
The output vertical cycle setting value obtained by adding the remaining line distribution value for each double speed setting mode to the output vertical cycle (S) obtained by the output vertical cycle calculation circuit 1 function unit 0504 and the output vertical cycle calculation circuit 2 function unit 0505 By using the generated output vertical synchronization signal (OUTVSYNCP), it is possible to generate an output frame frequency in which the input frame frequency is increased,
High-quality display of a simple matrix type liquid crystal panel can be realized.

Next, the display period control circuit 1970 will be described.

FIG. 10 shows a schematic configuration of the display period control circuit 1970. In FIG. 10, reference numeral 1001 denotes an input valid display line number counter for counting the number of video data valid display lines in one input frame, and 1002 denotes a count value (LIVDD) of the input valid display line number counter 1001.
SPCNT) and the specified number of lines for each display mode (XGA
768 lines for mode, 60 for SVGA mode
1003 is a display screen separation prevention circuit enable signal due to insufficient lines, 1003
4 is an output vertical counter that counts in the output horizontal cycle,
Reference numeral 1005 denotes an upper / lower screen display pulse width in the normal display mode, and an upper screen display pulse width generation function unit (hereinafter, referred to as a screen display pulse width generation function unit 1) in the line shortage mode.
Reference numeral 1006 denotes a lower screen display pulse width generation function unit (hereinafter referred to as screen display pulse width generation function unit 2) in the line shortage mode, 1007 denotes a lower screen display pulse width generation signal selector function unit, and 1008 and 1009 denote upper and lower screens, respectively. Each of the display pulse and latch function units is shown.

First, a circuit for preventing display screen separation due to a shortage of input lines is set to an effective state by setting a mode at the time of system startup (LCHKMODEN = “L”). Thus, the count value (LIV) of the input display line number counter 1001 based on the input display line signal (DSPTMG) is obtained.
DSPNT) and either “768 (XGA mode)” or “600 (SVGA mode)” are compared by the comparator 1002, and when the count value is smaller, a signal indicating the line shortage mode ( LINE
EMPP = "H") becomes effective. Whether the display mode is XGA or SVGA also depends on the mode setting at the time of starting the system. Here, X
GA mode as an example (XGAMODEP = "H"), 76
It is assumed that the number of lines is less than eight. Therefore, the assertion of the upper screen display pulse (OUTVDSPP) and the assertion of the lower screen display pulse (OUTLVDSPP) are equal at the timing of clearing the output vertical counter 1004. Next, the clear timing of the upper screen display pulse is controlled by the screen display pulse width generation function unit 11005, and is performed when the counter value of the output vertical counter 1004 becomes 384. Is controlled by the screen display pulse width generation function unit 21006 selected by the selector circuit 1007, and the counter value of the output vertical counter 1004 is changed by the counter value (LIVDSP) of the input display line number counter 1001.
CNT) is subtracted from 384 (a value obtained by subtracting the number of lines displayed on the upper screen from the total number of input display lines). As a result, for the upper screen, data of 384 lines, which are all display lines, and for the lower screen, the remaining data obtained by subtracting the upper screen display line data from the input total line data is the lower screen. To display from the top,
Images without upper and lower screen separation can be provided. When the system is started, the display screen separation preventing circuit due to the shortage of input lines is set to an invalid state (LCHKMODE).
N = “H”), the control of the upper and lower screen display pulses is common, and the screen display pulse width generation function unit 210
06 is unused. In the screen display pulse width generation function unit 11005, the fixed value (384) is compared with the counter value of the output vertical counter 1004. In this mode, the total number of input display lines by the input display line number counter 1001 is used. At the timing when the value (LSIVDSPCNT) obtained by dividing (LIVDSPCNT) into two and the counter value of the output vertical counter 1004 match,
Display pulses (OUTVDSPP) for both upper and lower screens, (O
UTLVDSPP) is cleared. Therefore, if the number of display lines of the input video data is a specified value (if it is 768 lines), half of the 384 lines of pulses are generated as upper and lower screen display pulses. Display. If the number of display lines of the input video data is less than the specified value, the half value is 38
4 and thus the upper and lower screen display pulse widths are both 384.
The number of lines is less than the line, and the display is as shown in FIG.

The present embodiment further has a function of forcibly increasing the number of lines on the output side when the number of input lines is insufficient.

Table 2 shows a list of operation modes in the XGA mode when the number of input lines is insufficient for indicating this function. That is, when the display screen separation prevention circuit due to the shortage of input lines is set to an effective state (LCHKMODEN = “L”), when the number of input effective display lines is less than 768, the output horizontal synchronizing signal is generated in the double speed mode. The number of output lines during one output frame period is increased by setting the control to the 2.5 × speed mode which is one rank faster and the output horizontal synchronization signal generation control to be one rank slower in each of the 2.5 × speed and 3 × speed modes. Things. Thus, the prescribed value of the minimum number of input lines of the liquid crystal panel can be satisfied, and the range of connectable liquid crystal panels can be expanded.

[0057]

[Table 2]

Next, the FRC access control circuit 1950 will be described.

In this embodiment, an 8-bit register is used as an FRC control data setting register.
A serial memory having a configuration of 64 words × 16 bits is provided as a memory for storing setting data for all the registers. By using a serial memory, the number of terminals in an LSI can be reduced, which can contribute to high-density mounting.

FIG. 12 shows a schematic configuration of the FRC access control circuit. In FIG. 12, reference numeral 1201 denotes a mode setting function unit that controls whether data from an external serial memory is set in the FRC control unit when the system starts up.
2 is a read enable signal and chip select signal generation function unit for the serial memory when the external serial memory is enabled, 1203 is a status signal and address generation function unit for the serial memory,
Reference numeral 1204 denotes a data conversion function unit for parallel-converting serial data read from the serial memory and a register write pulse generation function unit for taking in the FRC control unit register at the end of the conversion.

First, in the mode setting at the time of starting the system, the read mode of the external serial memory is enabled (SME
MRDENP), the mode setting function unit 1
The serial memory read flag 201 becomes effective (SMRFLGP = "H"). According to the valid state of the flag signal, the read enable signal and chip select signal generation function unit 1202 causes the 8-bit counter 1
Starts. External serial memory control clock (ROM
Input horizontal synchronization signal (IHSYNC)
The counter 1 is cleared each time the count value (A) of the counter 1 counted by P) counts 30 (1Dh). That is, the input horizontal synchronization signal (I
HSYNCP) 30 cycles are the number of cycles required for one external serial memory access, and at the same time, these 30 cycles are divided into 26 and 4 cycle periods, so that a precharge 4 cycle period (4IHSYNCP)
The chip select signal (ROMCSP) is generated. Further, a read enable signal (ROMRDENP) is generated based on the decoding result of the count value (C) of the 8-bit counter 2 which counts up by the clock (B) for each decode value 30 (1Dh). That is,
This read enable signal (ROMRDENP)
Serial memory by the mode setting function unit 1201
Asserted at the timing when the read flag becomes valid (SMRFGP = “H”), the 8-bit counter 2
Is negated at the timing when the count value (C) becomes 59 (3Bh) indicating the end of data setting from the serial memory. In addition, at this negation timing,
A counter mask signal (D) for stopping the counting of the 8-bit counter 2 is made valid. When the mask signal (D) becomes valid, the control circuit stops its operation thereafter, so that a malfunction during system operation can be prevented. Further, the read enable signal (ROMRDE)
By using this control signal, the period during which NP) is valid indicates that control of the external serial memory is being performed, and the external serial memory control period at system startup and the subsequent normal operation period can be identified. Therefore, sharing of terminals can be realized. Next, in the status signal and the address generation function unit 1203, the serial memory chip select signal (ROMCSP)
Triggered by a status signal (1
Following 10), the serial memory address is output (ROMDI), and at the same time, the register address (ILA [5: 0]) of the FRC control unit is generated. In this control unit comprising a parallel / serial conversion circuit, the count value (F) of the 8-bit counter 3 which counts up by the clock (E) based on the chip select signal (ROMCSP) is taken into the parallel / serial conversion circuit. Thereafter, the serial memory control clock (ROMC
KP), serial output (ROMD) in the order of status signal (110) and serial memory address
I). At the same time, a signal obtained by subtracting 1 from the counter value (F) of the 8-bit counter 3 is output as the FRC control unit register address (ILA [5: 0]). By the control up to this point, the FRC control unit setting data (ROMDO) output from the external serial memory is converted into serial / parallel conversion by the shift clock (G) in the input data conversion function unit and the register write pulse generation function unit 1204. To convert the data into 16-bit parallel data. Here, the 16-bit parallel data means data for two registers because the configuration of the FRC control unit register is an 8-bit configuration, that is, the same address is allocated to the two registers. At the time of conversion into 16-bit parallel data, a register write pulse (MREG) is used to write data to two corresponding registers.
CSN). According to the above control, the arbitrary FRC control section setting data from the external serial memory can be provided at the time of starting the system, and the gradation display control according to the state of the input video data can be performed. If this setting mode is invalidated when the system is started, the operation is performed using the initial data of the hardware.

Next, the mode setting by the mode setting circuit 1910 will be described.

One mode setting circuit 1910 is connected to each terminal of the address signal supplied to the frame memory 0108. Table 3 shows the contents of the mode setting in each terminal of the LSI 0103. As shown in Table 3, each terminal of the address signal A [0 to 5] is also used to capture 1-bit mode setting data MODE [0 to 5]. When the external serial memory read mode is designated, the read operation of the FRC access control circuit 1950 is performed.

[0064]

[Table 3]

FIG. 14 shows the configuration of the mode setting circuit 1910. 14, reference numeral 1401 denotes a pull-up resistor for setting an H-level mode; 1402, a pull-down resistor for setting an L-level mode; 1403, a bidirectional buffer; 1404, an 8-bit counter;
Reference numerals 5 to 1407 denote decoders, reference numerals 1408 to 1410 denote latches, and reference numeral 1411 denotes an external frame memory address control unit included in the display access control circuit 1940. In practice, one of the pull-up resistor 1401 and the pull-down resistor 1402 is connected.

The operation of mode setting circuit 1910 is described with reference to FIG.
This will be described with reference to the timing chart of FIG. At the time of system startup, the output (OUTENP) of the latch 1409 becomes L level, and the bidirectional buffer 1403 is in the input state. As a result, the connected pull-up resistor 1401 or pull-down resistor 14
02 is input. Data synchronization signal I
The supply of DCLK is started, and the count value of the 8-bit counter 1404 that counts the DCLK is "32" (decimal number)
At this point, the decoder 1405 sets the latch 14
08, a latch clock is output to hold mode setting data. Thereafter, when the counter value becomes “64”, the decoder 1406 sets the output of the latch 1409 to H level, and thereafter, the bidirectional buffer 1403 is in the output state. Further, when the counter value becomes “128”, the decoder 1407 outputs the output of the latch 1410 (INRSTN).
To the H level, and the reset state of each unit in the STN interface controller 1003 is released. Thus, the external frame memory address control unit 1411
Starts the output of the address signal, and the terminal that has taken in the mode setting data becomes the output terminal of the address signal. The mode setting circuit may be connected to an output terminal other than the address signal terminal.

As described above, by using the mode setting circuit 1910, one terminal of the LSI 0103 can be used for fetching mode setting data and for outputting other data, thereby reducing the number of LSI terminals. LS
I can be downsized.

FIG. 16 is a diagram showing the overall configuration of a liquid crystal display control device according to the second embodiment of the present invention.

The liquid crystal display control device of this embodiment has an A / D converter 1602 and a TFT
An analog video signal 1601 can be captured and displayed by adding an interface controller 1604. Analog video data 160
Reference numeral 1 denotes, for example, a video signal for a CRT.

The analog video data 1601 output from the system main unit 1001 is converted into an A / D converter 1602
Is converted into digital data 1603, and is output to the TFT interface controller 1604. T
The FT interface controller 1604 converts the input digital data 1603 into a TFT digital video signal 0102 in the same signal format as the one captured by the STN interface controller 0103 in FIG.
TFT digital video signal 0102 obtained by conversion
Is output to the STN interface controller 0103 and subjected to the same processing as described in the first embodiment.

The configuration of the first embodiment is suitable for a display system such as a notebook personal computer in which the system body and the STN liquid crystal panel are integrated, while the configuration of the second embodiment is a liquid crystal display control device. Is suitable as a liquid crystal monitor and realized separately from the system body. That is, in the present embodiment, a large-capacity, high-quality display can be performed in combination with, for example, a desktop personal computer (system body) that outputs only an analog video signal.

[0072]

As described above, according to the present invention, a high-resolution video signal that does not correspond to the liquid crystal display section is converted by a configuration that does not include many high-frequency operation parts, and a good image quality is obtained. A liquid crystal display control device for displaying can be provided.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a liquid crystal display system according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing the relationship between the total number of horizontal clocks and the total number of vertical lines for a screen in XGA and SVGA modes.

FIG. 3 is a schematic configuration diagram of a horizontal synchronization control circuit.

FIG. 4 is an operation timing chart of the horizontal synchronization control circuit.

FIG. 5 is a schematic configuration diagram of a vertical synchronization control circuit.

FIG. 6 is a diagram showing operation timings in a double speed mode of the vertical synchronization control circuit.

FIG. 7 is a diagram illustrating operation timings of the vertical synchronization control circuit in a 2.5 × speed mode.

FIG. 8 is a diagram showing operation timings of the vertical synchronization control circuit in the triple speed mode.

FIG. 9 is a display image diagram of a simple matrix type liquid crystal panel with respect to the number of display lines of an input video signal.

FIG. 10 is a schematic configuration diagram of an upper and lower screen display separation prevention control circuit.

FIG. 11 is a diagram showing operation timings of the display division control circuit.

FIG. 12 is a schematic configuration diagram of an FRC control unit register setting serial memory control circuit.

FIG. 13 is an operation timing chart of the serial memory control circuit for register setting of the FRC control unit;

FIG. 14 is a schematic configuration diagram of an LSI internal various mode setting function control circuit.

FIG. 15 is an operation timing chart of an LSI various mode setting function circuit.

FIG. 16 is an overall configuration diagram showing another embodiment of the present invention.

FIG. 17 is a schematic configuration diagram of a conventional liquid crystal display system.

FIG. 18 is an operation timing chart of a conventional liquid crystal display system.

FIG. 19 is a configuration diagram of the STN interface controller of FIG. 1;

[Explanation of symbols]

0101: System main unit, 0102: TFT digital video signal, 0103: STN interface controller, 0104: STN digital video signal, 0106:
FRC setting memory, 0108 ... frame memory, 010
9 STN liquid crystal panel, 1910 mode setting circuit, 1
920: vertical synchronization control circuit, 1930: horizontal synchronization control circuit, 1940: display access control circuit, 1950: FR
C access control circuit, 1960 ... FRC control circuit, 19
70: display period control circuit, 1900, 1901: liquid crystal panel (upper screen, lower screen), 1902, 1903: scan driver, 1904, 1905: data driver.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuyuki Kudo 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside Hitachi, Ltd.System Development Laboratory (72) Inventor Satoshi Onuma 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi Image Information Systems, Ltd. (72) Inventor Tatsuhiro Inuzuka 292, Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture, Japan Stock Company Hitachi Image Information Systems, Ltd. (72) Shinji Uchida 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. Electronic Devices Division

Claims (7)

[Claims] 1. A liquid crystal display control device for capturing a video signal composed of a group of synchronization signals including a vertical synchronization signal, a horizontal synchronization signal, and a data synchronization signal, and an image signal, and displaying an image, wherein the liquid crystal display control device is arranged adjacent to the liquid crystal display control device. Two simple matrix type liquid crystal panels, two sets of scan driving circuits and data driving circuits for individually driving the respective liquid crystal panels, and converting the captured video signals to the scanning driving circuits and the data driving circuits. An interface controller for supplying the image data, and a frame memory in which data of the captured image signal is sequentially written. The interface controller converts the captured vertical synchronization signal into N times (N times) the vertical synchronization signal.
Means for converting a vertical synchronizing signal having a frequency of 2 or more) and a common supply of the converted vertical synchronizing signal to the two scan driving circuits; and a video signal data stored in the frame memory,
A liquid crystal display control device comprising: means for reading out each liquid crystal panel at a speed at which one frame can be read in one cycle of the converted vertical synchronizing signal, and supplying the read data to a corresponding data drive circuit. 2. The liquid crystal display control device according to claim 1, wherein said interface controller is means for converting the taken horizontal synchronizing signal into a higher frequency horizontal synchronizing signal with a reduced retrace period. A liquid crystal display control method further comprising: 3. The liquid crystal display control device according to claim 1, wherein the interface controller further outputs the received data synchronization signal to an internal reference clock and an image signal to the data drive circuit. A liquid crystal display control method, wherein the liquid crystal display control method is used as a data transfer timing signal. 4. The liquid crystal display control device according to claim 1, wherein said interface controller detects the number of display lines of the fetched image signal based on the fetched synchronization signal, and based on said number of lines. Means for determining the number of display lines to be allocated to each of the liquid crystal panels and controlling a display period of each of the liquid crystal panels so that continuous and normal display is performed between the two liquid crystal panels. A liquid crystal display control device, comprising: 5. The liquid crystal display control device according to claim 1, further comprising: an external memory in which various setting data for gradation display control are stored, wherein the interface controller has a storage unit, Means for autonomously reading various data in the external memory and writing it to the storage means at power-on, and changing values in a plurality of frames for data stored in the frame memory according to various setting data in the storage unit A liquid crystal display control device further comprising: an FRC unit for performing processing. 6. A video signal comprising a group of synchronization signals including a vertical synchronization signal, a horizontal synchronization signal, and a data synchronization signal and a video signal, and two adjacently arranged simple matrix type liquid crystal panels are arranged. Two sets of scan drive circuits and data drive circuits that are individually driven, and a frame memory that stores the data of the captured image signal, and converts the captured video signal so that the scan drive circuit and the data drive An interface controller for supplying a vertical synchronizing signal to an N-fold (N
Means for converting the data into a vertical synchronization signal having a frequency of 2 or more) and reading out the data stored in the frame memory for each liquid crystal panel at a speed of reading one frame in one cycle of the converted vertical synchronization signal. An interface controller having means for distributing the data to a corresponding data drive circuit, and realized by a one-chip integrated circuit. 7. The interface controller according to claim 6, wherein said interface controller is connected to a bidirectional terminal of said integrated circuit,
Take in data for mode setting from the terminal, hold it,
Hereinafter, an interface controller further comprising means for opening the terminal for data output.