JPH11338424A - Liquid crystal controller and liquid crystal display device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize conversion of frame frequency of a display signal and gradation display process by FRC with a smaller capacity memory by switching a pattern of generated pattern signals according to the output order of a frame formed by binary display data output after conversion. SOLUTION: The input gradation data is individually converted to FRC data by the respective FRC processing parts A-C. In the respective memory areas A-C, FRC data converted by FRC processing parts A-C is sequentially written for each one frame, and after that, FRC data is read at double the speed of write operation. The above operation is repeated. The gradation data (input data) is converted to FRC data (output data) having a double frame period. Here, the operation periods (write operation and read operation) of the respective memory areas A-C are respectively shifted only by half the period of the input frame.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal controller for converting input display data into display data of a format suitable for a liquid crystal panel to be used, and more particularly to making a STN liquid crystal panel perform gradation display. It relates to a suitable liquid crystal controller.

[0002]

2. Description of the Related Art Conventionally, in a simple matrix type STN liquid crystal panel, a driving frame frequency for obtaining an optimum contrast is about 90 Hz to 180 Hz. This frequency is higher than the frame frequency (60 to 75 Hz) used in CRT devices and TFT liquid crystal panels. Therefore, S
In a liquid crystal display device using a TN liquid crystal panel, in order to display a display signal for a CRT device or a TFT liquid crystal panel, a process of increasing a frame frequency using a frame memory is required.

The display method of the STN liquid crystal panel is as follows.
Binary display of display on or display off is predominant for pixels. As a technique for displaying a gray level (intermediate gray level) intermediate between display ON and display OFF for one pixel using this display method, a frame rate control (FR)
C) There is a method.

[0004] The FRC method is a method of obtaining an intermediate gradation by adjusting the ratio of display ON and display OFF in each pixel in this cycle with several frames as one cycle. In this FRC system, for example, as shown in FIG. 4, a pattern consisting of display ON and display OFF (hereinafter, referred to as FRC pattern) is formed in a matrix of a certain size, and this FRC pattern is formed.
A general method is to switch the RC pattern for each frame.

FIG. 12 shows a configuration example of a conventional liquid crystal controller which realizes both the conversion of the frame frequency and the halftone processing. In this configuration, the input gradation data is stored in the frame memory for one frame, and after converting the frame frequency, the FRC processing unit performs the gradation processing.

[0006]

In the above-mentioned conventional liquid crystal controller, when performing frame frequency conversion and FRC intermediate gradation processing, gradation data for one frame is temporarily stored in a memory, and is stored in a memory. After converting the frequency,
A method of performing halftone processing is employed. For this reason, an expensive large-capacity memory that can store, for example, 8-bit grayscale data per pixel for one frame is required.

An object of the present invention is to provide a liquid crystal controller which realizes conversion of a frame frequency of a display signal and gradation display processing by FRC using a memory having a smaller capacity, and a liquid crystal display device using the same. To provide.

[0008]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method of receiving grayscale display data of a plurality of bits per pixel and a group of synchronization signals, and outputting binary display data of one bit per pixel. A liquid crystal controller for outputting a synchronizing signal group and causing a simple matrix type liquid crystal panel to perform a gradation display corresponding to the gradation display data. For each value of the gradation display data, P (P is an integer of 3 or more) FRCs for generating a pattern signal having a plurality of predetermined patterns and outputting a pattern value corresponding to the input gradation display data as binary display data
And a P which is arranged corresponding to each FRC processing unit and has a storage capacity of binary display data for one frame.
One frame of binary display data is written in each memory area at a predetermined phase in synchronization with the input synchronization signals and the memory area, and after writing, N times the writing time (N is greater than 1). A memory control unit for controlling reading of the binary display data of each memory area at a speed of (large real number), wherein each of the FRC processing units converts the pattern of the generated pattern signal into a binary display data to be output after the conversion. The liquid crystal controller is characterized in that the switching is performed in accordance with the output order of the frame constituted by.

The present invention also provides a simple matrix type liquid crystal panel, the above liquid crystal controller, and a scan driver for causing the liquid crystal panel to perform display corresponding to binary display data in accordance with a synchronization signal output from the liquid crystal controller. And a data driver.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a liquid crystal display device 100 according to a first embodiment of the present invention. As illustrated, the liquid crystal display device 100 includes a liquid crystal controller 110, a simple matrix type liquid crystal panel 120, and a scan driver 130.
And a data driver 140. Note that the scanning drivers 130 and the data drivers 140 are arranged by the number corresponding to the resolution (the number of pixels) of the liquid crystal panel 120.

The liquid crystal panel 120 has a plurality of data electrodes and scanning electrodes that intersect each other, and a plurality of STN liquid crystal cells formed at the intersections of the data electrodes and the scanning electrodes (not shown). Here, each scanning electrode corresponds to a row of the pixel array of the liquid crystal panel 120, and each data electrode corresponds to a column of the pixel array of the liquid crystal panel 120. The light transmittance of the STN liquid crystal cell changes according to the mean square of the difference between the voltages applied to the data electrodes and the scanning electrodes.

The liquid crystal controller 110 receives display data and a group of synchronization signals from an external device such as a personal computer, and outputs display data and a group of synchronization signals for displaying on the liquid crystal panel 120 to the scanning driver 130 and the data driver 140. .

Here, input display data is digital data of a plurality of bits (N bits) per pixel (hereinafter referred to as "N").
Gray scale data), and is input in pixel units via an N-bit width bus, for example. On the other hand, the output liquid crystal panel 12
The display data for 0 display is 1-bit data per pixel (hereinafter, FRC data) indicating ON display or OFF display.

The liquid crystal controller 110 converts the frame frequency. In the present embodiment, the frame frequency of the FRC data is set to two times the frame frequency of the gradation data.
In this example, the number is doubled.

The scanning driver 130 includes a liquid crystal panel 120
, And the operation of sequentially applying the voltage for enabling the display to the scanning electrodes from the first row to the last row in accordance with the synchronization signal group is repeated. On the other hand, the data driver 14
Numeral 0 is connected to the data electrode of the liquid crystal panel 120, and simultaneously applies a voltage (on display or off display voltage) corresponding to the FRC data of the row for which display is enabled to the data electrode in accordance with a group of synchronization signals. This operation is repeated to display a frame.

In the following description, it is assumed that the number of bits N of the gradation data is 8, and the gradation display for one screen is performed by 255 consecutive (2 N −1) frame displays on the liquid crystal panel 120. I do.

FIG. 2 shows the configuration of the liquid crystal controller 110.

As shown, the liquid crystal controller 110
Are the FRC processing units A202, B203, C204, the memory areas A205, B206, C207, the read data selector 208, and the liquid crystal output interface unit 20.
9 and a memory control unit 212.

The liquid crystal controller 110 generates and outputs FRC data and a synchronizing signal group (liquid crystal display signal 213) for liquid crystal panel display based on the gradation data 210 and the synchronizing signal group 211 input from an external device. . The input gradation data 210 and synchronization signal group 211 have the same contents and timing as those generated for a general TFT liquid crystal display device.

The input synchronizing signal group 211 has a V signal indicating one frame period in the transfer of the gradation data 210.
a sync signal, an Hsync signal indicating one horizontal period,
It consists of a dot clock indicating the transfer timing and a signal indicating the effective period of the transfer. Synchronous signal group to be output (21
3) has the same timing as that generated by a general STN liquid crystal display device, and is composed of the same type of synchronization signals as the synchronization signal group 211 described above.

Each of the FRC processing units A to C receives 8-bit gradation data 210 per pixel and outputs 1-bit FRC data (ON display / OFF display).

Each of the memory areas A to C has a storage capacity for storing one frame of FRC data. In each of the memory areas A to C, one frame of FRC data output from the FRC processing units A to C is written by a control signal from the memory control unit 212, and then read.

The data selector 208 selects the synchronization signal group 21
1, the FRC data read from the memory areas A to C is selected and output. At this time, the output FR
The C data is arranged in accordance with the pixel arrangement of the liquid crystal panel 120.

FIG. 3 shows the configuration of each of the FRC processing units A to C. As shown, each FRC processing unit A, B, C
C pattern generator 301 and FRC pattern selector 3
03.

The FRC pattern generator 301 determines each value (0 to 25) of the gradation data according to the synchronization signal group 211 described above.
An FRC pattern signal group 302 including 256 FRC pattern signals corresponding to 5) is generated and output. Each F
The RC pattern signal is a two-level (low / high) signal, and changes in a predetermined pattern.

[0027] The FRC pattern selector 303
256 FRs generated by the pattern generator 301
An FRC pattern signal corresponding to the value of the input gradation data 210 is selected from the C pattern signals (302), and the value is output as FRC data.

The FRC pattern signal group 302 will be described in more detail.

Each FRC pattern signal of the FRC pattern signal group 302 has a different high period ratio. An FRC pattern signal corresponding to a larger gradation data value has a higher ratio of a high period (hereinafter referred to as a gradation ratio). For example, low of the FRC pattern signal corresponds to off display, and high corresponds to on display.

Each F of the FRC pattern signal group 302
The RC pattern signal has 255 types (2 N -1 types) of patterns per gradation. Each FRC pattern generation circuit 301 controls the FR
The pattern of the C pattern signal group 302 is switched,
The change of the pattern is advanced in synchronization with the dot clock of the gradation data.

A specific example of the FRC pattern signal will be described using a simple model. Here, it is assumed that six gradations are displayed with five frames as one cycle.
FIG. 4 shows a display example when a uniform gray display with a gradation ratio of 4/5 is performed on the liquid crystal panel. In this example, one frame is 5
It is equally divided into pixel blocks in rows and 5 columns, and the same display is made in each pixel block in the frame. For simplification, only one pixel block is shown as a frame in the figure.

The display is performed in the order of frames 1, 2, 3, 4, and 5. When the value of the gradation data does not change, the display is repeated in the same order. By dispersing the ON display and the OFF display as shown in the figure, a display with less flicker can be realized.

In this display, an FRC pattern signal having a gradation ratio of 4/5 is continuously selected, and the signal value becomes FRC data. As shown, this FRC pattern signal is
The pattern is generated so as to be different between frames to be displayed. That is, the FRC pattern signal has five patterns corresponding to each of the frames 1 to 5. Note that these FRC pattern signals are
Since it can be generated by controlling the phase of one periodic signal (0, 1, 1, 1, 1), it can be generated by a circuit having a simple configuration.

The FRC pattern signals of other gradation rates have the same characteristics except that the ratio of the high period is different.

In the present embodiment for displaying 256 gradations, F
The RC pattern signal is the FR of the 6 gradation display described above.
This is an extension of the C pattern signal. That is, in this embodiment, one frame is displayed by displaying 255 consecutive frames.
Since the gradation display for the screen is performed, each FRC pattern signal has 255 types of patterns, and one of the patterns is selected according to the output order of the FRC data frame.

Next, the liquid crystal controller 11 of the present embodiment
The operation of 0 will be described.

FIG. 5 is a timing chart of the memory control in the liquid crystal controller 110. In the figure, 1_i
, 2_in,... are input gradation data 21
Indicates a frame of 0 (input data). 1W_FRC, 2
W_FRC,... Indicate frames of FRC data that are output to and written in the respective memory areas A, B, and C. 1
R_FRC, 2R_FRC,... Indicate frames of FRC data (output data) read from and output from the respective memory areas A, B, and C.

The input gradation data is individually converted into FRC data in each of the FRC processing units A, B and C. Each of the memory areas A, B, and C is an FRC processing unit A, B,
The FRC data converted by C is sequentially written for one frame, and then the FRC data is read at twice the speed of the write operation. Then, this operation is repeated.
Here, the operation cycle (write operation and read operation) of each of the memory areas A, B, and C is shifted by a half period of the input frame.

That is, as shown in FIG.
The _in gradation data is converted into FRC data of the frame 1W_FRC in the FRC processing unit A, and is written to the memory area A.

The gradation data of the second half of the frame 1_in and the first half of the frame 2_in are processed by the FRC processing section B in the frame 2
The data is converted into FRC data of W_FRC and written to the memory area B. On the other hand, during the period in which the first half gradation data of the frame 2_in is input, the FRC data for one frame in the memory area A is sequentially read, and the frame 1
It is output as FRC data of R_FRC.

The gradation data of the frame 2_in is expressed by FRC
In the processing unit C, the data is converted into FRC data of the frame 3W_FRC and written to the memory area C. On the other hand, during the period when the second half gradation data of the frame 2_in is input, the FRC data for one frame in the memory area B is sequentially read and output as the FRC data of the frame 2R_FRC.

The gradation data of the latter half of the frame 2_in and the first half of the frame 3_in are processed by the FRC processor A in the frame 4
The data is converted to FRC data of W_FRC and written to the memory area A. During the period in which the first half gradation data of the frame 3_in is input, the 1
FRC data for a frame is sequentially read and output as FRC data for frame 3R_FRC.

The above operation is repeated, and the gradation data (input data) is converted into FRC data (output data) having a double frame period.

To make the arrangement of the FRC data read from the memory conform to the pixel arrangement of the liquid crystal panel 120, the memory control unit 212 performs two types of address control for each of the memory areas A, B, and C. Do.

When the write / read target FRC data corresponds to one normal frame of gradation data (for example,
In 1W_FRC, 1R_FRC), addresses in the same order are generated in the write operation and the read operation, and the FRC data is read in the order in which the writing was performed.

On the other hand, when the FRC data to be written / read corresponds to the latter half and the first half of two consecutive frames (for example, 2W_FRC, 2R_FRC), addresses in different orders are generated for the write operation and the read operation. The FRC data is read in the first half and second half of the frame. For example, as the frame 2R_FRC, first, FRC data corresponding to the first half of the frame 2_in is output, and subsequently, FRC data corresponding to the second half of the frame 1_in is output.

By the address control, the FRC data output from the data selector 208 is, for example, in each output frame 1R_FRC, 2R_FRC,. Column,..., Second row, first column, second row, second column,.
・ The order is the last row, last column.

The FRC data of the output frame is input to the liquid crystal output interface unit 209 via the read data selector 208. LCD output interface 2
Reference numeral 09 outputs the input FRC data and a synchronizing signal group synchronized therewith as a liquid crystal display signal 213.

Next, the pattern switching control of the FRC pattern signal group 302 will be described with reference to the display of the gradation ratio 4/5 shown in FIG. 4 as an example.

FIG. 6 is a timing chart of the memory control when the gradation display of FIG. 4 is performed. Here, all the gradation data of the input frames 1_in, 2_in,... Correspond to the FRC pattern signal whose gradation ratio is 4/5. Also, output frames 1R_RFC, 2R_R
FC, 3R_RFC,... Correspond to frames 1, 2, 3,.

The FRC pattern signal of the gradation rate of 4/5 generated by the FRC processing unit A202 is synchronized with the dot clock during the input period of the frame 1_in, and the frame 1 of FIG.
Changes in a pattern corresponding to. The following frame 2_in
And 3_in, the input period changes in a pattern corresponding to frame 4 three frames ahead. Then, in the input period of the subsequent frame 4_in, the pattern changes in the pattern of the frame 7 three frames ahead (the cycle is the same as the frame 2).

The FRC pattern signal of the gradation rate of 4/5 generated by the FRC processing unit B203 is input frame 1_in
And 2_in, the input period changes in a pattern corresponding to frame 2. In the input period of the subsequent input frame 3_in, the input period changes in a pattern corresponding to the frame 5 three frames ahead. Then, the following frames 4_in and 5_
In each input period of “in”, the pattern changes in the pattern of frame 8 (same as frame 3) three frames ahead.

The FRC pattern signal of the gradation rate of 4/5 generated by the FRC processing unit C204 changes in a pattern corresponding to the frame 3 during the input period of the frame 2_in. In each input period of the subsequent input frames 3_in and 4_in, the input period changes in the pattern of the frame 6 (same as the frame 1) three frames ahead. Then, in the input period of the subsequent frame 5_in, a frame 9 (frame 4
And the same pattern).

As described above, each FRC processing section performs the first operation of processing the FRC data of one entire input frame,
The second operation of processing the second half and the first half of the FRC data of one input frame is alternately repeated. In the second operation period, the same pattern is generated in two input frame periods,
When the operation period is switched, generation of a pattern three frames ahead is started.

Since the change of the display image of an external device such as a personal computer is slow, the gradation data 2 of a plurality of input frames is different from the liquid crystal display device 100 of this embodiment.
Good display is possible even if gradation display for one screen is performed using the number 10.

The liquid crystal controller 110 is realized by one LSI including a memory area. This LSI can be arranged in a liquid crystal module such as the back side of the liquid crystal panel 120. A conversion unit (not shown) for adjusting the resolution (the number of pixels) and the data amount of the gradation data may be arranged at a stage preceding the circuit shown in FIG. Also, the F to be output to the liquid crystal output interface
A function for parallelizing RC data (213) is provided,
FRC data for a plurality of pixels may be transferred to the data driver 140 in parallel. As explained above,
In the liquid crystal display device 100 of the present embodiment, gray scale data which is a digital signal is input, and gray scale display by FRC can be performed at a frame frequency twice the input frame frequency. Further, in the liquid crystal display device 100, the memory capacity required for generating the FRC data is limited to the liquid crystal panel 12
This makes it possible to use an inexpensive memory having a smaller capacity as compared with the conventional example in which 0 is 3 bits per pixel and 8 bits per pixel. Since a display signal for a TFT liquid crystal display device can be displayed, there is an advantage that a notebook personal computer or the like designed for a TFT liquid crystal device can be easily replaced with a TFT liquid crystal display device.

Next, a liquid crystal display device according to a second embodiment of the present invention will be described.

The liquid crystal display of this embodiment is an example in which the frame frequency of the FRC data is set to be three times the frame frequency of the gradation data. The configuration and operation of the liquid crystal display device are the same as those of the first embodiment except for the liquid crystal controller.

FIG. 7 shows a liquid crystal controller 7 according to this embodiment.
No. 01 shows the configuration. As illustrated, the liquid crystal controller 701 further includes an FRC processing unit D and a memory D.

FIG. 8 is a timing chart of memory control in the liquid crystal controller 701. 8, the Vsync signal and input data (grayscale data) have the same timing as that used in the first embodiment (FIG. 5). Also, the same reference numerals as in FIG. 5 are assigned to the frames.

In this embodiment, the phase of the operation cycle (write operation and read operation) between the memories A to D and the read operation period are both one of the one frame period of the gradation data.
/ 3.

That is, in the memory area A, first, after 1W_FRC is written, this data is immediately read as 1R_FRC at three times the speed at the time of writing. Thereafter, 5W_FRC is written, and this data is immediately read as 3R_FRC at triple speed, and further 9W_FRC is written, and immediately this data is read as 9R_FRC at triple speed.

Here, 1W_FRC is 1_in = FR
C processing, 5W_FRC is 2_
The second half of “in” and the first half ３ of 3_in are generated by FRC processing. Therefore, 5R_FRC
As data, the first half of 3_in is output first, and the latter half of 2_in is output later.
The order of input and output is switched. Similarly, 9W_FRC is the latter half of input data 3_in and the former half of 4_in.
Are generated by FRC processing. For this reason,
As the 9R_FRC data, the order of input and output is switched so that the first half of 4_in is output first and the latter half of 3_in is output later.

In the memory area B, after the 2W_FRC is written to the memory area A with a delay of 1/3 of one frame, the data is immediately transferred to the 2R_FRC at triple speed.
Lead as _FRC. After that, 6W_FRC is written, and immediately this data is converted to 6R_FR at triple speed.
C is read, 10W_FRC is further written, and this data is immediately transferred to 10R_FRC at triple speed.
As a lead. Here, as in the case of the memory area A, when the write data extends over two input frame periods, the read order is switched in the same way as in the case of the memory area A.

Similarly, in memory area C, 3W_F is delayed from memory area B by 1/3 of one frame.
Immediately after RC is written, this data is read as 3R_FRC at triple speed. Then 7W_FR
C is written, and immediately this data is output at 7 times the speed of 7 times.
R_FRC is read, and 11W_FRC is written. Immediately, this data is output at 3 × speed to 11R_FRC.
Read as _FRC. Here, as in the case of the memory area A, when the write data extends over two input frame periods, the read order is switched in the same way as in the case of the memory area A.

Similarly, in memory area D, 4W_F is delayed from memory area C by 1/3 of one frame.
Immediately after RC is written, this data is read as 4R_FRC at triple speed. Then 8W_FR
C is written, and immediately this data is transferred at 3x speed to 8
R_FRC is read, and 12W_FRC is written.
Read as _FRC. Here, as in the case of the memory area A, when the write data extends over two input frame periods, the read order is switched in the same way as in the case of the memory area A.

Output data is obtained by sequentially selecting FRC data to be read from each of the memory areas A to D. At this time, the output data is 1R_FRC, 2R_FR
C, 3R_FRC,..., And the output frame frequency is tripled with respect to the input frame frequency.

The pattern switching of the FRC pattern signal in the FRC processing units A to D is performed in accordance with the output order of the frame to which the FRC data to be output after the conversion belongs, and is changed to the pattern of the next frame.

For example, in the case of the example shown in FIG.
The FRC pattern signal of the gradation rate of 4/5 generated by the C processing unit A is a pattern corresponding to the frame 1 in FIG. 4 during the 1W_FRC write operation period, and the frame 5 which is 4 frames ahead during the 5W_FRC write operation period. During the write operation period of 9W_FRC, the pattern corresponds to the frame 4 which is four frames ahead. Similarly,
The FRC pattern signal of the gradation rate of 4/5 generated by the FRC processing unit B corresponds to the pattern corresponding to the frame 2 during the write operation period of 2W_FRC, and corresponds to the frame 1 four frames ahead during the write operation period of 6W_FRC. It becomes a pattern. Similarly, the gradation ratio 4 /
5 is a pattern corresponding to frame 3 during the write operation period of 3W_FRC, and 7W_FRC.
During the write operation period, the pattern corresponds to the frame 2 four frames ahead. Similarly, the FRC pattern signal of the gradation rate of 4/5 generated by the FRC processing unit D is 4W_FR
During the write operation period of C, the pattern corresponds to frame 4 and during the write operation period of 8W_FRC, the pattern corresponds to frame 3 four frames ahead. Thereby, similarly to the first embodiment, 1R_FRC is used for frame 1 in FIG. 4 and 2R_FRC is used for frame 2, 3R_FRC.
Display frames 3,....

As described above, the liquid crystal display device of the present embodiment can perform gradation display at a frame frequency that is three times the frame frequency of the inputted gradation data. Further, the memory capacity required for generating the FRC data is 4 bits per pixel of the liquid crystal panel 120, and is 1 bit.
The number can be reduced as compared with the conventional example in which 8 bits per pixel.

In the above-described two embodiments, the example has been described in which the double speed ratio N of the output frame frequency of the FRC data with respect to the input frame frequency of the grayscale data is doubled or tripled, but the present invention is not limited to this. Not done. A liquid crystal controller in which the double speed ratio N is an integer of 4 or more can be realized by providing N + 1 sets of the FRC processing unit and the memory.

The double speed ratio N in the present invention is not limited to an integer. Hereinafter, this example will be described as a third embodiment.

In the liquid crystal display device according to the third embodiment of the present invention, the rate N of the frame frequency is set to 2.5 times. This liquid crystal display device has the same block configuration as the second embodiment, including the internal configuration of the liquid crystal controller. However, the write / read timing of FRC data is different from the timing of pattern switching of the FRC pattern signal.

FIG. 9 is a timing chart of memory control in the liquid crystal controller of the present embodiment. In FIG. 9, the Vsync signal and the input data (gradation data) have the same timing as that used in the second embodiment. Also, data frames are given the same reference numerals as in FIG.

In the memory area A, immediately after 1W_FRC is written, this data is output at a speed of 2.5 times, that is, 1 time at a time obtained by dividing one input frame by 2.5.
Read as R_FRC. Thereafter, a time during which no data is accessed for a 1/5 frame period is provided, and then 5W_
The FRC is written, and immediately this data is read as 5R_FRC at 2.5 times speed. 1 again
A period during which data is not accessed during a / 5 frame period is provided, and then 9W_FRC is written, and this data is immediately read as 9R_FRC at 2.5 times speed. Here, 1W_FRC data is input data 1_in
5W_FRC
Is the second half of input data 2_in and the first half of 3_in
/ 5 by FRC processing. Therefore, 5R_FRC data is 3 / in the first half of 3_in.
The order is switched so that 5 minutes are output first, and the latter 2/5 minutes of 2_in are output later. Similarly, 9W_F
RC is generated by performing FRC processing on the latter half 4/5 of the input data 4_in and the first half 1/5 of 5_in. Therefore, the 9R_FRC data includes the first half of 5_in
The order is switched so that / 5 minutes is output first and the latter half of 4_in is output later.

In the memory area B, after 2W_FRC is written to the memory area A with a delay of 2/5 of one frame, immediately this data is read as 2R_FRC at 2.5 times speed. Thereafter, a time during which data is not accessed for a 1/5 frame period is provided, and then 6W
_FRC is written, and immediately this data is read as 6R_FRC at 2.5 times speed. 1 again
A time period during which data is not accessed during a / 5 frame period is provided, and thereafter, 10W_FRC is written, and this data is immediately read as 10R_FRC at 2.5 times speed. Here, as in the case of the memory area A, when the write data extends over two input frame periods, the read order is switched in the same way as in the case of the memory area A.

Similarly, in memory area C, 3W_F is delayed from memory area B by 2/5 of one frame.
Immediately after the RC is written, this data is read as 3R_FRC at 2.5 times speed. Then 1/5
A period during which data is not accessed during the frame period is provided, and then 7W_FRC is written, and this data is immediately read as 7R_FRC at 2.5 times speed.
Further, a time during which the data is not accessed in the 1/5 frame period is provided again, and thereafter, 11W_FRC is written, and this data is immediately read as 11R_FRC at 2.5 times speed. Here, as in the case of the memory area A, when the write data extends over two input frame periods, the read order is switched in the same way as in the case of the memory area A.

Similarly, in memory area D, 4W_F is delayed from memory area C by 2/5 of one frame.
Immediately after RC is written, this data is read as 4R_FRC at 2.5 times speed. Then 1/5
A time period during which data is not accessed in the frame period is provided, and then 8W_FRC is written, and this data is immediately read as 8R_FRC at 2.5 times speed.
Here, as in the memory area A, the write data is input 2
In the case of the frame period, reading is performed in the same order as in the case of the memory area A and the order is reversed.

Output data is obtained by sequentially selecting the FRC data to be read from each of the memory areas A to D. At this time, the output data is 1R_FRC, 2R_FR
C, 3R_FRC,..., And the output frame frequency is 2.5 times the input frame frequency.

The pattern switching control of the FRC pattern signal is performed under the same conditions as those described in the second embodiment.

As described above, in the liquid crystal display device of the present embodiment, it is possible to perform a gradation display in which the rate N of the frame frequency is 2.5 times.

Further, it is possible to realize a liquid crystal display device in which another real number having a decimal part has a double speed ratio N. In this case, F
The number of pairs of the RC processing unit and the memory area is increased to one less than the decimal point of the double speed ratio N, and is provided by the number equal to one. Then, an operation synchronized with the input frame may be performed by appropriately setting a time during which the memory is not accessed and adjusting the time.

As described above, according to the present invention, it is possible to realize a liquid crystal display device which can cope with various double speed ratios N and which operates at an optimum frame frequency adapted to the response speed and other characteristics of the liquid crystal. Become.

Next, a liquid crystal display according to a fourth embodiment of the present invention will be described.

FIG. 10 shows a liquid crystal display device 11 of this embodiment.
1 shows a block configuration of No. 01. This liquid crystal display device 1101
Has an A / D converter 1102 in addition to the configuration shown in FIG. In the figure, a liquid crystal module 1001
Consists of all the components shown in FIG. Of course, any of the liquid crystal controllers described in the first to third embodiments may be used.

The liquid crystal display device 1101 is connected to the external device C
A display signal and a synchronizing signal group for the RT display device are input. Here, the display signal for the CRT display device is R
(Red), G (green), and B (red) analog data.

The A / D converter 1102 converts the input display data into 8-bit gradation data (digital data), and outputs it to the liquid crystal controller 110 in the liquid crystal module 1001. Thereby, the liquid crystal module 100
1, the conversion from the gradation data to the FRC data and the conversion of the frame frequency are performed on the liquid crystal panel 120 within 256.
A gradation display of gradation is performed.

As described above, the liquid crystal display device 1 of the present embodiment
The display 101 can perform gradation display by FRC based on a display signal for a CRT display device. Another advantage is that it can be easily replaced with a CRT monitor connected to an external device such as a desktop computer.

Next, a liquid crystal display according to a fifth embodiment of the present invention will be described.

The output frame frequency of the FRC data for performing good display needs to be within a certain range due to the characteristics of the liquid crystal panel and the like. However, when the speed ratio N is fixed, the output frame frequency greatly changes due to a change in the input frame frequency. Thus, the liquid crystal controller of the present embodiment has a function of automatically switching the setting of the output frame frequency according to the input frame frequency.

FIG. 11 shows that the output frame frequency is 180
FIG. 7 is a diagram illustrating a relationship between an input frame frequency and a speed rate N when the frequency is set to around [Hz]. In the present embodiment, by changing the rate N according to the input frame frequency in accordance with this relationship, the output frame frequency is always adjusted to the optimal range even when displaying signals of various input frame frequencies. To enable high-quality display.

The liquid crystal controller of this embodiment has a configuration shown in FIG. 12 for detecting the input frame frequency. In the figure, a counter 1302 counts up according to a high-speed clock 1301 having a constant frequency, and is reset by a Vsync signal input together with gradation data. The frame frequency switching unit 1303 estimates the input frame frequency based on the count value (maximum value) of the counter 1302. In addition, the frame frequency switching unit 1303 has registered in advance the correspondence relationship between the input frame frequency and the speed rate N (FIG. 11), and outputs the speed rate N corresponding to the estimated input frame frequency as a switching signal.

Further, the liquid crystal controller of the present embodiment
It has the configuration described in the second embodiment (FIG. 7) corresponding to the highest speed ratio N (3 times). The memory control unit selectively performs three types of memory control operations according to the switching signal from the frame frequency switching unit 1303. The FRC processing unit also selectively performs three types of pattern switching control according to the switching signal.

When the double speed ratio N is twice, the memory control unit performs the same control as described in the first embodiment on the memory areas A to C. During this time, the FRC processing unit D and the memory area D are not used, and the data selectors operate in the memory areas A to C.
Only the read data of is selected. When the double speed ratio N is 3 times,
The memory control unit performs the same control as described in the second embodiment. When the double speed ratio N is 2.5, the same control as that described in the third embodiment is performed. With the change of double speed ratio N,
The timing clock of the read operation is also switched, and the read is performed at a speed corresponding to the input frame frequency and the double speed rate N.

As described above, in the liquid crystal display device of the present embodiment, the double speed ratio N can be automatically switched in accordance with the value of the input frame frequency. Display can be provided. From this, it is possible to improve the quality of the display image.

[0096]

As described above, according to the present invention, a liquid crystal controller which realizes conversion of a frame frequency of a display signal and gradation display processing by FRC using a memory having a smaller capacity, and , A liquid crystal display device using the same can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a liquid crystal controller according to the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of an FRC processing unit.

FIG. 4 is a diagram showing an example of a frame (pattern of an FRC pattern signal) for gradation display by FRC.

FIG. 5 is a timing chart showing the operation of the liquid crystal controller.

FIG. 6 is a diagram showing the contents of write data when the display of FIG. 4 is performed.

FIG. 7 is a block diagram illustrating a configuration of a liquid crystal controller according to a second embodiment of the present invention.

FIG. 8 is a timing chart showing the operation of the liquid crystal controller.

FIG. 9 is a timing chart illustrating an operation of a liquid crystal controller according to a third embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 11 is a diagram illustrating a relationship between an input frame frequency and a rate of double the frame frequency in a liquid crystal controller according to a fifth embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of an automatic frame frequency determination unit.

FIG. 13 is a block diagram illustrating a configuration of a conventional liquid crystal controller.

[Explanation of symbols]

100: liquid crystal display device, 110: liquid crystal controller, 1
20: liquid crystal panel, 130: scanning driver, 140: data driver, 202: FRC processing unit A, 203: FR
C processing section B, 204 FRC processing section C, 205 memory area A, 206 memory area B, 207 memory area C, 208 data selector, 209 liquid crystal output interface, 212 memory control device, 301 FRC
Pattern generator, 302... FRC pattern signal group, 30
3 FRC pattern selector, 1001 liquid crystal module, 1101 liquid crystal display device, 1102 A / D converter, 1301 high-speed clock for automatic determination, 1302 counter, 1303 frame frequency switching unit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinji Uchida 3300 Hayano Mobara-shi, Chiba Hitachi, Ltd.Electronic Device Division (72) Inventor Tatsuhiro Inuzuka 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. In the image information system

Claims (6)

[Claims] 1. A simple matrix type liquid crystal display device comprising a plurality of bits of gray scale display data and a group of synchronization signals input per pixel, and a group of 1-bit binary display data and synchronization signals output per pixel. A liquid crystal controller for causing a panel to perform gradation display corresponding to gradation display data, wherein for each value of the gradation display data, a pattern signal having a plurality of predetermined patterns is generated and input. (P is an integer of 3 or more) FRCs that output the value of the pattern signal corresponding to the gray scale display data as binary display data
A processing unit, P memory regions arranged corresponding to the FRC processing units, each having a storage capacity of one frame of binary display data, and a predetermined phase in synchronization with an input synchronization signal. One frame of binary display data is written to each memory area, and after writing, control is performed to read the binary display data of each memory area at a speed N times (N is a real number greater than 1) that at the time of writing. A liquid crystal controller comprising: a memory control unit; wherein each of the FRC processing units switches a pattern of a generated pattern signal according to an output order of a frame included in binary display data to be output after conversion. 2. The liquid crystal controller according to claim 1, wherein the memory control circuit sets a write period and a read period for the memory area to 1 / frame of one frame period of gradation display data between each memory area. N, and so that the read periods of the respective memory areas are continuously connected,
A liquid crystal controller that performs control. 3. The liquid crystal controller according to claim 1, wherein in the memory control circuit, in each memory area, a read period and a write period sandwich a non-access period having a length determined by the value of N. A liquid crystal controller which performs control so as to be connected and a continuous read period of each memory area. 4. The liquid crystal controller according to claim 1, wherein said N based on the input synchronization signal is set such that the frame frequency of the binary display data to be output falls within a predetermined range.
A liquid crystal controller further comprising: means for changing the value of. 5. A liquid crystal panel of a simple matrix type, a liquid crystal controller according to claim 1, 2, 3 according to a synchronization signal output from the liquid crystal controller.
A liquid crystal display device comprising: a scan driver and a data driver for causing the liquid crystal panel to perform display corresponding to value display data. 6. The liquid crystal display device according to claim 5, further comprising an A / D converter for converting display data as analog data into gradation data as digital data. apparatus.