JPH06110411A - Simple matrix driving type liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide the simple matrix driving type liquid crystal display device which can displays display data from a host side on a two-screen division type simple matrix driving type liquid crystal display panel without changing the existent display controller of a CRT display driving device and using any frame buffer. CONSTITUTION:A video RAM is divided into two blocks for a lower and an upper screen. This device is provided with an address conversion part 4 which converts the row address of an address signal from a display controller 1 according to an address conversion truth, and divides the converted address into parts for the upper screen and lower screen and writes them in video RAMs 6a and 6b for the upper and lower screen individually at the time of read/write operation. Further, the device is provided with a transfer address serial clock conversion part 5 which increases the row address once in every two transfer cycles of the display controller 1 and gives the same address to both the video RAMs 6a and 6b, and outputs addresses from both the video RAMs 6a and 6b at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simple matrix drive type liquid crystal display device for displaying data from a host computer or the like on a liquid crystal display panel whose display screen is divided into two.

[0002]

2. Description of the Related Art In a conventional display system capable of displaying high resolution (1024.times.768) such as a workstation, a display controller (1) receives it through a bus of a CPU on the host side as shown in FIG. The address is converted and the address signal and various control signals are sent to the video RAM (2) consisting of a group of eight dual port RAMs to read / write. In the memory map of the video RAM (2) at that time, the same address is assigned to four pixels as shown in FIG.
The width of the data bus from the PU is 32 bits, which is 8 bits per pixel for display. The (X, Y) values in the memory of FIG. 7 indicate the coordinates of the dots to be displayed. For example, (4, 4) is the fourth horizontal line, that is, the fourth line, that is, the fourth line. The coordinates of the 13th to 16th dots are shown. 1
The reason for the 3rd to 16th dots is that 4 pixels are assigned to the same address. In the display cycle, the display controller (1) applies a serial output address signal to the video RAM (2) to perform a dual cycle.
Data is output from the serial input / output pin when a clock for inputting / outputting the video RAM (2) which is a port RAM is given. The 32-bit data output from the video RAM (2) is the video signal conversion circuit (3).
To each pixel and then latched internally
The RGB analog signal as a video signal is D / A converted into a value corresponding to each pixel of RGB in the M file, and the external analog C
Output to RT monitor. The horizontal and vertical synchronizing signals are supplied from the display controller (1) to the external CRT monitor together with the RGB analog signals described above.

[0003]

By the way, when a dot matrix liquid crystal display device having a high resolution display as described above is driven by turning on / off an applied voltage for each dot, a large number of wirings are required. Therefore, there is a simple matrix drive type liquid crystal display device in which a voltage of a predetermined waveform is applied to each row and column to drive each dot in a time division manner and a display screen is divided into two in order to increase the contrast. Such a liquid crystal display device is suitable for a space-saving type electric product such as a laptop type.

However, in order to drive the display of this type of simple matrix drive type liquid crystal display device, it is necessary to simultaneously output respective display data for the upper half and the lower half of the screen to the liquid crystal display section. The display drive device of FIG. 6 can output only data of a certain one horizontal period because the display cycle is performed by serial output, and is applicable to display drive of a simple matrix drive type liquid crystal display device. I can't. Therefore, the existing display drive section of the simple matrix drive type liquid crystal display device for displaying the display data from the CPU (host) has a complicated configuration using a frame buffer including a frame memory and many RAMs. However, since the size of the liquid crystal display device becomes large and expensive due to the complicated structure, a simple matrix drive type liquid crystal display device can be used as a space saving type electric product such as a laptop type device for the purpose of small size and low cost. It could not be applied to the display.

Therefore, the present invention does not change the display controller of the existing CRT display driving device, does not affect the host side, and does not use the frame buffer, and does not use the frame buffer. An object of the present invention is to provide a simple matrix drive type liquid crystal display device capable of displaying display data from the host side by simultaneously outputting data in the display cycle of the display controller.

[0006]

According to the present invention, as a technical means for achieving the above object, a simple matrix drive type liquid crystal display device is constructed as follows. That is, in a simple matrix drive type liquid crystal display device which displays data from a host computer or the like on a simple matrix drive type liquid crystal display panel which is divided into upper and lower parts, each is composed of a predetermined number of dual port RAM groups. Each video RAM for the upper screen and the lower screen, a display controller for converting an access address to the video RAM from the host side to an address for the video RAM, and an address signal from the display controller during a read / write cycle Row address is converted based on a predetermined address conversion truth, and the converted address is divided into an upper screen portion and a lower screen portion by a strobe signal which latches each column address of the upper screen portion and the lower screen portion. Then, each video RA for the upper screen and the lower screen RA
An address conversion unit that individually writes to M and one every two transfer cycles from the display controller during the transfer cycle.
The row address is incremented by one at a rate of twice, a transfer address for giving the same address to both the video RAMs and serially outputting at the same time, and a serial clock conversion unit, and output data from the both video RAMs are the simple matrix drive type A liquid crystal gradation control unit for signal processing for a liquid crystal front panel is provided.

[0007]

In the read / write cycle from the display controller to the video RAM, the address conversion unit converts the row address of the address signal from the display controller based on a predetermined address conversion truth, and
The converted address is divided into an upper screen portion and a lower screen portion by a strobe signal that latches each column address of the upper screen portion and the lower screen portion, and individually written in the upper screen video RAM and the lower screen video RAM. Be done. Then, during the transfer cycle, the row address is incremented by 1 at a rate of once every two transfer cycles from the display controller by the transfer address / serial clock conversion unit, and the same address is given to both video RAMs to give both video RAMs.
Are serially output simultaneously from. Therefore, a simple matrix drive type liquid crystal display panel divided into two screens can be displayed without using a frame buffer.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a system block diagram of a display drive portion which is an essential part of one embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 6 are designated by the same reference numerals. That is, the display controller (1) is the same as that shown in FIG. 6, and the row and column addresses for serial output are multiplexed to the video RAMs (6a) and (6b) described later in order to control the display cycle. The output 10-bit address signal "VA0-9" is output. Video RA
M is an upper screen video RAM (6a) and a lower screen video R
It is divided into two blocks of AM (6b), and each of the video RAMs (6a) and (6b) is composed of four 128K × 8 dual port RAM groups.

The address conversion unit (4) converts the address signals "VA0-9" from the display controller (1) as described below to convert the conventional memory map of FIG. 7 into the conventional memory map of FIG.
It is converted into a memory map as shown in (b) and output.
The transfer address / serial clock conversion unit (5) conforms to the present invention by converting a transfer address transmitted from the display controller (1) and converting an address at that time, and a serial clock during a display cycle. Generate a shift clock. This shift clock is basically a clock obtained by dividing the serial clock output from the display controller (1) by two, but since the active position is different, the existing CRT display drive device shown in FIG. 6 is used. Of the load clock output from the display controller (1) to the video signal conversion circuit (3) [equivalent to the serial clock output from the display controller (1) and continuously output], One horizontal period part of a simple matrix drive type liquid crystal display panel (CR
20 for a total of 1024 pixels (2 horizontal periods of T)
It consists of a part that creates a period in which 48 pixels are active. The transfer cycle is a cycle for giving an address for serial input / output of each video RAM (6a), (6b) which is a dual port RAM, and after giving the address, input the serial control clock. The address is incremented by. on the other hand,
In the display cycle, access to the video RAMs (6a) and (6b) is opened to the CPU on the host side by utilizing the function of automatically counting up.

The liquid crystal gradation control section (7) outputs 32 from each of the video RAMs (6a) and (6b).
A total of 64 bits of serial output data are input, and a portion for gradation of 8 pixels [4 pixels for upper screen and 4 pixels for lower screen] and horizontal and vertical synchronization signals from the display controller (1) And a portion for converting the transfer address and the serial clock divided by two from the serial clock conversion unit (5) for the simple matrix drive type liquid crystal display panel.

Next, the operation of the above embodiment will be described with reference to FIGS. First, the CPU on the host side
The address of access to the video RAMs (6a) and (6b) from the device is converted into the addresses for the video RAMs (6a) and (6b) by the display controller (1) as shown in FIG. 7, and these converted addresses are converted. Is further divided into addresses for the upper screen and the lower screen by the address section (4) as shown in the memory maps of FIGS. 5A and 5B, and then the upper screen video RAM (6a). And are individually output to the lower screen video RM (6b).

The address conversion in the address conversion unit (4) is performed by the video RAM from the display controller (1).
The address signal “VA” output from the display controller (1) at the time of reading / writing to (6a) and (6b)
0-9 ", the upper 3 bits of the row address" VA "
9 ”,“ VA8 ”, and“ VA7 ”, based on the address conversion truth table of FIG. 4, address signals“ VVA9 ”,“ VVA8 ”, and“ VVA7 ”for the video RAMs (6a) and (6b).
And the video RAM (6a), (6) of 4 blocks 0 to 3 output from the display controller (1).
b) column address latch signal "-CAS (3 to
0) ”in the upper and lower video RAMs (6a),
It is performed by dividing the access to (6b) to generate a latch signal "-CASA (3-0)" for the upper screen and a latch signal "-CASB (3-0)" for the lower screen. This latch signal "-CASA (3 ~
0) "and" -CASB (3-0) "are output according to the waveforms of the corresponding blocks of the latch signal" -CAS (3-0) "from the display controller (1). At this time, the other row address and column address remain unchanged, and the address for the transfer cycle output from the display controller (1) is not used. The "-" mark added to the head of the signal as described above indicates that the signal is a low active signal, and will be used in the same manner hereinafter.

FIG. 2 shows a timing chart of the address conversion unit (4) described above. First, each signal of (a) to (k) in the same figure will be described. "-R
"AS" is a row address strobe signal which is a latch signal of a row address of the RAM, and "-CAS (3-0)" is a column address latch which is output to the four blocks of RAMs 0 to 3 as described above. A column address strobe signal, "-DT / OE", which is a signal, is a data transfer control output enable signal that controls data in a transfer cycle and a read operation in a read cycle, and "-WE" is a write operation. Light to control
The enable signal, "-ACK", is an acknowledge signal indicating the end of the read / write cycle of the CPU, and any of the above is a signal output from the display controller (1).

Next, the signals output from the address conversion unit (4) and the transfer address / serial clock conversion unit (5) will be described. "-VRAS" is RA
Video RAM row address strobe signal, which is a latch signal for the row address of M, "-VCASA (3 to 0)"
Is a column address strobe signal for the video RAM, which is a latch signal of the column address of the upper screen video RAM (6a) of the four blocks 0 to 3 of the upper screen, as well as "-VCASB (3 to 0)". Is a column address strobe signal for the video RAM which is a latch signal of the column address of the lower screen video RAM (6b) of 4 blocks 0 to 3 of the lower screen, and "-VDT / OE" is the data in the data transfer cycle. In the read cycle, the data transfer control output enable signal for the video RAM for controlling the read operation, "-VWE" is the write enable signal for the video RAM for controlling the write operation, "VA
"A0-9" indicates a 10-bit address signal for the RAM which is output by multiplexing the row address and the column address, and "-VACK" indicates an acknowledge signal for the video RAM indicating the end of the CPU read / write cycle. .

Then, during the periods T1 and T2 of FIG. 2, the address conversion unit (4) causes the row address strobe signal "-RAS" of FIG. Since the row address strobe signal for video RAM "-RAS" is at a high level at the time, it is determined that it is not a transfer cycle, that is, read / write by the CPU, and operates. First,
The row address latched by the fall of the row address / strobe signal "-RAS" is subjected to address conversion based on the address conversion truth table of FIG. 4 and output as a video RAM address signal "VAA0-9". Also, the video RA
The M row address strobe signal "-VRAS" is output with a delay of one cycle of the reference clock from the row address strobe signal "-RAS". The reference clock is a clock used for the I / F logic of the video RAMs (6a) and (6b) inside the display controller (1) and has the same cycle as the normal load clock.

Further, depending on the value of the row address designated by the display controller (1), the upper screen video RAM (6
a) or the lower screen video RAM (6b), which is the column address / strobe signal for video RAM "-VCASA" shown in the address conversion truth table of FIG.
(3 to 0) "and" -VCASB (3 to 0) "for separation and output. Therefore, T1 in FIG. 2 is an access cycle for the upper screen video RAM (6a) from the CPU, and T2 is the lower screen video RAM (6a) from the CPU.
This is an access cycle for B). In either case, the column address / strobe signal for video RAM "-V
CASA (3-0) "," -VCASB (3-0) ",
Data transfer control output enable signal "-VDT / OE" for video RAM and video RA
The M write enable signal "-WE" is output with a delay of one cycle of the reference clock, and the acknowledge signal "-AC" is sent to notify the CPU of this delay.
K "is also delayed by one clock and returned as an acknowledge signal" -VACK "for the video RAM. In addition, in the same figure (c), data transfer control
The output enable signal "-DT / OE" has the waveform shown in FIG. 7C, and the write enable signal "-WE" has the waveform shown in FIG. 7C when writing. In either case, the other is high level. It has become. Further, the column address / strobe signal "-CAS (3-0)" has the waveform shown in FIG. 5B only for the corresponding one, and further, FIG.
As is clear from (a) and (b), the upper screen video R
The row address of the address signal "VA0-9" is 0 to AFH in the period T1 which is the access cycle to the AM (6a), and the lower screen video RAM (6b).
The row address of the address signal "VA0-9" in the period of T2 which is the access cycle for
It is 17FH. Video RAM address signal "VAA"
0-9 "are converted addresses.

Next, at time T3 in FIG. 2, since the row address strobe signal "-RAS" is at the high level at the fall of the column address strobe signal "-CAS (3-0)", the video RAM is (6a), (6
It is determined that there is a refresh cycle for holding the data in b). Since the address at this time has no meaning, it may be indefinite, and the output timing is not delayed, that is, it is output as it is without any timing adjustment. Therefore, the display controller (1) does not affect the CPU on the host side, and the display controller (1) for the CRT display of FIG. Can access (6b).

The data thus accessed and written in the video RAMs (6a) and (6b) for the upper screen and the lower screen are used as addresses for the display cycle in the transfer cycle indicated by T4 in FIG. It is given and displayed on a simple matrix drive type liquid crystal display panel. The display cycle is created by the display controller (1), but the same transfer address is given to both the upper screen and lower screen video RAMs (6a), (6b) so that they are serially output at the same time. Therefore, only one of the two transfer cycles of the display controller (1) is used. The display address is generated in the transfer address / serial clock conversion unit (5) because the output of the display controller (1) is not used. At this time, the address conversion unit (4) does not control anything. A timing chart of the relationship between the transfer address and the transfer cycle in the serial clock conversion unit (5) and the increase of the address is shown in FIG.
Each signal of (i) to (i) is the same as that described above. And
The display address is cleared by the vertical synchronizing signal and the row address is incremented by 1 in two transfer cycles.
The row address is converted in the transfer cycle, and the same row address is given to both the upper screen video RAM (6a) and the lower screen video RAM (6b) by the transfer address / shift clock converter (5). Therefore, it is possible to display on a simple matrix drive type liquid crystal display panel whose screen is divided into two without using a frame buffer.
In addition, a video RAM (6
A function for automatically counting up the display cycle by inputting the serial control clock after the addresses for serial input / output are given to a) and (6b) in the transfer cycle. The data of the video RAMs (6a) and (6b) is output using the above. However, the above-mentioned count-up is only for the row address, and the count-up function of this row address has an 8-bit counter and two transfer cycles. Can be obtained by a simple configuration with a circuit that counts up by "1".

Each video RAM (6
The data output from the serial input / output of (a) and (6b) is input to the liquid crystal gradation control unit (7) with a total of 64 bits of 32 bits. The liquid crystal gradation control section (7) has four pixels for the upper screen and four pixels for the lower screen.
Input data signals for pixels are processed for display on a simple matrix drive type liquid crystal display panel. When the simple matrix drive type liquid crystal display panel is monochrome, each pixel has 1 bit, so 8-bit data is grayed by using an existing method such as frame thinning. Further, the horizontal synchronizing signal and the vertical synchronizing signal are converted for the simple matrix drive type liquid crystal display panel. Although this differs depending on the specifications of the liquid crystal, in the normal case, the liquid crystal vertical synchronizing signal is activated at the position of the first line where the data becomes valid. Further, the liquid crystal vertical synchronizing signal becomes active at the first pixel where the data of each line becomes valid. Further, the clock for the liquid crystal and the data for the upper and lower screens are input according to the specifications of the liquid crystal of 1024 × 768. Usually high resolution ones
Since it is an upper and lower input of 8-bit pack, video R
Two data inputs from AM (6a) and (6b) complete the data for eight pixels of the upper and lower screens, and the liquid crystal clock is a cycle of the shift clock divided by two.

[0020]

As described above, according to the simple matrix drive type liquid crystal display device of the present invention, the row address of the address signal from the display controller is converted by the address conversion unit in the read / write cycle based on the predetermined address conversion truth. In addition, the converted address is divided into an upper screen portion and a lower screen portion, which are individually written in the upper screen video RAM and the lower screen video RAM, and at the time of a transfer cycle, the transfer address and the serial clock conversion unit are used to display the display controller. Since the row address is incremented by one at a rate of once every two transfer cycles from 1 to 2, the same address is given to both video RAMs and serial output is performed simultaneously from both video RAMs, so two screens are divided. Use frame buffer for simple matrix drive type liquid crystal display panel And without show without and change the display controller in the existing CRT display driver. Therefore, it can be applied as a display unit of a space-saving electric device such as a laptop type because it is small and inexpensive.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

2A to 2K are timing charts in the address conversion unit of the above.

3 (a) to (i) are timing charts of the transfer address and serial clock conversion unit in the above.

FIG. 4 is a diagram showing a truth table for address conversion of the above.

5A and 5B are diagrams showing a memory map and a display position of each video RAM for the upper and lower screens, respectively.

FIG. 6 is a system block diagram of a conventional CRT display driving device.

FIG. 7 is a diagram showing a memory map of a video RAM and a display position in the same as above.

[Explanation of symbols]

 1 display controller 4 address conversion unit 5 transfer address / serial clock conversion unit 6a upper screen video RAM 6b lower screen video RAM 7 liquid crystal gradation control unit

Claims (1)

[Claims] 1. A simple matrix drive type liquid crystal display device for displaying data from a computer or the like on a host side on a simple matrix drive type liquid crystal display panel divided into upper and lower parts, each of which is provided with a predetermined number of dual port RAM groups. Each configured video RAM for upper screen and lower screen
A display controller for converting an access address from the host side to the video RAM into an address for the video RAM, and a row address in an address signal from the display controller during a read / write cycle based on a predetermined address conversion truth. With conversion
The converted address is divided into an upper screen portion and a lower screen portion by a strobe signal which latches the column addresses of the upper screen portion and the lower screen portion, and is divided into the upper screen and lower screen video RAMs. An address conversion unit to be individually written, and a row address is incremented by one at a rate of once in every two transfer cycles from the display controller during the transfer cycle to give the same address to both the video RAMs and simultaneously perform serial output. A simple matrix comprising: a transfer address / serial clock conversion unit; and a liquid crystal gradation control unit for processing the output data from the video RAMs for the simple matrix drive type liquid crystal front panel. Driven liquid crystal display device.