JPH0635420A - Flat panel display - Google Patents

Abstract

PURPOSE:To lower the driving frequency of a drive by making a controller applicable to a multiscreen display. CONSTITUTION:This flat panel display consists of an input part 3 which writes the image data of a host computer 1 in an image memory pad 4, the image memory part 4 where the image data are written and an output part 5 which writes the image data of the image memory part 4 in driver part 6. Data buses are extended from the image memory part 4 to the driver parts 6 in parallel and the image data are inputted to the blocks of the respective driver parts in parallel, so the driving frequency of the driver parts 6 can be lowered by the number of their parallel processes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display, and more particularly to a flat panel display that allows a driver having a slow driving frequency to be used by dividing image data input to a drive unit in parallel.

[0002]

2. Description of the Related Art A controller for a liquid crystal display is described in, for example, Japanese Patent Application Laid-Open No. 61-123882. VGA size (640 x 480 pixels)
Liquid crystal display controllers are already known. These controllers are of a type that writes image data to the image memory unit according to an instruction from the host computer and transfers the image data serially to the LCD driver, and a type that expands the video signal output to the image memory unit. Writing is performed, and the image data is serially transferred to the liquid crystal driving driver unit.

FIG. 14 is a block diagram of a conventional liquid crystal display. In the figure, 21 is a host computer, 22 is a bus,
Reference numeral 23 is a liquid crystal controller, 24 is an image memory, 25 is a liquid crystal driver, and 26 is a liquid crystal panel. Generally, a flat panel display includes a panel section 26 in which liquid crystal elements and EL elements are formed, a driver section 25 that applies a signal to the liquid crystal elements and EL elements, and a controller section that sends image data to the driver section. It consists of 23. The controller unit 23 has a function of drawing an image in the image memory unit 24 according to an instruction from the host computer 21, and a function of transferring the image signal to the driver unit 25. Therefore, a controller has to be manufactured for each screen size of the flat panel display. Table 1 shows the standards for various displays.

[0004]

[Table 1]

In order to increase the definition and the number of gradations of the display, not only the definition of the panel section must be increased, but also the speed of the controller section and the driver section must be increased. This is because the display has high definition and multiple gradations, and the frame frequency cannot be lowered even if the number of data per screen increases. For example, XGA class (number of pixels; 1024 x 76
In the case of 8), the number of data… 1024 × 768 × 4 = 3.15 Mbit / screen
(16 gradations for each pixel) Pixel frequency: number of data x frame frequency 3.15 M x 60
= 189 MHz Here, assuming that the data bus size of the driver is 8 bits, the driving frequency of the driver is ... Pixel frequency / 8 = 23.6 MHz. In the case of color, a driving frequency three times as high as this is required. Furthermore, in the case of a driving method of a liquid crystal panel multiplex method (MIM-driven AM-LCD or STN method), the driving voltage increases as the number of pixels increases, so that the driver is required to have high speed and high breakdown voltage. , Drivers that satisfy this condition will be very expensive.

[0006]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to realize multi-screen support of a controller and to provide a flat panel display designed to reduce the driving frequency of a driver. It was done for the purpose.

[0007]

In order to achieve the above object, the present invention provides (1)
An input unit for inputting image data of the host computer,
An image memory unit for storing image data from the input unit;
It is composed of a drive unit for applying a signal to the elements of the liquid crystal panel unit, and a controller unit for transferring the image data of the image memory unit to the drive unit. The image memory unit is divided into a plurality of pieces of image data. And transferring the image data in parallel to the drive unit, further comprising (2)
Comprised of the image memory unit and a multi-port RAM of 256 columns or less, one pixel of the image memory unit corresponds to one address of the multi-port RAM, and various systems are supported by counting addresses in the column direction. ,
Further, (3) the image memory unit is divided into blocks for each flat panel display, and various systems are supported by counting addresses in the column direction, and (4) the image memory. It is characterized in that the number of columns in the set matches the number of outputs of the driver unit or is an integral multiple thereof. Hereinafter, description will be given based on examples of the present invention.

FIG. 1 is a block diagram for explaining an embodiment of a flat panel display according to the present invention.
1 is a host computer, 2 is a bus, 3 is a liquid crystal controller input unit, 4 is an image memory unit (VRAM), 5 is a liquid crystal controller output unit, 6 is a liquid crystal driver unit, and 7 is a liquid crystal panel.

The image data of the host computer 1 is stored in an image memory (multiport VRAM; Video Random Access).
Memory controller 4 for writing to memory 4
And a VRAM unit 4 in which image data is written, and an output unit 5 in which the data of the VRAM 4 is written in the driver unit 6. A data bus is input to the driver in parallel from the image memory unit. Therefore, since the image data is always input in parallel to each driver block, the driving frequency of the driver can be delayed by the number of parallel processes. 2A to 2G show timing charts.
The figure (a) is La, the figure (b) is a clock signal, the figure (c) is a conventional data signal, and the figure (d)-(g) is a data signal in this invention.

FIGS. 3A to 3F are views showing mounting configurations of various types of flat panel displays.
Is color, Figure (b) is monochrome, Figure (c) is VGA (Vi
deoGraphic Array) color, class 1 color, figure (d) shows class 2 monochrome, figure (e) shows XGA color, class 2 color, and figure (f) shows class 2 monochrome. Pixel pitch and driver (TAB; Ta
pe Automated Bonding) Depending on the pitch, one-sided driving and vertical driving can be considered. Pixel pitch is TA
If the connection pitch is larger than B, the unit can be downsized by driving on one side. If the size is small, vertical driving is advantageous in terms of cost, such as prevention of increase in substrate size. Since the general pitch of TAB is about 180 μm, it is driven up and down in the case of a color display (usually 1 dot; 110 μm), and a monochrome display (usually 1 dot; 3
In case of 30 μm), it is driven on one side. In addition to this, there are cases where the liquid crystal panel is divided into upper and lower parts to reduce the duty of the liquid crystal and improve the image quality.

In the case of a color display of class 1 size, this can be achieved by dividing the column direction into two, and by using it in combination with the vertical drive system, the drive frequency can be reduced to 1/4. In this case, one block is 480 bits. Drive frequency = 1 block x number of row lines x frame frequency x number of buses x bit per pixel = 480 x 480 x 60 ÷ 8 x 4 = 6.91 MHz

In the case of a class 2 size monochrome display, this can be achieved by dividing the column direction into four to make the driving frequency 1/4. In this case, one block is 320 bits. Drive frequency = 320 × 1024 × 60 ÷ 8 × 4 = 9.83 MHz

In the case of a class 2 size color display, this can be achieved by dividing the column direction into four, and by using the vertical drive system in combination with a drive frequency of 1/8. In this case, one block has 320 bits, and the drive frequency is the same as that of a monochrome display.

FIG. 4 is a block diagram of an image memory unit according to the present invention (claim 2). The image memory section has 5 multi-port RAMs with 256 columns in the column direction and 2 in the row direction.
Individually arranged. Therefore, with this method, it is possible to support a display with a size of column ... 256 x 5 = 1280 rows ... 512 x 2 = 1024. Also, up to 16 bits of image data can be stored for each address. In the VRAM output, when a clock signal is input to the output section, image data is output in synchronization with it. The start address in the column direction can be set arbitrarily. Therefore, by setting the start address of each VRAM and then inputting this clock, it becomes possible to transfer the image data to each liquid crystal driver, and by counting this, the image data corresponding to each system can be arranged in parallel. You can enter. Hereinafter, each method will be described in detail.

FIGS. 5A and 5B show a configuration diagram and a timing chart in the case of class 1 (color). First, image data is input to the VRAM according to a drawing command from the host controller. In this case, each color (red, green, blue) is composed of 4 bits out of 16 bits (if each color is 8 bits, the basic structure should be 24 bits). The number of VRAMs used is three in the column direction and two in the row direction. (1) V of a, c as the start address of VRAM
Address 0 is set in the RAM, and address 64 is set in the VRAM of b. (2) A clock signal (S
When C) is input, 12 × 2 bit image data is output. (3) If the number of clocks reaches 192, VR of a, c
A clock signal is input to the SAM section of AM, and the clock of section b is stopped. (4) If the clock signal reaches 256, V of b, c
A clock signal is input to the SAM section of the RAM, and the clock state of the section a is stopped. (5) When the clock signal reaches 320, the row address is set to +1 and the process returns to (1). In this system, 24 bits (12 × 2) data is output in one clock, but the LCD driver block is 32 bits (8 × 4).
You can enter the data of. In this case, it is necessary to use a buffer memory or the like for timing.

FIGS. 6A to 6C show a configuration diagram, a timing chart and cells in the case of class 2 (monochrome). First, the VR is executed by the drawing command of the host controller.
Input image data to AM. 8 bits for 256 gradations
(It becomes 4 bits in the case of 16 gradations). Also,
There are 5 VRAMs in the column direction and 2 in the row direction.
It is an individual. (1) V of a, e as the start address of VRAM
Address 0 is set in the RAM, and address 64 is set in the VRAM of b. Address 128 is set in the VRAM of c. d
Address 192 is set in the VRAM. (2) A clock signal (S
When C) is input, 8 × 4 bit image data is output. (3) If the number of clocks reaches 64, the VRAM of d
Then, the clock signal of the SAM section is stopped and the clock signal is input to the e section.

(4) When the number of clocks reaches 128, stop the clock signal of the SAM section of the VRAM c,
A clock signal is input to the d section. (5) If the number of clocks reaches 192, VRA of b
The clock signal of the SAM portion of M is stopped and the clock signal is input to the c portion. (6) If the number of clocks reaches 256, VRA of a
The clock signal of the SAM portion of M is stopped and the clock signal is input to the portion b. (7) When the clock signal reaches 320, the row address is set to +1 and the process returns to (1). In this system, 32 bits (8 × 4) data can be output in one clock, and the LCD driver can input 32 bits (8 × 4) data. When one pixel is 4 bits, it is necessary to use a buffer memory or the like to take timing.

Further, in the case where the drive is divided into two for high image quality and the duty ratio is reduced, if the data is simultaneously output from the image memory in the row direction, the drive frequency can be further reduced. 7A to 7C show a configuration diagram, a timing chart and a cell in this case.

FIGS. 8A to 8C show a configuration diagram, a timing chart and a cell in the case of class 2 (color). First, the VR is executed by the drawing command of the host controller.
Input image data to AM. In this case, of 16 bits, each color (red, green, blue) is composed of 4 bits (if each color is 8 bits, the basic structure should be 24 bits). The number of VRAMs used is five in the column direction and two in the row direction. (1) V of a, e as the start address of VRAM
Address 0 is set in the RAM, and address 64 is set in the VRAM of b. Address 128 is set in the VRAM of c. d
Address 192 is set in the VRAM. (2) A clock signal (S
When C) is input, 8 × 4 bit image data is output.

(3) If the number of clocks reaches 64,
The clock signal of the SAM section of the VRAM of d is stopped and the clock signal is input to the e section. (4) If the number of clocks reaches 128, VRA of c
The clock signal of the SAM portion of M is stopped and the clock signal is input to the d portion. (5) If the number of clocks reaches 192, VRA of b
The clock signal of the SAM portion of M is stopped and the clock signal is input to the c portion. (6) If the number of clocks reaches 256, VRA of a
The clock signal of the SAM portion of M is stopped and the clock signal is input to the portion b. (7) When the clock signal reaches 320, the row address is set to +1 and the process returns to (1). With this method, 48-bit (24 × 4) data can be output in one clock, and 32-bit (8 × 4) data can be input to the LCD driver unit, so it is necessary to use a buffer memory or other means to obtain timing. is there.

As described above, various display sizes can be dealt with by switching with the same number of clocks (SC). Although the 256-column multiport VRAM is used here, the same effect can be obtained by operating the 256-column operation using the split register operation of the 512-column multiport RAM.

FIG. 9 shows another configuration diagram (claim 3) of the image memory unit according to the present invention. In the image memory unit, 512 multicolumn RAMs of four columns are arranged in the column direction and two in the row direction. Therefore, with this method, it is possible to support a display with a size of column ... 512 x 4 = 2048 rows ... 512 x 2 = 1024. In addition, up to 12 bits of image data can be stored for each address. For inputting image data to the VRAM, address designation of the image memory unit and input of the image data are input in pairs from the host controller. Therefore, each VRA
Basic size of M (standard number of columns; usually 256,512 columns)
The basic size of the LCD driver (usually an integral multiple of 160 to 320,
480), the output of each VRAM can be made to correspond one-to-one to the input of the liquid crystal driver. Less than,
Each method will be described in detail.

FIGS. 10A and 10B show a configuration diagram and a timing chart in the case of class 1 (color). 12 b
It is composed of 4 bits for each color (red, green, blue) (if each color is 8 bits, the basic structure should be 24 bits). The number of VRAMs used is two in the column direction and two in the row direction. The column address signal output from the host controller is converted as follows. From 1.1 to 320, the data is directly transferred to the VRAM section. 2. From 320 to 480, enter the address obtained by adding +192 to that address. In this system, 24 bits (12 × 2) data is output in one clock, but the LCD driver block is 32 bits (8 × 4).
You can enter the data of. In this case, it is necessary to use a buffer memory or the like for timing. Also, class 2
In the case of (monochrome / color), if the column address signal output from the host controller is matched with the division number of the driver, the image data may be transferred in parallel to each driver unit.

11 (a) and 11 (b) are diagrams showing a configuration diagram and a timing chart of still another embodiment (claim 4) of the present invention. The number of columns in a general VRAM is 256 or 512. On the other hand, the LCD driver is 80,160
It is output. Therefore, the number of driver outputs is 256,1
By changing to 28 outputs, it becomes possible to support various systems without using a special circuit. In this case, each block is 2
Since it is enough to have 56 units, a configuration like 160 + 96 is also possible.

FIG. 12 is a diagram showing another embodiment of the flat panel display according to the present invention. In the figure, 11 is a controller, 12 is a GSP (graphics processor), 13 is a work RAM, 14 is a program ROM,
15 is VRAM, 16 is Logic + buffer, 17 is FI
FO, 18 are liquid crystal drivers, and 19 is a liquid crystal panel.
MI using a hard carbon film (iC) in the liquid crystal panel section
Using M type liquid crystal panel display, PC9801 as photo controller, VR by command
GSP (graphic processor: TMS34020; manufactured by TI) that draws image data in the AM section, and 1M of 256 × 8bit configuration
10 bit multi-port VRAM is mounted on the expansion board, and FIF is used as the buffer memory of the LCD driver.
A liquid crystal controller using an O memory was manufactured. The screen size can be displayed in various sizes simply by writing it in the GSP register. A general-purpose counter is used to count the VRAM, and the output of the 3-state buffer is switched to deal with this. I was able to create a program for GSP control on the PC9801, operate liquid crystal panels of various sizes, and display a large-screen liquid crystal display using a driver for driving liquid crystal with a low drive frequency.

FIG. 13 is a view showing still another embodiment of the flat panel display according to the present invention. The PC9801 is used as a host controller, and image data is drawn in the VRAM by sending a drawing command to the GSP. VR
A logic circuit is provided on the address bus of AM. If it is "320" or less, the address is output as it is. If it is more than "320", "320" is subtracted from that address, and the next V
An address decoder for accessing the RAM is provided.
It was possible to create a program for GSP control on the PC9801, operate liquid crystal panels of various sizes, and display a large-sized liquid crystal display using a driver for driving a liquid crystal with a low drive frequency.

[0027]

As is apparent from the above description, the present invention has the following effects. (1) Effect corresponding to claim 1: Since image data to be input to the driver unit can be divided in parallel, a driver with a slow driving frequency can be used, so that a flat panel display with a large screen at low cost can be used. Can be provided. (2) Effect corresponding to claim 2: Same address (1,
64, 128, 192, 256, 320), it suffices to switch the VRAM, which makes it possible to support flat panel displays of various sizes. (3) Effect corresponding to claim 3: Same address (320 bi
In t), since it is sufficient to switch the VRAM, it becomes possible to support various flat panel displays. (4) Effect corresponding to claim 4: Since the driver having the same number of columns as the number of columns of the VRAM is used, the controller circuit is simplified and the cost of the controller unit can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram illustrating an embodiment of a flat panel display according to the present invention.

FIG. 2 is a diagram showing a timing chart of each signal in FIG.

FIG. 3 is a diagram showing mounting configurations of various types of flat panel displays for explaining the present invention.

FIG. 4 is a diagram showing a configuration of an image memory unit according to the present invention.

FIG. 5 is a diagram showing a configuration diagram and a timing chart in the case of class 1 (color) according to the present invention.

FIG. 6 is a diagram showing a configuration diagram, a timing chart, and a cell in the case of class 2 (monochrome) according to the present invention.

FIG. 7 is a diagram showing a configuration diagram, a timing chart, and cells in the case of class 2 (monochrome, upper / lower split driving) according to the present invention.

FIG. 8 is a diagram showing a configuration diagram, a timing chart, and a cell in the case of class 2 (color) according to the present invention.

FIG. 9 is a diagram showing another embodiment of the image memory unit according to the present invention.

FIG. 10 is a diagram showing a configuration diagram and a timing chart in the case of class 1 (color) of the present invention.

FIG. 11 is a diagram showing a configuration diagram and a timing chart according to claim 4 of the present invention.

FIG. 12 is a view showing another embodiment of the flat panel display according to the present invention.

FIG. 13 is a view showing still another embodiment of the flat panel display according to the present invention.

FIG. 14 is a configuration diagram of a conventional liquid crystal display.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Host computer, 2 ... Bus, 3 ... Liquid crystal controller input part, 4 ... Image memory part, 5 ... Liquid crystal controller output part, 6 ... Liquid crystal driver part, 7 ... Liquid crystal panel.

Claims (4)

[Claims] 1. An input unit for inputting image data of a host computer, an image memory unit for storing image data from the input unit, a drive unit for applying a signal to an element of a liquid crystal panel unit, and the image memory unit. And a controller unit for transferring the image data of the above to the drive unit, and the image memory unit is divided into a plurality to form one image data,
A flat panel display, wherein the image data is transferred in parallel to the drive unit. 2. The image memory unit is composed of a multi-port RAM of 256 columns or less, and one pixel of the image memory unit corresponds to one address of the multi-port RAM, and various addresses are obtained by counting addresses in the column direction. The flat panel display according to claim 1, which is compatible with the system. 3. The flat panel according to claim 1, wherein the image memory unit is divided into blocks for a flat panel display, and various types are supported by counting addresses in a column direction. display. 4. The flat panel display according to claim 1, wherein the number of columns of the image memory unit is equal to the number of outputs of the driver unit or is an integral multiple thereof.