JP3534872B2 - Liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a liquid crystal display device suitable for a liquid crystal which responds at high speed. In particular, the present invention relates to a simple matrix type liquid crystal display device that performs multiplex driving by the MLS method (multiple line simultaneous selection method). Specifically, data processing, that is, receiving data to be displayed and performing an operation according to the MLS method,
The present invention relates to the configuration of a circuit that sends data to a display driver.

[0002]

2. Description of the Related Art Hereinafter, in the present specification, data electrodes are referred to as column electrodes, and scanning electrodes are referred to as row electrodes.

Conventional STN (super twisted nematic) liquid crystal element indicator is a liquid crystal display device which responds in dependence on the effective value of the applied voltage. However, such liquid
In crystal display device, the use of liquid crystal for high speed response, optical change between the ON state and the OFF state is small, there is a phenomenon (frame response) that the contrast is lowered, a problem.

In order to solve such a problem, recently,
The MLS method has been proposed. In the MLS method, in order to control the column display pattern independently, a constant voltage pulse train is applied to each row electrode applied simultaneously.

The selection pulse voltage group applied to each row electrode can be expressed as a matrix of L rows and K columns (hereinafter referred to as a selection matrix (A)). Since the selected pulse voltage series can be represented as mutually orthogonal vector groups, a matrix including these as column elements is an orthogonal matrix. At this time, the row vectors in the matrix are orthogonal to each other. The number L of rows corresponds to the number of simultaneous selections, and each row corresponds to each line. For example, L
The elements in the first row of the selection matrix (A) are applied to the line 1 in the selection lines of the book, and the selection pulse is applied in the order of the elements in the first column and the elements in the second column.

FIG. 4 is an explanatory view showing the concept of how to determine the sequence of voltage waveforms applied to the column electrodes. An example will be described in which a Hadamard matrix of 4 rows and 4 columns is used as the selection matrix. In the notation of the selection matrix (A),
1 means a positive selection pulse, and -1 means a negative selection pulse.

It is assumed that the display data on the column electrode i and the column electrode j are as shown in FIG. 4 (a). The column display pattern is represented as a vector (d) as shown in FIG. Here, when the column element is -1, it indicates on display, and when it is 1, it indicates off display. Assuming that the row electrode voltages are sequentially applied to the row electrodes in the order of the columns of the matrix, the column electrode voltage level becomes like the vector (v) shown in FIG. 4 (b). This is about the column display pattern (image display data) and the corresponding column of the selection matrix (row selection pattern),
Corresponds to the exclusive OR of each bit.
The waveform is as shown in FIG. In FIG. 4C, the vertical axis and the horizontal axis are arbitrary units.

In fact, in the case of partial line selection, it is preferable that the voltages are dispersed and applied within one display cycle in order to suppress the frame response of the liquid crystal display element. Specifically, for example, after the first element of the vector (v) for the first simultaneously selected row electrode group (hereinafter, referred to as a subgroup) is applied, the second simultaneously selected row electrode group is applied. Of the vector (v) for the row electrode group
The second element is applied, and so on.

[0009] When the display data has a gradation rather than a binary, the gradation can be realized by a frame decimation method.
In addition, JP-A-6-138854 and JP-A-6-2361.
Amplitude modulation as proposed in No. 67 can also be used.

[0010]

By the way, the frequency of an input image signal is generally different from the frequency of one display cycle on the liquid crystal display element side. The basic pulse width of the waveform for driving the liquid crystal display element is often set to about 10 to several tens of msec from the viewpoint of the multiplicity of scanning lines and the visibility of the display. Therefore, the frequency of one display cycle is often about 70 to 200 Hz, although it depends on the number of scanning lines. On the other hand, the frequency of the input image signal is 60
Often around Hz.

Therefore, it is necessary to adjust each timing. This adjustment is generally performed by temporarily writing the image signal in the memory and reading the written data asynchronously with the writing.

FIG. 5 shows a circuit configuration which the applicant has already proposed in order to reduce the number of such memories (Japanese Patent Laid-Open No. 6-348237).

Image data of 3 bits each of RGB having gradation information is turned on / off by the frame modulation circuit 110 every display cycle in response to image data input.
It is converted into bit data and output to the serial-parallel converter 120. The 1-bit serial data input to the serial-parallel converter 120 is converted into parallel data having a predetermined bit width. A shift register can be used as the serial-parallel converter 120.

A memory (VRAM) 130 stores image signals for one frame. At the time of input to the memory 130, RGB data are put together, a random access mode is used, and the data on the row electrodes corresponding to the same column electrodes are adjacent to each other for the L row electrodes selected at the same time. Store at L addresses. Reading from the memory 130 is performed in the high speed sequential access mode, and the output is sent to the format converter 190.

The format converter 190 is a circuit that rearranges the data format, and includes vertical-horizontal conversion and the like. The data-formatted signal is sent to the column voltage signal calculation circuit 180.

A signal from the row selection pattern generator 70 is also input to the column voltage signal calculation circuit 180 and used for calculation and formation of the column voltage signal. The signal output from the column voltage signal calculation circuit 180 is input to the column driver 80 to form a column voltage, and is input to the column electrode of the liquid crystal panel 40. On the other hand, the signal from the row selection pattern generator 70 is input to the row driver 90 to form a row voltage, and is input to the row electrode of the liquid crystal panel 40. The column driver 80 and the row driver 90 are controlled by the driver control circuit 60. Further, the image signal processing circuit 2
00 is controlled by the processing control circuit 150.
To simplify the drawing , the wiring of the processing control circuit 150 is omitted.

In this method, since the frame modulation is performed before storing in the memory, a relatively simple circuit is realized. However, the memory read timing is
It is synchronized with the timing of data input,
The high frame frequency on the liquid crystal display module side has not been fully utilized. That is, since the frame frequency is low, there is a problem that flicker is noticeable.

Further, the VRAM used as a memory is relatively expensive, and the cost reduction has not been sufficient for the entire system of the liquid crystal display device.

Further, there is a problem that power consumption and radiated noise are relatively large because high speed access to the memory is required.

[0020]

In order to solve the above-mentioned problems, the present invention is provided with a liquid crystal display module having a row electrode and a column electrode, and a liquid crystal display device for simultaneously selecting a plurality of lines is input. and a column driver for converting the image signal to the image signal processing circuit and said column voltage signal column voltage to be converted to the column voltage signal, the image signal processing circuit integrated times
Is a road, a total of a plurality of frame memories can be stored an image signal exceeding the one frame, before writing the input image signals to said plurality of memory once the input port to be saved from the plurality of memory Column voltage signal calculation circuit for calculating a column voltage signal from an image signal from the output port and a row selection pattern signal
And before transferring the image signal containing the gradation to the input port
Frame modulation circuit that converts binary signals of multiple frames
And transfer data between the input port and output port and the memory.
And a single memory bus is a signal line for feeding the input ports
Data transfer between port and memory and between output port and memory
Data transfer is performed by the memory bus, the frame frequency of the liquid crystal display module is set higher than the frame frequency of the input image signal, and timing adjustment between the two frame frequencies is performed by the image signal processing circuit, On the floor
The number of frames is greater than the number of frames used for
Provided is a liquid crystal display device having a small number of frames .

Further, the image signal processing circuit is provided with a frame modulation circuit for converting an image signal including gradations into a binary signal of a plurality of frames before being transferred to an input port, and the liquid crystal is provided. A display device is provided.

Further , the above liquid crystal display device for simultaneously selecting four lines is provided.

[0023]

According to the present invention, the image signal processing circuit has a plurality of memories capable of storing one frame of the image signal, and an input port for temporarily storing the input image signal before writing it into the plurality of memories. Since the output port for temporarily storing the outputs from the plurality of memories and the column voltage operation circuit for operating the column voltage signal from the image signal and the row selection pattern signal from the output port are provided, Since it is possible to write different data to the memory of,
Display with less flicker is possible.

Further, by providing a frame modulation circuit for converting an image signal containing gradations into a binary signal of a plurality of frames before being transferred to an input port, display with less flicker is possible and the number of memories is reduced. Can be reduced.

Further, since the read / write data width of the memory can be widened by forming the image signal processing circuit as an integrated circuit, a memory having a low access speed (for example, DRAM) can also be used.

[0026]

[Embodiment 1] FIG. 1 shows an embodiment of an image signal processing circuit 100 according to the present invention. The image signal processing circuit 100 includes a frame modulation circuit 1, an input port (shift register) 2, a memory (DRA
M) 3, 4, output port (shift register) 5, driver control circuit 6, row selection pattern generator 7, column voltage signal operation circuit 8, and processing control circuit 15.

The input image signal is a digital signal in parallel with each color of RGB and has a bit number according to the number of gradations. That is, in the case of 16 gradations, the data is 12 bits in total for 4 bits for each color, and in the case of 64 gradations, it is 18 bits in total for 6 bits for each color. Along with this image signal, a horizontal synchronizing signal, a vertical synchronizing signal, an enable signal, a clock signal, etc. are input to control the timing.

The frame frequency of the input image signal depends on the display controller, for example, RGB of VGA.
In the 64-gradation mode, it is usually 60 Hz. That is,
60 images are sent in 1 second. As aforementioned,
The frame frequency of the high-speed response STN liquid crystal display requires high-speed refreshing in order to suppress flicker, and is generally higher than the frame frequency of the input image signal. Particularly, in combination with frame modulation, a frame frequency of 100 Hz or higher is obtained. In the present invention, a timing adjustment between the two frame frequency is performed by the image signal processing circuit 100.

In this embodiment, the frame frequency of the input image signal is 60 Hz and the frame frequency of the liquid crystal display module is 120 Hz, and the image signal processing circuit 100 has a memory for two screens. .
Generally, in the driving method of the present invention, when the frame frequency of the liquid crystal display module is 60 to 120 Hz, the memory for two frames is provided, and the frame frequency of the liquid crystal display module is 120 to 1 Hz.
In the case of 80 Hz, driving is facilitated by providing a memory for 3 frames.

In the frame modulation circuit 1, the inputted multi-bit gradation data is converted into multi-frame 1-bit data. In the present embodiment, the spatial modulation is also used to shift the position of the ON / OFF pattern temporally to reduce the flicker, and 16 gradations are displayed using 8 frames. Data conversion in the frame modulation circuit 1 is performed by preparing a lookup table corresponding to 1 to 8 frames and referring to it. Of course, it is arbitrary to perform this data conversion by calculation without using a lookup table.

The input port 2 converts the data of a plurality of frames transferred from the frame modulation circuit 1 into parallel data for K pixels, and enables a large amount of data to be transferred to the memories 3 and 4 in the subsequent stage at a time. The larger the value of K, the larger the amount of data that can be transferred at one time. In this embodiment, a shift register is used as the input port 2.

The memories 3 and 4 can be used regardless of their formats as long as they have a capacity capable of storing data for one screen. In particular, if the image signal processing circuit of the present invention is integrated and a memory is built in, the read / write data width of the memory can be widened, so that a memory with a low access speed (for example, DRAM) can also be used. Using a low-priced DRAM is extremely advantageous from the viewpoint of cost. That is, since the present invention can use a low-cost and low-speed DRAM, it is very effective in terms of low power consumption and low radiation noise.

The output port 5 transfers the data transferred from the memories 3 and 4 to the column voltage signal operation circuit 8. In this embodiment, a shift register is used like the input port 2.

In this embodiment, reading and writing are performed on the same memory bus. The input port 2 and the output port 5 have a function of controlling so that read / write signals do not collide with each other in time and can be efficiently accessed.

The column voltage signal operation circuit 8 takes the exclusive OR of the input image data and the corresponding row selection pattern and counts the number of "1" and outputs it. This data is sent to the column driver 80 of the liquid crystal display module as display data.

The row selection pattern generator 7 generates a group <br/> Zukugyo selected pattern selection matrix. The row selection pattern is sent to the row driver 90 to form a row voltage, and is also sent to the column voltage signal operation circuit 8 to be used for an operation for forming a column voltage signal.

The driver control circuit 6 is a circuit for controlling the timing of the column driver 80, the row driver 90, etc. A clock, a latch signal and the like necessary for driver control are generated and output to the row selection pattern generator 7, the column driver 80 and the row driver 90.

The processing control circuit 15 is the image signal processing circuit 1.
00 is a circuit for controlling the operation and timing. In the figure, the connection is omitted.

FIG. 2 shows an example of the circuit of the column voltage signal operation circuit 8 described above . A 4-bit data signal is input to the exclusive OR gates 143, 143, .... A row selection pattern is also input to each of the exclusive OR gates 143 from the row selection pattern generator. Exclusive OR gate 143
Are added to the row electrodes simultaneously selected by the adder 141.

As shown in this figure, the display data sent to the column voltage signal calculation circuit 8 is data in the column direction equal to the number of simultaneously selected lines, and this is the data sent from the display controller to the image signal processing circuit 100. The transfer order is different.

FIG. 3 is a conceptual diagram showing the difference.
FIG. 3A shows a data transfer order sent from the display controller to the image signal processing circuit 100.
(B) shows the transfer order of the data sent to the column voltage signal calculation circuit 8.

That is, the image signal input to the image signal processing circuit 100 is normally sequentially transferred as RGB 1 set (that is, 1 pixel) serial data in the order from the upper left of the corresponding display screen in the horizontal direction. When all the data in the first line has been transferred, the process moves to the next line, and the data for one screen is sent in the same manner.

The format conversion for changing the transfer order is performed when reading / writing the memory. For example, when writing to the memory, the data is converted into a predetermined format using the random access mode and then written, and when read, it is read sequentially and at high speed, or when writing is performed at high speed in sequence, when writing and reading are specified in random access mode. There is a method to read in the format of. In any case, by integrating the image signal processing circuit and incorporating the memory in the integrated circuit, the data width for reading and writing of the memory can be widened. Therefore, by storing the serial data in the port as parallel data having a wide data width, it is possible to give a margin to the memory access time.

The operation of the circuit in this embodiment will be described below.

The image data input to the image signal processing circuit 100 is converted into a 1-bit signal of 8 frames as a whole by referring to the look-up table of the frame modulation circuit 1. In this embodiment, 1-bit signal for 8 frames is converted and output every 2 frames.

First, the 1-bit signals corresponding to the first frame and the second frame of these are output to the input port 2. The input port 2 temporarily stores an amount that can be written in the memories 3 and 4, and then writes the data corresponding to the first frame to the memory 3 and the data corresponding to the second frame to the memory 4. At the same time, the data corresponding to the first frame is first read from the memory 3 while utilizing the free time, and transferred to the column voltage signal calculation circuit 8 via the output port 5. Subsequently, the data corresponding to the second frame is read from the memory 4 and transferred to the column voltage signal calculation circuit 8 via the output port 5.

FIG. 6 is a timing chart showing an outline of the timing of writing and reading in the above memory. As shown in the figure, in this embodiment, output is performed at a frequency twice as high as the input.

The column voltage signal operation circuit 8 uses the row selection pattern from the row selection pattern generator 7 and the display data from the output port 5 to output the column driver 8 of the liquid crystal display module.
Is transferred to 0.

Next, the second image input signal is input from the display controller to the frame modulation circuit 1, and this time, it is converted into a 1-bit signal using the tables corresponding to the third and fourth frames. The data corresponding to the third frame is stored in the memory 3 and the data corresponding to the fourth frame is stored in the memory 4 via the input port 2.
Is written to.

With respect to these image data, the data corresponding to the third frame is read from the memory 3 while utilizing the vacant time, and the data is output via the output port 5.
It is transferred to the column voltage signal calculation circuit 8. Subsequently, the data corresponding to the fourth frame is read from the memory 4 and transferred to the column voltage signal calculation circuit 8 via the output port 5. The read / write timing and the calculation of the column voltage signal formation are the same as the data corresponding to the first frame and the second frame.

Thereafter, similarly, 5, 6 frames, 7, 8
Transferring data of the frame, ending one of the tone sequence.

As described above, by providing the memory for plural screens, different data can be written in the memory for plural screens. In addition, by performing frame modulation processing before writing to the memory, if the data stored in these memories is read in synchronization with the frame frequency of the liquid crystal display module, a display with less flicker can be obtained and the number of memories can be increased. Can be reduced. Also,
In the present invention, the display data is constant for one frame period of the liquid crystal display module, and the so-called voltage averaging method of the simple matrix liquid crystal driving method is established.

Although the above sequence has been described on the basis of the operation synchronized with the input signal, it is possible to drive even if the operation is not necessarily synchronized.

Further, if the image signal processing circuit has a memory for more than 2 frames, the data of a plurality of frames is converted into the data of the number of frames corresponding to the number of memories, and each is written in the memory. Good. For example, if a memory for three frames is provided, it is possible to process every three frames.

The data format conversion by the format converter may be used together. In this case, it may be performed before writing to the memories 3 and 4, or may be performed when reading.

[0056] The image processing circuit 100 of the present invention as an integrated circuit, when mounted on a circuit board of an LCD module MLS system, it is beneficial for maintain the interface compatibility with TFT module. Of course, it can also be mounted on a circuit board in a personal computer. Also, some or all of this circuitry may be incorporated onto the column driver chip.

[Embodiments 2 to 5] The following Embodiments 2 to 5 are cases in which upper and lower two-screen split driving is performed. Input frequency is 60Hz (1 cycle is 16.6mse)
c), the drive frequency on the module side is 120 Hz (one cycle is 8.3 msec). Driving was performed by selecting four lines simultaneously, and the cycle of one scan was set to 2.08 msec. In addition, as in the first embodiment, in order to display a predetermined gradation,
Use 8 frames.

Embodiment 2 The memory uses 3 frames. FIG. 7 shows the operation, particularly the timing of reading and writing to the memory.

The view of the figure is as follows. Memory 71
Each of ˜74 is a memory for ½ frame.
Binary display data for two screens can be stored. U
F1, UF2, ... Show the data of the first frame, the second frame, ... Of the upper screen. Also, LF1, LF
2, ... is the first frame of the lower screen, the second frame ...
.. shows the data.

FIG. 11 shows how to read and write symbols .
First, the horizontal axis of one cell corresponds to the time axis, and the length of the horizontal side of one cell represents a half cycle of the frequency of the input signal. Therefore, the length of two squares is the time corresponding to one cycle of the input signal. FIG. 11A shows the data F in the memory 1.
1 indicates that it is overwritten on F4, and one diagonal line in the cell indicates that the memory is scanned once at the time of the above-mentioned overwriting.

FIG. 11B shows the data F2 in the memory 2.
Is read out, and the four diagonal lines in the cell indicate that the memory is scanned four times during the above-mentioned reading. In this embodiment, since a selection matrix of 4 rows and 4 columns is used, calculation for 4 columns is required. Therefore,
Reading from the memory is performed by reading data four times by scanning four times.

FIG. 11C shows the data F1 in the memory 1.
Indicates that data is being read at the same time as is overwritten on F4. That is, it indicates that the memory is scanned once and the data is read four times during overwriting.

The read / write timing is as follows. After receiving the input signal at a frequency of 60 Hz and converting it into 1-bit data by the frame modulation circuit, the UF is stored in the memories 71 and 72 in the first half of one cycle of the input signal.
1. Write frame-modulated data corresponding to each frame of UF2. Next, in the latter half of one cycle of the input signal, UF1 is read from the memory 71 and the frame-modulated data corresponding to each frame of LF1 and LF2 is written in the memories 74 and 75, respectively.

Then, in the first half of one cycle of the next input signal, the frame-modulated data corresponding to each frame of UF3 and UF4 is written in the memories 71 and 73, respectively, and the UF2 is read from the memory 72 and the UF2 is read from the memory 74. L
Read F1 respectively. Then, in the latter half of one cycle of the input signal, UF3 is read from the memory 71 and LF2 is read from the memory 75, and the memories 74 and 7 are read.
The frame-modulated data corresponding to the respective frames of LF3 and LF4 is written in 6.

Reading and writing are similarly performed thereafter. Since four rows are simultaneously selected, reading is performed by four scans, and the frequency is 480 Hz. The advantage of this embodiment is that the content of the memory is constant at the time of reading and the voltage averaging method is almost completely established.

Embodiment 3 The memory uses 2.5 frames. Figure 8 shows its operation,
In particular, the timing of reading and writing to the memory is shown. The way of viewing the drawing is the same as in FIG. 7.

The read / write timing is as follows. After receiving the input signal at a frequency of 60 Hz and converting it into 1-bit data by the frame modulation circuit, the UF is stored in the memories 81 and 82 in the first half of one cycle of the input signal.
1. Write frame-modulated data corresponding to each frame of UF2. Next, in the latter half of one cycle of the input signal, UF1 is read from the memory 81, and the frame-modulated data corresponding to each frame of LF1 and LF2 is written in the memories 84 and 85, respectively.

Then, in the first half of one cycle of the next input signal, the frame-modulated data corresponding to each frame of UF3 and UF4 is written in the memories 81 and 83, respectively, and the memory 82 and UF2 are read from the memory 84. L
Read F1 respectively. Then, in the latter half of one cycle of the input signal, UF3 is read from the memory 81 and LF2 is read from the memory 85, and the memories 82 and 8 are read.
4, the frame-modulated data corresponding to each frame of LF3 and LF4 is written.

Reading and writing are similarly performed thereafter. Also in this case, since four rows are simultaneously selected, reading is performed by four scans, and the frequency is 480 Hz. The advantage that the voltage averaging method is almost completely established when the contents of the memory are read out is the same as that of the second embodiment, but there is an advantage that the memory used is smaller by half a frame.

Example 4 The memory is used for two frames. FIG. 9 shows the operation, particularly the timing of reading and writing to the memory. The way of viewing the drawing is the same as in FIG. 7.

The read / write timing is as follows. After receiving the input signal at a frequency of 60 Hz and converting it into 1-bit data by the frame modulation circuit, the UF is stored in the memories 91 and 92 in the first half of one cycle of the input signal.
1. Write frame-modulated data corresponding to each frame of UF2. At this time, since the memory 91 is read at the same time, half of the UF1 is read. Next, in the latter half of one cycle of the input signal, the UF2 is read from the memory 92 and the memories 93 and 94 are read.
The frame-modulated data corresponding to the respective frames of LF1 and LF2 is written in. At this time, since the memory 94 is being read at the same time, half of the LF2 is read.

Next, during the first half of one cycle of the next input signal, the frame-modulated data corresponding to each frame of UF3 and UF4 is written in the memories 91 and 92, and the memories 91 and 93 are read out. At this time, since the memory 91 is the timing when UF3 is overwritten on UF1, half is UF1 and half is UF3.
Will be read. LF1 is read from the memory 93.

During the latter half of one cycle of the input signal, the frame-modulated data corresponding to each frame of LF3 and LF4 is written in the memories 93 and 94, respectively, and
The memories 92 and 94 are read respectively. At this time, since LF4 is overwritten on LF2 in the memory 94, half of LF2 and half of LF4 are read. UF4 is read from the memory 92.

Reading and writing are similarly performed thereafter. Also in this case, since four rows are simultaneously selected, reading is performed by four scans, and the frequency is 480 Hz. Also in this method, the voltage averaging method is almost completely established. Even if the memory contents change during the four scans, two appropriate read frames (eg, UF
If it is 1, the first frame and the third frame are taken out and considered, which is equivalent to the case where the memory contents are constant during four scans. Further, there is an advantage that the memory used is smaller than that in the fourth embodiment by half a frame.

Embodiment 5 The memory uses 1.5 frames. FIG. 10 shows the operation, especially the timing of reading and writing to the memory. The way of viewing the drawing is the same as in FIG. 7.

The read / write timing is as follows. It is similar to the second to fourth embodiments that the input signal is received at a frequency of 60 Hz, the frame modulation circuit converts the input signal into 1-bit data, and then the reading and writing to the memory are performed.

In this embodiment, data reading is always performed from the memories 101 and 103. Writing is performed in the memories 101 and 102 in the first half of the input signal and in the memories 102 and 103 in the second half of the input signal. Then, during the first half of the input signal, data transfer (TRANSFER) is performed from the memory 102 to the memory 103, and during the latter half of the input signal, the memory 102 to the memory 10 are transferred.
For 1, the data is transferred. Specifically, it is as follows.

In the first half of one cycle of the input signal, the frame-modulated data corresponding to each frame of UF1 and UF2 is written in the memories 101 and 102, respectively. At this time, since the memory 101 is being read at the same time, the UF
Half of 1 will be read. Then, in the latter half of one cycle of the input signal, the memory 102 to the memory 10
While transferring the data UF2 to 1, the data LF2 and LF1 are written in the memory 102 and the memory 103, respectively. At the same time, data is read from the memories 101 and 103, respectively. At this time, since the data in the memory 101 has changed from UF1 to UF2, almost half of each data is read. Also, memory 1
In 03, since the data has changed from the previous data to LF1, LF1 is read by almost half.

Next, in the first half of one cycle of the next input signal, the data LF3 and UF4 are written in the memory 101 and the memory 102, respectively, while transferring the data LF2 from the memory 102 to the memory 103. At the same time, data is read from the memories 101 and 103, respectively. At this time, data is stored in the memory 101 from UF2 to UF2.
Since the number has been changed to 3, the number of times read is about half each. In addition, the data in the memory 103 is LF.
Since it has changed from 1 to LF2, only half of each is read.

Reading and writing are similarly performed thereafter. Also in this case, since four rows are simultaneously selected, reading is performed by four scans, and the frequency is 480 Hz. Also in this method, the voltage averaging method is almost completely established for the same reason as in the fourth embodiment. There is also an advantage that the memory used is smaller than that in the fourth embodiment by half a frame.

In the fourth and fifth embodiments, when the contents of the memory are changed during data reading, consideration should be given so that different frame data are not mixed in the subgroup, which increases the degree of freedom in the frame modulation method and causes waveform distortion. The non-uniformity of the brightness caused by is improved.

For that purpose, one subgroup of data may be stored in the additional memory (the number of simultaneously selected rows) at the time of writing and then transferred to the above-mentioned memory. further,
When using spatial modulation, in order to improve display uniformity, the capacity of the additional memory is set to (the least common multiple of the number of simultaneously selected rows and the number of rows of a matrix such as dither used for spatial modulation) × (space It may be a multiple of the number of columns of a matrix such as dither used for modulation.

For example, when the number of simultaneously selected rows is 4 and the dither matrix is an 8 × 8 matrix, a minimum of 8 × 8 additional memory may be used. Of course, for VGA display, an additional memory of 8 × 640 may be used.

As such additional memory, a plurality of line memories may be used in addition to the above memory, or a required capacity may be added to the above memory. When the required capacity is added to the memory, there is an advantage that a bus line used for data transfer can be commonly used.

[0085]

According to the circuit of the present invention, it is possible to use an inexpensive dynamic memory while realizing high-speed calculation of the column voltage required for the MLS driving method, and reduce the number of memories to simplify the circuit. Therefore, cost reduction, power consumption reduction, and radiation noise reduction can be achieved.

Further, since the data can be read out from the memory at a substantially high frame frequency without being restricted by the frame frequency of the input image data, display with suppressed flicker can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a column voltage signal arithmetic circuit.

FIG. 3 is a conceptual diagram showing a difference between a data transfer order from a display controller and a data transfer order sent to a column voltage calculation circuit.

FIG. 4 is a conceptual diagram showing the basic concept of the MLS method.

FIG. 5 is a block diagram showing a previously proposed example.

FIG. 6 is a timing chart showing memory read / write timing in the embodiment of the present invention.

FIG. 7 is a chart showing a timing of reading and writing a memory according to the second embodiment of the present invention.

FIG. 8 is a chart showing memory read / write timing in Embodiment 3 of the present invention.

FIG. 9 is a chart showing a timing of reading and writing a memory according to the fourth embodiment of the present invention.

FIG. 10 is a chart showing a timing of reading and writing from a memory according to a fifth embodiment of the present invention.

11 (a) to (c) are explanatory views showing how to see FIGS. 7 to 10. FIG.

[Explanation of symbols]

1: Frame modulation circuit 2: Input port 3, 4: Memory 5: Output port 6: Driver control circuit 7: Row selection pattern generator 8: Column voltage signal arithmetic circuit 10: Processing control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuyoshi Kawaguchi 1150 Hazawa-machi, Kanagawa-ku, Yokohama, Kanagawa Prefecture Asahi Glass Co., Ltd. Central Research Institute (72) Inventor Hiroyuki Mogi 1150, Hazawa-machi, Kanagawa-ku, Yokohama Asahi Glass Co., Ltd. Central Research Institute (72) Inventor Satoshi Nakazawa 1150 Hazawa-machi, Kanagawa-ku, Kanagawa Prefecture Asahi Glass Co., Ltd. Central Research Institute (72) Inventor Makoto Nagai 1150, Hazawa-cho, Kanagawa-ku, Yokohama City Asahi Glass Co., Ltd. 56) References JP-A-6-195043 (JP, A) JP-A-7-287552 (JP, A) JP-A-6-138853 (JP, A) JP-A-6-167947 (JP, A) Flat 5-46125 (JP, A) JP 5-88648 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 505- 580

Claims (6)

(57) [Claims] 1. A liquid crystal display device comprising a liquid crystal display module having row electrodes and column electrodes, wherein a plurality of lines are simultaneously selected, and an image signal processing circuit for converting an input image signal into a column voltage signal and the column. A column driver for converting a voltage signal into a column voltage, the image signal processing circuit is an integrated circuit, and a plurality of frame memories capable of storing image signals exceeding one frame in total, and input image signals Before writing to the plurality of memories, an input port that temporarily stores the output, an output port that temporarily stores the outputs from the plurality of memories, and a column voltage signal calculated from the image signal and the row selection pattern signal from the output port. Column voltage signal operation circuit for
Multiple frames before transferring the captured image signal to the input port
Frame modulation circuit that converts the binary signal of
And a signal line that transfers data between the output port and the memory
With one memory bus , between the input port and memory
Before data transfer and data transfer between output port and memory
Performed in serial memory bus, set higher frame frequency of the liquid crystal display module than the frame frequency of the input image signal, the timing adjustment between the two frame frequency is performed in the image signal processing circuit, predetermined gradation Frames more than the number of frames used to display
A liquid crystal display device characterized by a small number of frames in the frame memory . 2. An additional memory for storing data for one subgroup.
Memory is provided so that one subgroup of data can be written when writing data.
Data is temporarily stored and then transferred to a memory.
The described liquid crystal display device. 3. The method according to claim 1, wherein four lines are simultaneously selected.
2. The liquid crystal display device according to item 2. 4. The liquid crystal display device according to claim 1, 2 or 3, wherein the plurality of frame memories includes memories exceeding two frames. 5. The liquid crystal display device according to claim 1, wherein the plurality of frame memories include memories for 1.5 frames. 6. The liquid crystal display device according to claim 1, wherein the frame memory is a DRAM.