JP2752623B2 - Driving method of TFT liquid crystal display device and TFT liquid crystal display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of a TFT liquid crystal display device and a TFT liquid crystal display device, for example, to a technology effective when used for a defect repair technology of a TFT (thin film transistor). It is. [Prior Art] As a technique for increasing the yield of liquid crystal display panels, a technique employing a redundant configuration has been proposed, for example, by Nikkei McGraw-Hill 1986.
Proposed by "Nikkei Electronics" dated December 15, pp. 193-209. [Problems to be Solved by the Invention] In the above-mentioned redundant configuration, two TFT transistors are provided for one pixel electrode, and when a defect occurs, the TFT is switched to a spare TFT. In this configuration, it is necessary to form a spare TFT transistor and a scanning line electrode for one pixel electrode, so that the aperture ratio is sacrificed. In addition, since laser trimming technology is used for defect relief, the number of manufacturing steps and equipment increases. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of driving a TFT liquid crystal display device capable of substantially relieving defects of a TFT transistor with a simple configuration, and an optimum method for implementing the driving method.
It is to provide a TFT liquid crystal display device. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. [Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is,
In the driving method of the TFT liquid crystal display device, all of the scanning signals are provided in a vertical blanking period in one frame period and in a first period different from the vertical blanking period in the one frame period. A black display signal is applied to all the signal lines in a state where the non-selection signal is applied to the lines and the scanning signal line selection operation is stopped. [Operation] According to the above-described means, the scanning signal line selection is performed during a vertical blanking period during one frame period and a first period different from the vertical blanking period during the one frame period. Since the black display signal is applied to all the signal lines while the operation is stopped, the signal applied to the defective pixel having the TFT transistor whose source and drain are short-circuited is the display data during the display period. , And a vertical blanking period in one frame period, and a black display signal in a first period different from the vertical blanking period in one frame period. Becomes Thereby, the brightness of the defective pixel can be brought close to the black level, and the defective pixel can be made inconspicuous. Embodiment FIG. 1 is a timing chart of an embodiment for explaining a method of driving a color liquid crystal display panel having an active matrix structure. In the color display device used in this embodiment,
As will be described later, in order to relieve defects, one frame period is composed of 304 horizontal periods even though there are 200 color pixel lines composed of three primary color dots, and almost the first horizontal period. The vertical synchronizing signal VSYN is generated in synchronization. The vertical blanking period is from the 303rd horizontal period of the previous frame to the 2nd horizontal period of the frame. Therefore, the display operation in one frame is performed in 200 horizontal periods corresponding to 1 to 200 lines from the third horizontal period to the 202nd horizontal period, and the remaining 100 horizontal periods are used for defect relief. During the blanking period. In other words, during the horizontal period from the 203rd period to the 302nd period, the scanning operation is stopped and the signal of the black level (non-lighting level) is supplied to the signal line. One horizontal period is defined by the horizontal synchronizing signal HSYN, and as shown enlarged at the head, while the display timing signal DST is at a high level, color display data composed of R, G, and B is displayed. The data is valid display data, and the rest is horizontal retrace data (black display). As the effective display data, red (R), green (G) and blue (B) are each composed of 640 dots (bits). Therefore, the display timing signal DST is not formed from the 203rd to the vertical blanking period. Among the defects of the TFT transistor, those that do not turn on are not conspicuous as defects because the corresponding pixels are not lit (black display). On the other hand, when the drain and source of the TFT transistor are short-circuited, the level of the signal line electrode is always transmitted to the pixel electrode, and a bright display is performed according to the supplied signal. Become. In particular, when the surrounding display is close to black, if there is the above-described defect, only that portion performs a bright display, which is extremely annoying. In this embodiment, paying attention to this fact, an extra horizontal period consisting of the 203rd to 302nd periods is inserted in one frame period as described above, and during this period, the scanning operation is stopped. By supplying the black level to the signal line as described above, a blanking period similar to the vertical blanking period is set. In this configuration, even if a signal of the lighting level is transmitted as a worst case to a signal line to which a defective pixel is coupled in the display period, the black level is not changed in a blanking period inserted thereafter. Reportedly. On the other hand, in a pixel having no defect as described above, the TFT transistor is kept off in response to the stop of the scanning operation, and the display data written in the display period is held.
As a result, only for the defective pixel, the signal in the display period and the black level in the blanking period are averaged, and a display having an intermediate brightness is displayed. Therefore, even in the roast case as described above, the defect can be made inconspicuous. By the way, in the color display panel, it is necessary to supply R (red), green (G), and blue (B) color data each consisting of 640 dots in one horizontal period. The liquid crystal display frame frequency depends on the data transfer speed of an X (signal line) drive circuit that performs serial / parallel conversion of the color data. For example, if the maximum transfer rate is
6MHz HD6610 sold by Hitachi, Ltd.
When “6” is used, the frame frequency f is obtained by the following equation (1). f = 1 / ((1/6 MHz) × (640/4) × (200 × 3)) = 62.5 Hz (1) Here, 640/4 of the second term of the denominator is in units of 4 bits. The color data is transferred serially, and the third term 200 × 3 means that one line of one color pixel is constituted by three primary color dots of R, G and B. ing. However, as described above, the actual line in one frame has 20 pixel rows.
Despite 0 lines, 300 lines of display time are required. Therefore, the actual frame frequency of the color display device to which this embodiment is applied is expressed by the following equation (2). f ′ = 1 / ((1/6 MHz) × (640/4) × (300 × 3)) ≒ 41.7 Hz (2) If the frame frequency f is only 41.7 Hz as described above, the active matrix In the liquid crystal display panel having the above configuration, it is necessary to write color data in both positive and negative polarities for AC driving of the liquid crystal, and the substantial frame frequency f ′ is about half of the frame frequency f ′. The frequency drops to 20.8 Hz, and the image quality deteriorates. In order to prevent such a decrease in frame frequency, a color display device employing the above-described driving method has the following configuration. FIG. 2 is a block diagram showing one embodiment of a color display device to which the present invention is applied. The color display device of this embodiment uses an active matrix color liquid crystal display panel LCD. Although not particularly limited, the color liquid crystal display panel LCD is capable of displaying color pixels of 640 dots × 200 lines as shown in detail in FIG. One line is composed of a combination of red, green, and blue color filters in the form of three horizontal stripes.
Y1-Y3, Y4-Y6 ... Y598- shown as examples
A Y selection (scanning) line such as 600 is provided.
Further, signal lines X1 to X640 are arranged in the vertical direction. Therefore, the color liquid crystal display panel LCD has 600 Y selection lines in the vertical direction as described above, and the total number of dots is 640 × 600. In FIG. 2, a color display device is provided with color display data consisting of R, G, and B. The combination of these three primary color data makes it possible to display eight color (including white and black) color pixels.
The dock clock signal CLK is supplied in synchronization with the display data R, G, and B. The display timing signal DST is
This is a timing signal that is displayed as visible information (valid display data) of the display data when it is set to a high level, and is set as a horizontal retrace period when it is set to a low level.
The horizontal synchronization signal HSYN is a timing signal for controlling one line, and the vertical synchronization signal VSYN is a timing signal for controlling one frame. The serial / parallel conversion circuit SPC receives the above three color display data R, G and B, and receives a dock clock signal.
In accordance with the CLK and the display timing signal DST, the color display data R, G, and B input serially in synchronization with each other are changed to 4-bit parallel data.
These 4-bit parallel data are supplied to the input of a write memory selection circuit (hereinafter simply referred to as a multiplexer) MPX1. The multiplexer MPX1 selectively selects the color display data converted into the 4-bit parallel data,
In response to a control signal R / W described later, the first line memory LM1
Alternatively, it is supplied to the write input terminal of the second line memory LM2. The first and second line memories LM1 and LM2 each have a storage capacity for storing color display data corresponding to one line of the color liquid crystal display panel LCD.
That is, since the display panel LCD has 640 dots in the horizontal direction, a storage capacity of 640 × 3 bits is required. As described above, since the parallel data formed by the serial / parallel conversion circuit SPC is input to the line memories LM1 and LM2, memory access is performed in units of 4 × 3 bits. Therefore, the line memories LM1 and LM2 have addresses 0 to 159, respectively, as described later. Although not particularly limited, the above line memories LM1 and LM2
Uses a static RAM (random access memory). Instead of this configuration, a dynamic memory cell can be used. This is because the line memories LM1 and LM2 alternately perform a write operation and three read operations every horizontal period, as described later. Since such a write operation and a read operation are always performed at the extremely short time interval as described above,
Since a refresh operation is always performed, a special refresh operation is unnecessary even when a dynamic memory cell is used, so that memory access can be performed in the same manner as when a static memory cell is used. By doing so, the occupied area of the line memories LM1 and LM2 can be further reduced in combination with the small storage capacity. A read memory selection circuit (hereinafter simply referred to as a multiplexer) MPX2 is provided on the read output terminal side of the first and second line memories LM1 and LM2. The multiplexer MPX2 performs a switching operation complementarily to the multiplexer MPX1 for writing. For example, when the multiplexer MPX1 for writing transmits parallel display data to one line memory LM1 (or LM2) in response to the control signal R / W, the multiplexer MPX2 for reading is replaced with the other line memory LM2 (or Select and output the read data of LM1). The write control circuit WC receives the dot clock signal CLK, the display timing signal DST, and the horizontal synchronization signal HSYN,
The control signal R / W and the write address signal WA are generated. Further, the read control circuit RC outputs the horizontal synchronization signal HSYN
In response, a read address signal RA and a 2-bit color selection signal CS are generated. For example, if the control signal R / W is at a high level by the write control circuit WC, the multiplexer MPX1 selects the first line memory LM1. The read / write control circuit RWC, according to the control signal R / W,
Write address signal generated by write control circuit WC
WA is output as the address signal A1 of the line memory LM1. As a result, the color display data R, G, and B of three primary colors serially input for one line are written to the line memory LM1. On the other hand, the read address signal RA generated by the read control circuit RC is transmitted by the read / write control circuit RWC as the address signal A2 of the second line memory LM2. As a result, the read operation is performed on the live memory LM2, and the stored color display data is
It is supplied to the color selection circuit CSEL through X2. As described above, since the three primary color data R, G, and B are output in parallel in units of 4 bits from the line memory LM2, the color selection circuit CSEL outputs the three primary color data R, G, and B in response to the color selection signal CS. Output in chronological order in the order of B. In this embodiment, in order to increase the frame frequency equivalently, each color data which is divided into colors and output serially is not particularly limited by the divided data control circuit DDC, but is divided into two for each color. Divided. Accordingly, the X drive circuits XDVL and XDVR are also divided into two. That is, the display screen of the color liquid crystal display panel LCD is apparently divided into upper left (L) and right (R), and the X drive circuits XDVL and XDVR are provided corresponding to each of them. In this configuration, the X driving circuits XDVL and XDVR do not have display data driving capability corresponding to half of the 320 signal electrodes, although the color liquid crystal display panel has 640 signal line electrodes. Then, since a configuration is adopted in which two display data are simultaneously taken, the transfer speed of the display data can be doubled as viewed from the liquid crystal display panel LCD. In other words, the time required to capture display data for one line can be reduced by half. The timing control circuit TC outputs the display timing signal DS
T and the vertical synchronization signal VSYN, the X drive circuit XDV
The data shift clock signal DSC and the line clock signal LCK necessary for the operation of the L and XDVRs and the Y drive circuit YDV are formed.
Further, the timing control circuit TC generates a line head clock signal LFS supplied to the Y drive circuit YDV. The Y drive circuit YDV captures the high level of the clock signal LFS at the falling edge of the line clock signal LCK, and sets the scanning line Y1 to the high level. Then, the line clock signal
The above high level is changed to Y in synchronization with the falling edge of LCK.
2. A vertical scanning operation is performed by shifting in correspondence with Y3... Y600. In order to prevent the scanning operation, the signal LFS may be set to a high level. FIG. 3 shows the above color liquid crystal display panel LCD and its X drive circuits XDVL, XDVR and Y drive circuit YDV. As described above, the color liquid crystal display panel LCD has a horizontal stripe color filter, and one line is composed of three dot rows of R, G and B. The Y drive circuit YDV has the scanning lines Y1 to Y600 as described above, takes in the line head clock LFS generated at the beginning of the frame, synchronizes with the line clock signal LCK, and shifts it to select Y. Form a signal. Therefore, one horizontal display period is temporally divided into three as described later, and the X drive circuits XDVL and XDVR output 64 horizontal periods.
When R1 data of 0 dots is transmitted, the scanning line Y1 is selected, when G1 data is transmitted, the scanning line Y2 is selected, and when B1 data is transmitted, the scanning line Y3 is selected. Is done. Thus, the color image data of the first line 1 is written to each pixel in one horizontal period. In the next horizontal period, when 640-dot R2 data is transmitted from the X drive circuits XDVL and XDVR, the scanning line Y4
Is selected and when G2 data is sent out, scan line Y5
Is selected and the scan line Y6 is
Is selected. Thus, the color image data of the next line 2 is written to each pixel. Hereinafter, similarly, color pixel data R200, G up to the last line 200
200 and B200 are written to each pixel. Further, in this embodiment, an extra 100-line dummy writing period is provided as shown in FIG. 1 for defect relief, and the above-mentioned black level signal is supplied. During this time, all the scanning lines are left in a non-selected state. Thus, writing of one frame is performed. The same display data R1, G
1, B1 to R200, G200, and B200 are inverted in polarity and output from the X driving circuits XDVL and XDVR, and the same scanning line selection operation as described above is performed in synchronism therewith. Therefore, it is necessary for the liquid crystal display panel LCD having the active matrix configuration to spend two frames having the above-described dummy writing period in order to display one screen. FIG. 4 is a timing chart for explaining an example of the color display data written in the line memory LM1 or LM2. The serial / parallel conversion circuit SPC converts the serially input color display data of each color (R, G, and B) into parallel in units of 4 bits to form write parallel data. That is, signals R0 to R159, G0 to G159, and B0 to B159 are written to the line memory LM1 or LM2 in units of 4 bits corresponding to each color. As a result, color display data of 160 × 4 = 640 bits is written for each color as a whole. FIG. 5 shows an address map of the line memories LM1 and LM2. In this embodiment, since the write parallel data is input in units of 4 × 3 bits as described above, the line memory LM
1 and LM2 have addresses 0 to 159, respectively. In this embodiment, in order to increase the frame frequency as described above, as described above, the X driving circuit is used as XDVL and XD
It is divided into two like VR. To make it correspond, X
The signals R0 to 879, G0 to G79 and B0 to B79 to be made to correspond to the drive circuit XDVL are represented by the even addresses 0, 2,.
Signals R80 to R159, G80 to G1 that should correspond to the drive circuit XDVR
59 and B80 to B159 are odd addresses 1, 3,... 159
Respectively. Thus, in the line memories LM1 and LM2, odd-numbered addresses store left-side data, even-numbered addresses store right-side data, and one address stores 4 × 3 = 12-bit color display data. FIG. 6 is a timing chart for explaining a read operation from the line memory LM1 or LM2. The address signal RA formed by the read control circuit RC is
Multiplexer MPX1 according to the level of control signal R / W
The switching operation of the read / write control circuit RWC and the other line memory LM2 (or LM1) are performed by the read / write control circuit RWC while the above-described writing is performed on the line memory LM1 (or LM2). The read signal is transmitted and output by switching the multiplexer MPX2. At this time, the read control circuit RC generates the address signal RA so that the selected line memory LM2 (or LM1) is read three times in one horizontal period. Therefore, the read parallel data passed through the multiplexer MPX2 is repeatedly output from R0 to R159, G0 to G159, and B0 to B159 three times. A color selection signal CS consisting of two bits is formed according to the number of times of reading by the read control circuit RC. For example, in the first reading, the color selection signal CS is set to 0 (00), and the color selection circuit CSEL outputs R0 to R159 among the color display data composed of the three primary colors as described above. In the second reading, the color selection signal CS is set to 1 (01), and the color selection circuit CSEL outputs G0 to G159 among the color display data composed of the three primary colors as described above. In the third reading, the color selection signal CS is 2 (1
0), and the color selection circuit CSEL outputs B0 to B159 among the color display data composed of the three primary colors as described above. Further, the color display data R0 to R159 are divided into odd addresses and even addresses of the line memories LM1 and LM2.
Since G0 to G159 and B0 to B159 are stored, if the read address signal RA is generated in order as 0 to 159, the left and right alternate color display as R0 and R80, R1 and R81. Data is output. Divided data control circuit DDC
Temporarily latches the left and right color display data corresponding to the X drive circuits XDVL and XDVR as described above,
And supply to XDVR. For example, if the serial transfer speed of the X drive circuits XDVL and XDVR is 6 MHz as described above, the line memories LM1 and LM2 are read at twice the speed. The parallel color data divided as described above is represented by X
In driving times XDVL and XDVR, R0 to R79 and R80 respectively
The color display data up to R159 is shifted in 4-bit units in synchronization with the data shift clock DSC, and when the capture is completed, it is distributed to the X1 to X640 color display data and output in parallel in synchronization with the line clock LCK I do. G0 to G79, G80 to G159 and B0 to B79, B80
The input and output of the color display data from B159 to B159 are performed in the same manner as described above. However, the Y drive circuit YDV
Since the selection line is switched from Y1 to Y2 and Y3 in synchronization with the line clock LCK, the display operation corresponding to each color line is performed. In this embodiment, by using two line memories as described above, while the display data is being written to one of the line memories, the other line memory which has already been written is read to perform the display. Since it operates, it has only a storage circuit having a storage capacity of two lines. Therefore, even a color display device having a large screen and high image quality as described above can be configured with a small number of storage circuits. Further, since the X drive circuit is divided into two, the time required for the transfer operation is halved. In other words, from the viewpoint of the entire display device, this is equivalent to doubling the transfer speed of the X drive circuit. Therefore, the frame frequency can be increased to 125 Hz, as is clear from the above description. This allows for defect relief
The dummy display period for 100 lines is inserted to stop the substantial display operation, and during that time the black level is supplied to the signal line, and for the AC drive of the liquid crystal display panel LCD,
Even if the same display data is written in positive and negative polarities, the frame frequency is 41.7 Hz, and higher stable image quality can be obtained as compared with a home television receiver. This makes it possible to equivalently increase the frame frequency while using the existing X drive circuit, so that the above-described defect remedy method can be easily implemented only by the timing signal change processing. In this configuration, only one TFT transistor is provided for a pixel constituting the liquid crystal display panel, and accordingly, only one scanning line electrode is provided. Therefore, the aperture ratio can be increased. In addition, a special process and equipment for defect remedy become unnecessary. The operational effects obtained from the above embodiment are as follows. (1) Vertical retrace period during one frame period, and 1
In a state where the scanning signal line selection operation is stopped during a first period different from the vertical blanking period in one frame period,
Since the black display signal is applied to all the signal lines, the signal applied to the defective pixel having the TFT transistor whose source and drain are short-circuited is the signal corresponding to the display data during the display period and 1 The vertical blanking period in one frame period and the black display signal in a first period different from the vertical blanking period in one frame period are averaged. As a result, the brightness of the defective pixel can be brought close to the black level, and the effect that the defective pixel can be made inconspicuous can be obtained. (2) According to the above (1), only one TFT transistor is provided for a pixel constituting a liquid crystal display panel, and accordingly, only one scanning line electrode is provided. Therefore, it is possible to increase the aperture ratio, and it is possible to obtain the effect that the process and equipment for the special defect relieving process become unnecessary. (3) First and second line memories for storing display data corresponding to one line of the display panel are provided, and the first and second line memories are alternately controlled for writing and reading. The display data read from the first or second line memory is divided and supplied in parallel in accordance with the divided X drive circuit.
In this configuration, even if an existing X drive circuit is used, the transfer rate can be equivalently increased, and the frame frequency can be increased. Therefore, there is an effect that a frame for supplying a black level for defect remedy can be provided without sacrificing display quality. Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor. 1 for defect relief
The period during which the black level is provided during the frame period may be, for example, a horizontal period twice as long as the display line in one frame, and may be a half of the horizontal period. In this case, the defective pixel can be made less noticeable because the black level can be made longer at the rate of the supplied time. Even in this case, the frame frequency can be maintained at 31.5 Hz by using the display device as shown in FIG. As described above, when the proportion of the frame supplying the black level is increased, the substantial frame frequency is correspondingly reduced. Therefore, the compensation may be performed by dividing the X drive circuit into three or more N circuits. . Alternatively, an X drive circuit with a higher transfer speed may be developed. The specific configuration of the memory control circuit for alternately performing the write / read operation of the two line memories can employ various embodiments. The liquid crystal display panel may perform black and white (bright and dark) display in addition to the above-described color display. INDUSTRIAL APPLICABILITY The present invention can be widely used for a liquid crystal driving system having an active matrix configuration. [Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the driving method of the TFT liquid crystal display device of the present invention,
During a vertical blanking period in one frame period and a first period different from the vertical blanking period in one frame period, all the signal lines are stopped while the scanning signal line selection operation is stopped. Since a black display signal is applied, a signal applied to a defective pixel having a TFT transistor whose source and drain are short-circuited is a signal corresponding to display data during a display period and a signal corresponding to display data during one frame period. The vertical blanking period and the period of one frame period are averaged with the black display signal in a first period different from the vertical blanking period. Thereby, the brightness of the defective pixel can be brought close to the black level, and the defective pixel can be made inconspicuous. (2) According to the driving method of the TFT liquid crystal display device of the present invention,
It is only necessary to provide one TFT transistor for the pixels constituting the liquid crystal display panel, and accordingly only one scanning line electrode is required, so that the aperture ratio of the pixels can be improved. (3) According to the TFT liquid crystal display device of the present invention, by using the first and second line memories, the read display data is sequentially supplied to a plurality of divided X drive circuits. Even if an existing X drive circuit is used, the transfer rate of display data can be equivalently increased, so that the frame frequency can be increased. Thus, even when the method of driving the TFT liquid crystal display device of the present invention is employed, a period for supplying a black-level signal for defect repair can be provided in one frame without deteriorating the display quality.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a timing chart for explaining an embodiment of a liquid crystal drive system according to the present invention, and FIG. 2 is an embodiment of a color display device to which the present invention is applied. FIG. 3 is a block diagram showing one embodiment of the color liquid crystal display panel, FIG. 4 is a timing chart for explaining parallel data written to the line memory, and FIG. FIG. 6 is a timing chart for explaining the parallel data read from the line memory. SPC: Serial / parallel conversion circuit, MPX1: Multiplexer (write memory selection circuit), MPX2: Multiplexer (read memory selection circuit), LM1, LM2: Line memory, RWC: Read / write control circuit, TC ... ... Timing control circuit, LCD ... Color liquid crystal display panel, WC ... Write control circuit, RC ... Read control circuit, CSEL ... Color selection circuit, DDC ... Divided data control circuit, XDVL, XDVR ... X drive Circuit, YDV ... Y drive circuit

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Mitsuhisa Fujita 3300 Hayano Mobara-shi, Chiba Inside Mobara Plant, Hitachi, Ltd. (72) Inventor Shinji Matsumoto 3300 Hayano, Mobara-shi, Chiba Mobara Plant, Hitachi Ltd. (72) Inventor Hiroyuki Mano 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Microelectronics Equipment Related Research Laboratory, Hitachi, Ltd. (56) References JP-A-61-128292 (JP, A) JP-A-59 −86092 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G09G 3/36 G02F 1/133

Claims (1)

(57) [Claims] 1. In a vertical blanking period during one frame period and a first period different from the vertical blanking period during the one frame period, all A TF characterized in that a black display signal is applied to all signal lines in a state where the non-selection signal is applied to the scanning signal lines and the scanning signal line selection operation is stopped.
Driving method of T liquid crystal display device. 2. A liquid crystal display panel having color filters of three primary colors in the form of horizontal stripes; M X drive circuits to which display data is input and which outputs signals corresponding to the input display data to signal lines in parallel; A Y-driving circuit for sequentially applying a selection signal to the scanning signal lines other than the selected scanning signal line, and applying a non-selection signal to the scanning signal lines, and sequentially selecting the scanning signal lines. The Y drive circuit applies non-scan signals to all the scanning signal lines during a vertical blanking period during one frame period and during a first period different from the vertical blanking period during the one frame period. Applying a selection signal, wherein the M X drive circuits have a first blanking period different from the vertical blanking period during a vertical blanking period during one frame period and during the one frame period. Within the period, all A first and second line memories for storing display data of three primary colors corresponding to one line of the liquid crystal display panel, respectively; The display data of the three primary colors corresponding to the one line is stored in such a manner that the storage order of the display data is arranged in the order of the display data supplied to the M X drive circuits.
While the display data of the three primary colors are alternately written to the first line memory and the second line memory, and the display data of the three primary colors are written to one of the line memories, the display data of the three primary colors is sequentially written three times from the other line memory. A memory control circuit for reading, and display data selection for sequentially selecting display data of one color among display data of three primary colors read from the first line memory or the second line memory in accordance with the number of times of reading. A TFT liquid crystal display device comprising: a circuit; and a display data division circuit that sequentially supplies one-color display data from the display data selection circuit to the M X drive circuits.