JP2590782B2 - Liquid crystal display - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color display device, for example, a high-resolution color display having a relatively large screen suitable for a display device in a computer system or various control devices. The present invention relates to technology that is effective when used with a liquid crystal panel. 2. Description of the Related Art An example of a color liquid crystal display device is disclosed in JP-A-59-212101. This color liquid crystal display device has a configuration in which color display data is stored once in a frame memory, and then color data consisting of red, green and blue is repeatedly read out for each line of the color liquid crystal display panel, and is provided to the color liquid crystal display panel. Has become. In the above-described color liquid crystal display device, when a color liquid crystal display panel having a relatively large screen such as 640 × 200 dots is driven, one screen area is correspondingly driven. There is a problem that the storage capacity of the frame memory increases because the display data increases. [0004] In the above color display panel,
In one horizontal period, it is necessary to supply each color data of red (R), green (G), and blue (B) composed of 640 dots. The liquid crystal display frame frequency is X (signal line) for performing serial / parallel conversion of the color data.
It depends on the data transfer speed of the drive circuit. For example, when using “HD66106” sold by Hitachi, Ltd. with a maximum transfer rate of 6 MHz, the frame frequency f
Is obtained by [Equation 1]. F = 1 / (1/6 MHz) × (640/4) × (200 × 3) = 62.5 Hz where 640/4 of the second term of the denominator is a unit of 4 bits. Means that color data is transferred serially, and 200 × 3 in the third term means that one primary color dot (line) is composed of three primary color lines of R, G and B. doing. As described above, when the frame frequency f is 62.
If the frequency is only 5 Hz, flickering of the screen and deterioration of the image quality at high temperatures become a problem in the color liquid crystal display panel. That is, in a liquid crystal display panel of an active matrix configuration, it is necessary to write color data in both positive and negative polarities for AC driving of the liquid crystal, and the substantial frame frequency f is about half of the frame frequency f. This is because the frequency drops to 31 Hz. An object of the present invention is to provide a color display device capable of performing a display operation at a high frame frequency with a simple configuration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. In order to achieve the above object, the present invention provides a liquid crystal display panel having a signal line of M dots, and a display area of M dots of the liquid crystal display panel. N (N) each having a continuous display dot
N data drive circuits for supplying an image signal to each of the signal lines in each of the partial regions of 2 or more natural numbers), a storage circuit for storing at least M dots of display data to be displayed on the liquid crystal display panel, The display data input as continuous display data is written to the storage circuit, and the display data for M dots stored in the storage circuit is to be displayed in each of the N partial regions. A memory control circuit for reading out N sets of display data composed of the following units from the storage circuit in a predetermined order, and sequentially holding the read out sets of N sets of display data, in parallel with the N data drive circuits. And a divided data control circuit for outputting the divided data control circuit. According to the above-mentioned means, the storage circuit for storing the color display data can have a small storage capacity because of adopting a configuration for storing the data for the lines, and the X drive circuit can be divided into Correspondingly, since the display data can be input in parallel, the transfer speed in the X drive circuit can be equivalently increased, so that a high quality display screen can be obtained. FIG. 1 is a block diagram showing one embodiment of a color display device according to the present invention. The color display device of this embodiment uses an active matrix color liquid crystal display panel LCD. Although not particularly limited, as shown in FIG.
Display of color pixels of 0 dots × 200 lines is enabled. One line is formed of a combination of three color filters of red, green and blue in the form of a horizontal stripe.
3, Y4 to Y6 ... Y598, Y599, Y60
A Y selection (scanning) line such as 0 is provided. Further, signal lines X1 to X640 are arranged in the vertical direction.
Therefore, the color liquid crystal display panel LCD has 600 Y selection lines in the vertical direction as described above, and the total number of pixels is 640 × 600. In FIG. 1, the color display device includes R, G
And B are provided. By combining the color data consisting of these three primary colors,
Display of color pixels of eight colors (including white and black) is enabled. The dot clock signal CLK is equal to the display data R,
It is supplied in synchronization with G and B. Display timing signal D
ST is a timing signal that is displayed as visible information (valid display data) of display data when it is set to a high level, and is set as a horizontal blanking period when it is set to a low level. The horizontal synchronizing signal HSYN is a timing signal for controlling one line, and the vertical synchronizing signal VSYN is a timing signal for controlling one frame. The serial / parallel conversion circuit SPC receives the above three color display data R, G, and B, and in synchronization with the dot clock signal CLK and the display timing signal DST, the serially input color display data R, G, and B, respectively. G and B are each changed to 4-bit parallel data. These 4-bit parallel data are supplied to the input of a write memory selection circuit (hereinafter simply referred to as a multiplexer) MPX1. The multiplexer MPX1 selectively converts the color display data converted into 4-bit parallel data into a first signal in accordance with a control signal R / W described later.
To the write input terminal of the line memory LM1 or the second line memory LM2. The first and second line memories LM1, L
M2 has a storage capacity for storing color display data corresponding to one line of the color liquid crystal display panel LCD. That is, since the display panel LCD has 640 dots in the horizontal direction, a storage capacity of 640 × 3 bits is required. Since the parallel data formed by the serial / parallel conversion circuit SPC is input to the line memories LM1 and LM2 as described above, memory access is performed in units of 4 × 3 bits. Therefore, the line memories LM1, LM2
Have addresses 0 to 159 as described later. Although not particularly limited, a static RAM (random access memory) is used as the line memories LM1 and LM2. Instead of this configuration, a dynamic memory cell can be used. Because the line memories LM1 and LM2 are
As will be described later, a writing operation and three reading operations are alternately performed every one horizontal period. Since such a write operation and a read operation are always performed at the extremely short time interval as described above, a refresh operation is also always performed, and even if a dynamic memory cell is used, a static memory cell can be used. Memory access can be performed in the same manner as used. By doing so, the occupied area of the line memories LM1 and LM2 can be further reduced in combination with the small storage capacity. The first and second line memories LM1, L
On the read output terminal side of M2, a read memory selection circuit (hereinafter simply referred to as a multiplexer) MPX2 is provided. The multiplexer MPX2 performs a switching operation complementarily to the multiplexer MPX1 for writing. For example, the multiplexer MPX1 for writing makes one of the line memories LM1 according to the control signal R / W.
When transmitting the parallel display data to the line memory LM2 (or LM2), the read multiplexer MPX2 selects and outputs the read data of the other line memory LM2 (or LM1). The write control circuit WC receives the dot clock signal CLK, the display timing signal DST and the horizontal synchronizing signal HSYN, and generates the control signal R / W and the write address signal WA. Also, the read control circuit R
C receives the horizontal synchronizing signal HSYN and generates a read address signal RA and a 2-bit color selection signal CS. For example, by the write control circuit WC,
If the control signal R / W is at a high level, the multiplexer MP
X1 selects the first line memory LM1. The read / write control circuit RWC responds to the control signal R / W,
The write address signal WA generated by the write control circuit WC is output as the address signal A1 of the line memory LM1. Thus, color display data R, G, and B composed of three primary colors serially input for one line.
Is written to the line memory LM1. On the other hand, the read address signal RA generated by the read control circuit RC is transmitted by the read / write control circuit RWC as the address signal A2 of the second line memory LM2. As a result, the line memory LM2 performs a read operation, and supplies the stored color display data to the color selection circuit CSEL through the multiplexer MPX2. As described above, since the three primary color data R, G, and B are output in parallel in units of 4 bits from the line memory LM2, the color selection circuit CSEL outputs the three primary color data R, G, and B in response to the color selection signal CS. B
Output in chronological order. In this embodiment, in order to increase the frame frequency equivalently, each color data which is output in a serial manner by being divided into colors is divided by a divided data control circuit DDC.
Although there is no particular limitation, the image is divided into two for each color. Correspondingly, X drive circuits XDVL, XDVR
Is also divided into two. That is, the color liquid crystal display panel L
The display screen of the CD is apparently divided into two parts, left (L) and right (R), and the X drive circuits XDVL and XDVR are provided correspondingly to the two. In this configuration, the X driving circuits XDVL and XDVR are provided with a color liquid crystal display panel of 640.
Despite having one signal line electrode, half of it has 320
It has only display data driving capability corresponding to the signal electrodes. Since a configuration is adopted in which two display data are simultaneously read, the transfer speed of the display data can be doubled as viewed from the liquid crystal display panel LCD.
In other words, the time required to capture display data for one line can be reduced by half. The timing control circuit TC receives the display timing signal DST and the vertical synchronizing signal VSYN, and receives a data shift clock signal DS necessary for the operation of the X drive circuits XDVL and XDVR and the Y drive circuit YDV.
C, forming a line clock signal LCK. Further, the timing control circuit TC generates a head clock signal LFS supplied to the Y drive circuit YDV. Y drive circuit YDV
Captures the high level of the clock signal LFS at the falling edge of the line clock signal LCK and sets the scanning line Y1 to the high level. Then, in synchronization with the falling edge of the line clock signal CLK, the high level is shifted in correspondence with Y2, Y3,... FIG. 2 is a timing chart for explaining the operation of the color display device of this embodiment. In the color display device of this embodiment, one frame period is composed of 204 horizontal periods, and the vertical synchronizing signal VSYN is generated almost in synchronization with the first horizontal period. The period from the 203rd horizontal synchronization of the previous frame to the 2nd horizontal period of the frame is defined as a vertical retrace period. Therefore, the display operation in one frame is performed in 200 horizontal periods corresponding to 1 to 200 lines from the third horizontal period to the 202nd horizontal period. One horizontal period includes a horizontal synchronizing signal HSYN.
As shown in the figure in an enlarged manner,
While the display timing signal DST is at the high level, the color display data consisting of R, G, and B is regarded as valid display data, and the remaining data is regarded as horizontal blanking data (black display). As described above, the effective display data includes red (R), green (G), and blue (B) each composed of 640 dots (bits). FIG. 3 shows the color liquid crystal display panel LC.
D and its X drive circuits XDVL, XDVR and Y drive circuit YDV are shown. As described above, the color liquid crystal display panel LCD
Has a horizontal stripe-shaped color filter, and one line is composed of three pixel columns of R, G, and B. As described above, the Y drive circuit YDV
It has scanning lines 1 to Y600 and captures a line head clock LFS generated at the beginning of a frame,
In synchronization with the line clock signal LCK, a Y selection signal is formed by shifting it. Therefore, one horizontal display period is temporally divided into three as described later, and X
From the driving circuits XDVL and XDVR, 640-dot R1
When data is transmitted, the scanning line Y1 is selected, when G1 data is transmitted, the scanning line Y2 is selected, and when B1 data is transmitted, the scanning line Y3 is selected. Thus, the color image data of the first line 1 is written to each pixel in one horizontal period. In the next horizontal period, X driving circuits XDVL and XDVL
When R2 data of 640 dots is transmitted from VR, the scanning line Y4 is selected, when G2 data is transmitted, the scanning line Y5 is selected, and when B2 data is transmitted, the scanning line Y6 is switched. It is selected. Thus, the color image data of the next line 2 is written to each pixel. Hereinafter, similarly, the color pixel data R200, G200, and B200 up to the last line 200 are written to each pixel. Thus, writing of one frame is performed. The same display data R1, G1, B1 to R200, G200,
The polarity of B200 is inverted and output from the X drive circuits XDVL and XDVR, and the same scanning line selection operation as described above is performed in synchronism therewith. Therefore, the liquid crystal display panel LCD of the active matrix configuration needs to spend two frames to display one screen. FIG. 4 shows the line memory LM1 or L
A timing chart for explaining an example of the color display data written in M2 is shown. The serial / parallel conversion circuit SPC converts the serially input color display data of each color (R, G, and B) into parallel in 4-bit units to form write parallel data. That is, signals R0 to R159, G0 to G corresponding to each color in units of 4 bits.
159 and B0 to B159 are written to the line memory LM1 or LM2. As a result, color display data of 160 × 4 = 640 bits is written for each color as a whole. FIG. 5 shows the line memories LM1 and LM
2 is shown. In this embodiment, since the write parallel data is input in units of 4.times.3 bits as described above, the line memories LM1 and LM2 store addresses 0 to 1 respectively.
It is made to have 59. In this embodiment, in order to increase the frame frequency as described above, the X drive circuit is divided into two such as XDVL and XDVR as described above. In order to cope with this, signals 0 to R79, G0 to G79 and B0 to B79 to be corresponded to the X drive circuit XDVL are set to the even addresses 0, 2,.
Signals R80 to R159, G80 to correspond to VR
G159 and B80 to B159 are odd addresses 1, 3
.. 159 are respectively assigned. As a result, in the line memories LM1 and LM2, odd-numbered addresses store left-side data, even-numbered addresses store right-side data, and one address stores 4 × 3 = 12-bit color display data. FIG. 6 shows the line memory LM1 or L
A timing chart for explaining the read operation from M2 is shown. The address signal RA formed by the read control circuit RC is supplied to the line memory LM1 (or LM) by the switching operation of the multiplexer MPX1 according to the level of the control signal R / W and the read / write control circuit RWC.
While the above-described writing is being performed on 2), it is transmitted to the other line memory LM2 (or LM1) by the read / write control circuit RWC, and the read signal is output by switching the multiplexer MPX2. At this time, the read control circuit RC generates the address signal RA so that the selected line memory LM2 (or LM1) is read three times in one horizontal period. Therefore, the parallel data read through the multiplexer MPX2 is R0-R159, G0-G159.
And B0 to B159 are repeatedly output three times. A color selection signal CS consisting of two bits is formed according to the number of times of reading by the read control circuit RC. For example, in the first reading, the color selection signal CS is set to 0 (00), and the color selection circuit CSEL is
Of the color display data composed of the three primary colors as described above, R
0 to R159 are output. In the second read, the color selection signal CS is set to 1 (01), and the color selection circuit C
The SEL outputs G0 to G159 among the color display data including the three primary colors as described above. In the third reading, the color selection signal CS is set to 2 (10), and the color selection circuit CSEL outputs B0 to B159 among the color display data including the three primary colors as described above. The color display data R0 to R159, G0 to G159 and B0 to B1 are divided into odd addresses and even addresses of the line memories LM1 and LM2.
59 are stored, and if the read address signal RA is generated in order from 0 to 159, R
Left and right alternate color display data such as 0 and R80 and R1 and R81 are output. Divided data control circuit DDC
Temporarily latches the left and right color display data corresponding to the X drive circuits XDVL and XDVR as described above, and supplies the data to the X drive circuits XDVL and XDVR. For example, if the serial transfer speed of the X drive circuits XDVL and XDVR is 6 MHz as described above, the line memory L at twice the speed is used.
Reading of M1 and LM2 is performed. The parallel color data divided as described above is used to synchronize the color display data R0 to R79 and R80 to R159 with the data shift clock DSC in units of 4 bits in the X drive circuits XDVL and XDVR, respectively. Then, when the capture is completed, the data is divided into color display data of X1 to X640 and output in parallel in synchronization with the line clock LCK. G
0 to G79, G80 to G159 and G0 to G79
Up to and including the color display data of G80 to G159 and the output thereof are also performed in the same manner as described above. However, since the Y drive circuit YDV switches the selection line from Y1 to Y2 and Y3 in synchronization with the line clock CLK, the display operation corresponding to each color line is performed. In this embodiment, by using two line memories as described above, while the display data is being written to one of the line memories, the other line memory which has already been written can be read. Since the display operation is performed by performing the operation, only a storage circuit having a storage capacity of two lines is provided. Therefore, as compared with a conventional device using a frame memory, a color display device having a large screen and high image quality can be configured with a small number of storage circuits. That is, if the number of display lines on one screen is N, the storage capacity can be greatly reduced to 2 / N as compared with the related art. Further, since the X drive circuit is divided into two, the time required for the transfer operation is halved. In other words, from the viewpoint of the entire display device, this is equivalent to doubling the transfer speed of the X drive circuit. Therefore, as apparent from the above description, the frame frequency is 125
Hz and higher frequencies can be achieved. As a result, even if the same display data is written in positive and negative polarities for AC driving of the liquid crystal display panel LCD, a frame frequency of 62.5 Hz and high image quality with less flicker than a home television receiver can be obtained. be able to. The operation and effect obtained from the above embodiment are as follows. That is, (1) First and second line memories for storing color display data corresponding to one line of a color display panel are provided, and the first and second line memories are alternately written and read controlled. At the same time, the color display data read from the first or second line memory is divided and supplied in parallel corresponding to a plurality of divided X drive circuits. In this configuration, since only two lines of data are stored as a storage circuit for storing color display data, an effect is obtained that the storage capacity of the storage circuit required for the display operation can be reduced. (2) According to the above (1), the liquid crystal display controller can be constituted by a one-chip semiconductor integrated circuit, and the effect of greatly simplifying the system can be obtained. (3) Since the X drive circuit can be divided and the color display data stored in the line memory can be input in parallel corresponding thereto, the transfer speed in the X drive circuit can be equivalently increased, so that the frame frequency And a high-quality display screen without flicker can be obtained. (4) In a liquid crystal display panel having an active matrix configuration, a configuration is adopted in which pixels are equivalently regarded as capacitors and display data is held. Therefore, the leakage current increases as the temperature rises. Therefore, by increasing the frame frequency as described above, the number of times of writing per unit time can be increased, and an effect that a display operation up to a high temperature can be realized is obtained. (5) By dividing the X drive circuit, it is possible to drive a liquid crystal display panel having a larger screen and a higher density while using an existing drive circuit. Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say. For example,
The X driving circuit may be divided into three or more N circuits. In this case, the substantial transfer speed can be increased N times. For example, in FIG. 1, the X drive circuit may be divided into four parts, and the parallel data formed by the serial / parallel conversion circuit SPC may be changed from four bits to two bits. In this configuration, the frame frequency is the same, but the serial shift register constituting the X drive circuit has a 2-bit configuration, and the circuit can be simplified. Further, in the X drive circuit, the divided X drive circuits may be configured in one semiconductor integrated circuit. That is, a plurality of X drive circuits may be provided in one semiconductor integrated circuit. By doing so, the number of circuit components constituting the color display device can be reduced. The specific configuration of the memory control circuit for alternately performing the write / read operation of the two line memories can employ various embodiments. This can be applied to those using various color display panels having a matrix configuration, in addition to those using a color liquid crystal display panel. The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows. That is, first and second line memories for storing color display data corresponding to one line of a color display panel are provided, and the first and second line memories are alternately controlled for writing and reading. The color display data read from the first or second line memory is divided and supplied in parallel corresponding to a plurality of divided X drive circuits. In this configuration, since only two lines of data are stored as the storage circuit for storing the color display data, the storage capacity of the storage circuit required for the display operation can be reduced. Also,
Since the X drive circuit can be divided and the color display data stored in the line memory can be input in parallel corresponding thereto, the transfer speed in the X drive circuit can be equivalently increased, so that the frame frequency can be increased and the flicker can be reduced. It is possible to obtain a high quality display screen without any.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of a color display device according to the present invention. FIG. 2 is a timing chart for explaining a display operation. FIG. 3 is a configuration diagram showing one embodiment of a color liquid crystal display panel. FIG. 4 is a timing chart for explaining write parallel data to a line memory; FIG. 5 is a memory map diagram showing one embodiment of a line memory. FIG. 6 is a timing chart for explaining parallel data read from a line memory. [Description of Signs] SPC: serial / parallel conversion circuit, MPX1: multiplexer (write memory selection circuit), MPX2: multiplexer (read memory selection circuit), LM1, LM2: line memory, RWC: read / write control circuit, TC ... Timing control circuit, LCD: color liquid crystal display panel, WC: write control circuit, RC: read control circuit, CSEL: color selection circuit, DDC: divided data control circuit, XDVL, XDVR: X drive circuit, YDV: Y drive circuit .

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Kazuhiro Fujisawa               292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa               Hitachi, Ltd. Micro Elect               Inside Ronix Equipment Development Laboratory (72) Inventor Kaoru Hasegawa               3300 Hayano Mobara-shi, Chiba Sun               Inside the Mobara factory (72) Inventor Shinzo Matsumoto               3300 Hayano Mobara-shi, Chiba Sun               Inside the Mobara factory (72) Inventor Mitsuhisa Fujita               3300 Hayano Mobara-shi, Chiba Sun               Inside the Mobara factory                (56) References JP-A-62-63993 (JP, A)                 JP-A-59-61883 (JP, A)                 JP-A-59-54394 (JP, A)                 JP-A-58-75195 (JP, A)

Claims (1)

(57) [Claims] 1. A liquid crystal display panel having M dot signal lines, and a display area of M dots of the liquid crystal display panel is configured.
N data driving circuits for supplying an image signal to each of the signal lines of N (N is a natural number of 2 or more) partial areas each having a continuous display dot, and display data to be displayed on the liquid crystal display panel A memory for storing at least M dots, and the display data input as continuous display data is written in the storage circuit, and the M stored in the storage circuit is stored in the storage circuit.
A memory control circuit for reading out, from the storage circuit, N sets of display data of a predetermined unit to be displayed in each of the N partial regions, in the display data for the dots, in a predetermined order; A liquid crystal display device comprising: a divided data control circuit that sequentially holds the read N sets of display data and outputs the read data to the N data drive circuits in parallel. 2. The memory control circuit includes two memory circuits, the memory control circuit includes a write switch circuit that supplies write data to one of the two memory circuits, and a read data that is read from one of the two memory circuits. A read-out switching circuit for selecting, during the operation of writing the display data to one of the two storage circuits, the write-in switching circuit and the read-out switching circuit so that the display data reading operation is performed from the other storage circuit. 2. The liquid crystal display device according to claim 1, wherein 3. The liquid crystal according to claim 1, wherein the storage circuit stores, at the same address, each of a plurality of color display data each supplied in a plurality of bits. Display device. 4. The storage circuit outputs the color display data of the plurality of colors stored at the same address simultaneously at the same address, and the memory control circuit reads the color display data of the plurality of colors simultaneously read from the storage circuit. 4. The liquid crystal display device according to claim 3, further comprising a color selection circuit that selects specific color display data from the display data and supplies the selected data to the divided data control circuit. 5. The liquid crystal display device according to claim 4, wherein the liquid crystal display panel is an active matrix liquid crystal display panel provided with color filters in a horizontal stripe shape. 6. The input display data includes continuous M dots of display data and non-display data added before and after the display data, and the memory control circuit controls the continuous display data included in the input display data. 2. The storage device according to claim 1, wherein only the display data for the continuous M dots is written in the storage means in accordance with a display timing signal for distinguishing between display data for the M dots and non-display data. 5
Item 6. The liquid crystal display device according to any one of items 1.