JP2001092426A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a display, which has no disinclination and no flickering and has a good contrast and bright, for a display device in which a direct view type pixel pitch is set to <=20 μm. SOLUTION: The device is driven by a frame reverse driving method, the vertical frame frequency is >=120 Mz and each pixel is set to correspond to one of R, G and B color filters provided on a TFT substrate side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method suitable for a display device in which pixels are arranged in a matrix using a display medium such as a liquid crystal. Further, the present invention relates to a display device which performs display using the driving method. In particular, it relates to a direct-view type active matrix type liquid crystal panel (liquid crystal panel).

[0002]

2. Description of the Related Art In recent years, a technology for fabricating a semiconductor device in which a semiconductor thin film is formed on an insulating substrate, for example, a thin film transistor (TFT) has been rapidly developed. The reason is that the demand for liquid crystal panels (typically, active matrix type liquid crystal panels) has increased.

An active matrix type liquid crystal panel displays an image by controlling the charge flowing into and out of tens to millions of pixels arranged in a matrix by switching elements of the pixels.

[0004] A pixel in this specification refers to a switching element, a pixel electrode connected to the switching element, a liquid crystal, and a counter electrode provided to face the pixel electrode via the liquid crystal. Refers mainly to elements that are configured.

A typical example of a display operation of an active matrix type liquid crystal panel will be briefly described below with reference to FIG.

[0006] The source signal line drive circuit 103 and the source signal lines S1 to S6 are connected. Further, the gate signal line drive circuit 104 and the gate signal lines G1 to G5 are connected. Then, the source signal lines S1 to S6 and the gate signal line G
A plurality of pixels 106 are provided in a portion surrounded by 1 to G5. The pixel 106 includes a switching element 101 and a pixel electrode 102. Note that the number of source signal lines and gate signal lines is not limited to this value (FIG. 19).
(A)). Note that FIG. 19B is a diagram (display pattern) illustrating positions of a plurality of pixels 106 included in the pixel portion 105.

A video signal is applied to the source signal line S1 according to a signal from a shift register circuit or the like (not shown) in the source signal line driving circuit 103. Further, a selection signal is applied from the gate signal line driving circuit 104 to the gate signal line G1, and the switching elements of the pixels (1, 1) where the gate signal line G1 intersects with the source signal line S1 are turned on. . Then, the video signal of the source signal line S1 is applied to the pixel electrode of the pixel (1, 1). The liquid crystal is driven by the potential of the applied video signal, the amount of transmitted light is controlled, and a part of an image (an image corresponding to the pixel (1, 1)) is displayed on the pixel (1, 1).

Next, while the state in which an image is displayed on the pixel (1, 1) is held by a holding capacitor (not shown) or the like, at the next moment, the shift register circuit 103 in the source signal line driving circuit 103 (Not shown), a video signal is input to the source signal line S2. The selection signal is still applied to the gate signal line G1 from the gate signal line driving circuit 104, and the switching elements of the pixels (1, 2) where the gate signal line G1 intersects with the source signal line S2 are turned on. To Then, the potential of the video signal of the source signal line S2 is applied to the pixel electrodes of the pixels (1, 2). The liquid crystal is driven by the potential of the applied video signal to control the amount of transmitted light, and the pixel (1, 1) is controlled similarly to the pixel (1, 1).
In 2), a part of the image (the image corresponding to the pixels (1, 2)) is displayed.

Such display operations are sequentially performed, and the pixels (1, 1) (1, 2) connected to the gate signal line G1 are displayed.
(1, 3) (1, 4) (1, 5) (1, 6) Part of the image is displayed one after another. During this time, the selection signal is continuously applied to the gate signal line G1.

When the video signal is applied to all the pixels connected to the gate signal line G1, no selection signal is applied to the gate signal line G1, and subsequently, the selection signal is applied only to the gate signal line G2. Is done. Then, the pixels (2, 1) (2, 2) connected to the gate signal line G2
(2, 3) (2, 4) (2, 5) (2, 6) Display a part of the image one after another. During this time, the selection signal is continuously applied to the gate signal line G2. By performing such a display operation on all the gate signal lines, one screen (frame) is displayed in the display area. This period is called one frame period. (FIG. 19B)

Finally, the pixels (4,
Until a part of the image is displayed in 6), all the other pixels hold the state in which the image is displayed by a storage capacitor (not shown) or the like.

An image is displayed on the pixel portion 105 by sequentially repeating these display operations.

[0013]

Generally, in a liquid crystal panel using a TFT or the like as a switching element, in order to prevent deterioration of the liquid crystal material, the polarity of the potential of a signal applied to each pixel is inverted with respect to a common potential (AC). Drive).

One of the AC drive methods is a source line inversion drive. FIG. 20A shows a polarity pattern of a pixel in source line inversion driving. Note that the polarity pattern shown in FIG. 20 corresponds to the display pattern shown in FIG.

In the drawings showing the polarity patterns in this specification (FIGS. 20, 22, and 23), when the potential of the video signal applied to the pixel is positive with respect to the common potential, " It is shown by "+", and when negative, it is shown by "-".

In addition, the scanning method is performed twice (2 times) by skipping the gate signal lines of one screen (one frame) one by one.
There are two types of scanning, namely, interlaced scanning, which scans each field separately, and non-interlaced scanning, which sequentially scans without skipping the gate signal lines. Here, an example using non-interlaced scanning will be mainly described.

As shown in FIG. 20 (A), the feature of the source line inversion drive is that, during an arbitrary one frame period,
The same polarity video signal is applied to all pixels connected to the same source signal line, and the opposite polarity video signal is applied between pixels connected to adjacent source signal lines. is there. Then, in the next one frame period, a video signal having a polarity opposite to the polarity pattern displayed in the immediately preceding one frame period is applied to each pixel to display the polarity pattern.

As another AC driving method, there is a gate line inversion driving method. FIG. 20B shows a polarity pattern of the gate line inversion driving.

As shown in FIG. 20B, the video signal of the same polarity is applied to all the pixels connected to the same gate signal line during an arbitrary one frame period.
This means that video signals of opposite polarities are applied between pixels connected to adjacent gate signal lines. Then, in the next one frame period, a video signal having a polarity opposite to the polarity pattern displayed in the immediately preceding one frame period is applied to each pixel to display the polarity pattern.

That is, similar to the above-described conventional source line inversion driving method, the driving method is such that two types of polarity patterns (a polarity pattern and a polarity pattern) are repeatedly displayed.

In recent years, liquid crystal panels have been required to be thinner and lighter, and also to have higher definition, higher image quality and higher brightness.

In order to reduce the thickness and weight of the liquid crystal panel, it is necessary to reduce the size of the liquid crystal panel substrate. In order to reduce the size of the substrate and not to degrade the image quality, it is necessary to shorten the pixel pitch and thereby reduce the area of the pixel portion.

FIG. 21 is an enlarged view of a pixel of the liquid crystal panel. A pixel TFT (switching element) 15 having a source signal line 12a, a gate signal line 12b, a semiconductor layer 13, and a gate electrode 14 which is a part of the gate signal line 12b.
And the pixel electrode 16 are provided as shown in FIG. The source signal line 12a and the gate signal line 12
A black matrix 17 is provided on the pixel b and the pixel TFT 15 so as to cover a region that does not need to transmit visible light. A black matrix (BM) refers to a light-blocking film provided above a wiring (a source signal line 12a and a gate signal line 12b) that does not need to transmit visible light or a pixel TFT 15 or the like.

The pixel pitch L indicates the shorter of the distance between the source signal lines 12a facing each other across the pixel 11 and the distance between the gate signal lines 12b facing each other. When the distance between both signal lines is the same, the distance is defined as the pixel pitch L.

As the pixel pitch becomes shorter, the distance between the pixel electrodes 16 of adjacent pixels becomes shorter. Therefore, when the source line inversion drive and the gate line inversion drive are performed, stripes called disclination lines are generated between adjacent pixels to which the opposite polarity is applied, and the brightness of the entire display screen tends to be reduced. .

In this specification, the disorder of the alignment state of the liquid crystal (disk) is caused by a potential difference between a pixel to which a video signal of a positive polarity is applied and a pixel to which a video signal of a negative polarity is applied. (A loss of light in the case of normally white and a light leak in the case of normally black) due to the above-mentioned disclination line.

The potential difference between adjacent pixels is shown in FIG.
This is caused by the electric flux lines shown in FIG. FIG. 22A shows that an effective electric field (positive or negative) applied to the pixel electrodes A and B of two adjacent pixels in a direction perpendicular to the paper surface is positive between the two pixel electrodes A and B. FIG. 22B shows a top view of a state diagram of the generated lines of electric force, and FIG. 22B shows a cross-sectional view thereof. However, for convenience, FIG. 22A shows only lines of electric force generated between the pixel electrodes A and B generated in the horizontal direction, and FIG. 22B shows liquid crystal molecules whose alignment is controlled in the vertical direction. FIG. 2 shows a state diagram of electric lines of force immediately before responding to the application of.

A disclination pattern corresponding to FIG. 20A is shown in FIG. FIG.
In (C), although the disclination line is formed at a fixed position and the polarity of the video signal applied to the pixel is different, the disclination pattern and the disclination pattern are substantially the same. is there. FIG.
The disclination line as shown in FIG. 2C is also seen in the gate line inversion drive. In the case of gate line inversion drive, the disclination line
It appears between the pixels in parallel with the direction of the gate signal line.

In addition, although not shown, as another AC driving method, a method of inverting the polarity of a video signal applied to a pixel between all adjacent pixels (dot inversion driving) has been proposed. In the dot inversion drive, since the polarity is different from that of an adjacent pixel, the influence of a potential difference generated between the adjacent pixels is large. In particular, when the pixel pitch is short, disclination greatly affects display.

The shorter the pixel pitch, the shorter the distance between adjacent pixel electrodes. Disclination was particularly remarkable when it was 20 μm or less.

Therefore, instead of the source line inversion drive, the gate line inversion drive, and the dot inversion drive, discrimination is performed by using frame inversion drive for inverting the polarity of the video signal applied to all the pixels every one frame period. It is conceivable to suppress the nation.

FIG. 23 shows a polarity pattern of each pixel in the frame inversion driving. The feature of the frame inversion drive is that a video signal of the same polarity is applied to all the pixels within an arbitrary one frame period (polarity pattern), and a video signal applied to all the pixels in the next one frame period (Polarity pattern) to be displayed with the polarity inverted.
That is, when focusing only on the polar pattern, the driving method is such that two types of polar patterns (a polar pattern and a polar pattern) are repeatedly displayed. Therefore, during the same frame period, the polarities of the video signals applied to the adjacent pixels are the same, and the occurrence of disclination is suppressed.

However, the problem of the frame inversion drive is that the brightness of the screen is slightly different between the display when the polarity of the video signal is positive and the display when the polarity is negative, so that it is visually recognized as a flicker by the observer. It is to be. The cause of the flicker will be described in detail below.

FIG. 24 shows the video signal applied to the source signal lines S1 to Sn, the selection signal applied to the gate signal line G1, and the potential of the pixel electrode (1, 1) of the pixel (1, 1). The timing chart is shown. A period in which the selection signal is applied to the gate signal line G1 is defined as one line period, and a period from when the selection signal is applied to all the gate signal lines to display one image is defined as one frame period.

When a video signal and a selection signal are applied to the source signal line S1 and the gate signal line G1, respectively, a pixel (1,...) Provided at the intersection of the source signal line S1 and the gate signal line G1 In 1), the potential of the video signal having a positive polarity selected by the selection signal is applied. Ideally, this potential is held for one frame period by a storage capacitor or the like.

However, in practice, when one line period ends, the selection signal is not applied to the gate signal line G1 and the potential of the gate signal line G1 changes, and at the same time, the potential of the pixel electrode also changes. The gate signal line is connected to a gate electrode of a pixel TFT which is a switching element of the pixel. The source signal line is connected to the source or drain region of the pixel TFT, and the pixel electrode is connected to the source or drain region that is not connected to the source signal line.
A small capacitance is formed between the gate electrode and the pixel electrode. When the potential of the gate signal line G1 changes, the potential of the pixel electrode also changes by ΔV accordingly. In this case, the potential of the pixel electrode changes in the negative direction.
In the timing chart shown in FIG. 24, the actual potential of the pixel electrode is indicated by a solid line, and the potential of the pixel electrode when there is no capacitance formed between the gate electrode and the pixel electrode is indicated by a dotted line.

Next, in the second frame period, a video signal having a negative polarity opposite to that of the first frame period is applied to the pixel (1, 1).
Is applied to the pixel electrode of 1 of the second frame period
When the line period ends, the selection signal is not applied to the gate signal line G1, and the potential of the gate signal line G1 changes. The potential of the pixel electrode also changes by ΔV in the negative direction accordingly.

That is, the potential difference V1 between the pixel electrode potential and the common potential after one line period in the first frame period is defined as the potential difference V2 between the pixel electrode and the common potential after the one line period in the second frame period is completed. Then, there is a difference of 2 × ΔV between the potential difference V1 and the potential difference V2. Therefore, the brightness of the screen differs between the first frame period and the second frame period.

Similarly, in the case of the source line inversion drive, the gate line inversion drive, and the dot inversion drive, the brightness of the pixel to which the video signal of the positive polarity is applied and the brightness of the pixel to which the video signal of the negative polarity is applied are different. However, since the pixels having different brightnesses are adjacent to each other, it is difficult for the observer to visually recognize the pixels. However, in the case of the frame inversion drive, the polarities of adjacent pixels are all the same, and the polarity is inverted during one frame period which is a frequency range (about 30 Hz) visible to human eyes. The display is slightly different from the display when the polarity of the video signal is negative, and it is visually recognized by the observer as a flicker. In particular,
Significant flicker was confirmed in the halftone display.

As described above, in the source line inversion driving and the gate line inversion driving, FIGS.
As shown in an example in (B), a polarity pattern and a polarity pattern are repeatedly displayed, and a disclination line is continuously formed at a fixed position between adjacent pixels having different polarities, so that the brightness of the screen is reduced. Had been done. In addition, the same applies to dot inversion driving.

In the frame inversion drive, disclination does not occur, but flicker occurs.

Accordingly, the present invention is intended to solve such problems.

That is, an object of the present invention is to provide a liquid crystal panel having a short pixel pitch and capable of obtaining a bright display without flicker and a driving method thereof.

[0044]

According to the present invention, there are provided a plurality of gate signal lines, a plurality of source signal lines, and a plurality of pixel electrodes provided at each intersection of the gate signal lines and the source signal lines. And a second substrate having a color filter including three colors, wherein the plurality of pixel electrodes pass through the plurality of source signal lines during a first frame period. The first video signal having the same polarity is applied, and the first video signal is applied to the plurality of pixel electrodes through the plurality of source signal lines in a second frame period following the first frame period. A display device is provided, wherein a second video signal having a polarity opposite to that of the signal is applied.

According to the present invention, a plurality of gate signal lines,
A first substrate having a plurality of source signal lines, a plurality of pixel electrodes provided at intersections of the gate signal lines and the source signal lines, and a second substrate having a color filter including three colors. A video signal having the same polarity is applied to the plurality of pixel electrodes through the plurality of source signal lines, and the polarity of the video signal changes every frame period. A display device is provided.

According to the present invention, a plurality of gate signal lines,
A first substrate having a plurality of source signal lines, a plurality of switching elements and a plurality of pixel electrodes provided at respective intersections of the gate signal lines and the source signal lines, and a color filter including three colors And a second substrate having: a video signal of the same polarity is applied to the plurality of switching elements through the plurality of source signal lines, and through the plurality of gate signal lines,
A selection signal for selecting the video signal is applied to the plurality of switching elements, and a video signal selected by the selection signal is applied to the plurality of pixel electrodes through the plurality of switching elements, A display device is provided, wherein the polarity of the video signal changes every frame period.

The interval between the plurality of gate signal lines or the plurality of source signal lines may be not more than 20 μm.

[0048] The lengths of the first frame period and the second frame period may be 8.3 msec or less.

The length of the one frame period is 8.3 ms.
c or less.

Each of the plurality of switching elements has a gate electrode, a semiconductor layer having a source region, a drain region, and a channel formation region, and an insulating film provided between the gate electrode and the semiconductor layer. The gate signal line may be connected to the gate electrode, and the source signal line may be connected to the source region or the drain region.

A liquid crystal may be provided between the first substrate and the second substrate.

The plurality of pixel electrodes may correspond to one of three colors included in the color filter.

A goggle-type display having one display device is provided.

A goggle type display having two display devices is provided.

A mobile computer having one display device is provided.

A notebook personal computer having one display device is provided.

A video camera having one display device is provided.

A DVD player having one display device is provided.

A game machine having one display device is provided.

[0060]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of the present invention will be described below in comparison with a conventional configuration. Although an example using non-interlaced scanning will be described here, it goes without saying that the present invention is not limited to non-interlaced scanning but can be applied to other scanning methods such as interless scanning. .

FIG. 2 shows the structure of the active matrix type liquid crystal panel of the present invention. Source signal line driving circuit 1801
The gate signal line driving circuit 1802 is generally called a driving circuit. In recent years, this driver circuit may be formed over the same substrate as a pixel portion 1808 in which pixels are provided in a matrix.

In the pixel portion 1808, the source signal line 1803 connected to the source signal line driving circuit 1801
(S1 to Sn) intersect with a gate signal line 1804 (G1 to Gn) connected to the gate signal line driving circuit 1802. The source signal line 1803 and the gate signal line 1
A thin film transistor (pixel TFT) 1805 of a pixel, a liquid crystal cell 1806 in which liquid crystal is interposed between a counter electrode and a pixel electrode, and a storage capacitor 1807 are provided in a region surrounded by 804.

A video signal sampled by the timing signal output from the source signal line driving circuit 1801 is applied to the source signal line 1803.

The pixel TFT 1805 turns on the pixel TFT 1805 by a selection signal input from the gate signal line driving circuit 1802 via the gate signal line 1804. When the pixel TFT 1805 is turned on, a video signal applied to the source signal line 1803 is applied to the liquid crystal cell 1806.
Are applied to the pixel electrodes.

In the liquid crystal panel shown in FIG. 2, video signals applied to source signal lines S1, S2,.
FIG. 1 shows a timing chart of the selection signal applied to the gate signal line G1 and the potential of the pixel electrode of the pixel (1, 1) at the intersection of the source signal line S1 and the gate signal line G1. . As a conventional example, the potential of the pixel electrode of the pixel (1, 1) of the liquid crystal panel driven at a frame frequency of 60 Hz is also shown. A period in which the selection signal is applied to the gate signal line G1 is defined as one line period, and a period until the selection signal is completely applied to all the gate signal lines is defined as one frame period.

In the present invention, one frame period is 8.3.
msec or less. That is, the frame frequency is 120H
It is desirably equal to or greater than z. In the present embodiment, the frame frequency is set to 120 Hz.

When a video signal and a selection signal are applied to the source signal line S1 and the gate signal line G1, respectively, a pixel (1,...) Provided at the intersection of the source signal line S1 and the gate signal line G1 In 1), the potential of the video signal having a positive polarity selected by the selection signal is applied. Ideally, this potential is held for one frame period by a holding capacitor or the like.

However, actually, when one line period ends, the selection signal is not applied to the gate signal line G1, and the potential of the pixel electrode changes at the same time as the potential of the gate signal line G1 changes. The gate signal line is connected to a gate electrode of a pixel TFT which is a switching element of the pixel. The source signal line is connected to the source or drain region of the pixel TFT, and the pixel electrode is connected to the source or drain region that is not connected to the source signal line. A small capacitance is formed between the gate electrode and the pixel electrode. When the potential of the gate signal line G1 changes, the potential of the pixel electrode also changes by ΔV accordingly.
In this case, the potential of the pixel electrode changes in the negative direction. In the timing chart shown in FIG. 1, the actual potential of the pixel electrode is shown by a solid line, and the potential of the pixel electrode when there is no capacitance formed between the gate electrode and the pixel electrode is shown by a dotted line.

Next, in the second frame period, a video signal having a negative polarity opposite to that of the first frame period is applied to the pixel (1, 1).
Is applied to the pixel electrode of 1 of the second frame period
When the line period ends, the selection signal is not applied to the gate signal line G1, and the potential of the gate signal line G1 changes. The potential of the pixel electrode also changes by ΔV in the negative direction accordingly.

That is, the potential difference V1 between the pixel electrode potential and the common potential after one line period in the first frame period is defined as the potential difference V2 between the pixel electrode and the common potential after the one line period in the second frame period is completed. Then, there is a difference of 2 × ΔV between the potential difference V1 and the potential difference V2. Therefore, the first
The screen brightness differs between the frame period and the second frame period.

However, when the frame frequency is set to 120 Hz or more, the difference in screen brightness between the first frame period and the second frame period cannot be visually recognized by human eyes. Therefore, since the polarity is inverted every frame period, even if the display when the polarity of the video signal is positive is slightly different from the display when the polarity of the video signal is negative, the display is visually recognized as a flicker by the observer. Disappears.

As described above, in the present invention, the direct-view type liquid crystal panel is driven by using the frame inversion driving method and the frame frequency is set to 120 Hz or more faster than in the past, so that the direct-view type pixel pitch is 20 μm or less. In the short display device, no disclination or flicker was observed, and a bright display with good contrast could be obtained.

[0073]

An embodiment of the present invention will be described with reference to FIGS.

(Embodiment 1) The arrangement of pixels and the arrangement of color filters according to the present invention will be described with reference to FIG. In the present invention, the color filter is provided on the TFT substrate side. FIG. 3A illustrates a case where the pixel arrangement of the liquid crystal panel is a delta arrangement. Each pixel is R (red),
It corresponds to each of the three colors G (green) and B (blue).
One dot is composed of three adjacent pixels corresponding to R (red), G (green), and B (blue), respectively.

FIG. 3B illustrates a case where the pixel arrangement of the liquid crystal panel is a stripe arrangement. Each pixel is R
(Red), G (green), and B (blue). Adjacent R (red), G (green), B (blue)
One pixel is constituted by three pixels corresponding to each of.

Embodiment 2 In this embodiment, an example of a driving circuit used in the present invention will be described.

FIG. 4 shows one example of a liquid crystal panel driving circuit according to the present invention.
One example of a source signal line driving circuit is shown. An input signal input from outside the source signal line driving circuit, in this case, a signal (S-CLb) inverted with respect to a common potential of the source clock signal (S-CL) and the source clock signal (S-CL). Is input to the source signal line driving circuit.

The source clock signal (S-CL) input to the source signal line driver circuit is input to the source shift register circuit 401. The input source clock signal (S-CL) and the source start pulse signal (S-CL) input to the source shift register circuit at the same time.
SP), the source shift register circuit 401 operates to sequentially generate timing signals for sampling the video signal.

The timing signal is input to the source level shift circuit 402 and its voltage amplitude level can be raised. Here, in this specification, the voltage amplitude level means the absolute value of the difference (potential difference) between the highest potential and the lowest potential of a signal, and the higher the voltage amplitude level (increased), the larger the potential difference. This means that a lower voltage amplitude level means a smaller potential difference.

The timing signal whose voltage amplitude level has been increased is input from the video signal line 404 to the sampling circuit 403, and the sampling circuit 403 performs an operation of sampling the video signal based on the input timing signal. The sampled video signals are sequentially applied to the corresponding source signal lines S1 and S2.

Next, a circuit diagram of the gate signal line drive circuit of this embodiment is shown in FIG. From the outside of the gate signal line driving circuit, a signal (G−L) that is inverted with respect to a common potential of the gate clock signal (G−CL) and the gate clock signal (G−CL).
CLb) is input to the gate signal line driving circuit.

The gate clock signal (G-CL) input to the gate signal line driving circuit is input to the gate shift register circuit 501.

On the basis of the gate clock signal (G-CL) input to the gate shift register circuit 501, a gate start pulse signal (G-SP) input to the gate shift register circuit 501 simultaneously causes a gate. The shift register circuit 501 performs an operation of sequentially generating a selection signal for operating all the pixel TFTs connected to the gate signal line. The generated selection signal is input to the gate level shift circuit 502.

The gate level shift circuit 502
The voltage amplitude level of the selection signal input to the gate level shift circuit 502 is increased. This selection signal needs to be raised to a voltage amplitude level necessary for reliably operating all the pixel TFTs. The selection signal having the increased voltage amplitude level is input to the gate signal lines G0, G1, and G2, and the pixel TFT performs an operation of applying a video signal to the liquid crystal. FIG. 6A illustrates an example of a circuit diagram of the shift register circuit (the source shift register circuit 401 and the gate shift register circuit 501) used for each driver circuit.

FIG. 6B shows an equivalent circuit diagram of the level shift circuits (the source level shift circuit 402 and the gate level shift circuit 502) used in each drive circuit.
in means that a signal is input, and inb means that an inverted signal of in is input. VDD indicates a plus voltage. The level shift circuit is in
The signal obtained by raising the voltage of the signal input to
It is designed to output from tb. That is, i
When Hi is input to n, the signal from outb to Lo becomes L
When o is input, a Hi signal is output from out.

(Embodiment 3) In this embodiment, the case where the TFT substrate has a digital drive circuit will be described with reference to FIG.

In the display of this embodiment, a source signal line driving circuit A301, a source signal line driving circuit B302, a gate signal line driving circuit 303, a digital video data dividing circuit 305, and a plurality of pixel TFTs are arranged in a matrix on a TFT substrate. Has a pixel portion 304 provided for the pixel.
The source signal line driver circuit B302 has the same configuration as the source signal line driver circuit A301.

The source signal line driving circuit 301 and the gate signal line driving circuit 303 drive a plurality of pixel TFTs provided in the pixel portion 304. Source signal line driving circuit 301 and gate signal line driving circuit 3 from outside via FPC terminal
In 03, various signals are input to the pixel portion 304.

The source signal line driving circuit A301 includes a source signal line side shift register circuit (240 stages × 2 shift register circuits) 301-1 and a latch circuit 1 (960).
× 8 digital latch circuit) 301-2, latch circuit 2
(960 × 8 digital latch circuit) 301-3, selector circuit 1 (240 selector circuit) 301-4, D / A
It has a conversion circuit (DAC of 240) 301-5 and a selector circuit 2 (selector circuit of 240) 301-6.
In addition, a buffer circuit and a level shift circuit (both not shown) may be provided. For convenience of explanation, D
The / A conversion circuit 301-5 includes a level shift circuit.

The gate signal line driving circuit 303 has a shift register circuit, a buffer circuit, a level shift circuit and the like (all not shown).

The pixel section 304 is (640 × RGB) × 1
080 (horizontal x vertical) pixels. A pixel TFT is disposed in each pixel, and a source signal line is electrically connected to a source region of each pixel TFT, and a gate signal line is electrically connected to a gate electrode. A pixel electrode is electrically connected to a drain region of each pixel TFT. Each pixel TF
T controls application of a video signal (grayscale voltage) to a pixel electrode electrically connected to each pixel TFT. A video signal (grayscale voltage) is applied to each pixel electrode, and a voltage is applied to the liquid crystal sandwiched between each pixel electrode and the counter electrode to drive the liquid crystal.

Here, the operation of the TFT substrate of this embodiment and the flow of signals will be described.

First, the operation of the source signal line driving circuit A301 will be described. Note that for the operation of the source signal line driver circuit B302, the operation of the source signal line driver circuit A301 may be referred to.

Source signal line side shift register circuit 301
The clock signal (CK) and the start pulse (S
P) is input. The shift register circuit sequentially generates a timing signal based on the clock signal (CK) and the start pulse (SP), and sequentially applies the timing signal to a subsequent circuit through a buffer circuit or the like.

Source signal line side shift register circuit 301
The timing signal from -1 is buffered by a buffer circuit or the like. The source signal line to which the timing signal is applied has a large load capacitance (parasitic capacitance) because many circuits or elements are connected. This buffer circuit is formed in order to prevent "dulling" of the rise of the timing signal caused by the large load capacitance.

The timing signal buffered by the buffer circuit is applied to the latch circuit 1 (301-2). The latch circuit 1 (301-2) has 960 stages of latch circuits for processing 8-bit digital video data. When the timing signal is input, the latch circuit 1 (301-2) sequentially captures and holds the 8-bit digital video data applied from the digital video data division circuit 305.

The time required until the writing of digital video data to the latch circuits in all the stages of the latch circuit 1 (301-2) is completed is called a line period.
That is, from the time when the writing of the digital video data to the latch circuit of the leftmost stage in the latch circuit 1 (301-2) starts, the writing of the digital video data to the latch circuit of the rightmost stage ends. The time interval up to the point in time is the line period. Actually, a period in which the horizontal retrace period is added to the line period may be referred to as a line period.

After the completion of one line period, the latch signal (La) is sent to the latch circuit 2 (301-3) in accordance with the operation timing of the source signal line side shift register circuit 301-1.
tchSignal) is applied. At this moment, the latch circuit 1
The digital video data written and held in (301-2) is simultaneously sent to the latch circuit 2 (301-3), and written and held in the latch circuits of all stages of the latch circuit 2 (301-3). Is done.

The digital video data is stored in the latch circuit 2 (3
Latch circuit 1 (301-2) that has finished sending to 01-3)
Then, based on the timing signal of the source signal line side shift register circuit 301-1, the writing of the digital video data applied from the digital video data dividing circuit is sequentially performed again.

During this second line period, the digital video data written and held in the latch circuit 2 (301-3) is transferred to the selector circuit 1 (301-4).
Are sequentially selected and applied to the D / A conversion circuit.
In this embodiment, in the selector circuit 1 (301-4), one selector circuit corresponds to four source signal lines.

As the selector circuit, the one described in Japanese Patent Application No. 11-167373, which is a patent application filed by the present applicant, can be used.

Latch circuit 2 selected by selector circuit
The 8-bit digital video data from (301-3) is applied to the D / A conversion circuit.

The D / A conversion circuit converts the 8-bit digital video data into a video signal (grayscale voltage) and sequentially applies the source signal line selected by the selector circuit 2 (301-6).

The video signal applied to the source signal line is applied to the source region of the pixel TFT in the pixel section connected to the source signal line.

In the gate signal line driving circuit 303,
A timing signal (scanning signal) from the shift register is applied to the buffer circuit, and is applied to a corresponding gate signal line (gate signal line). The gate signal lines are connected to the gate electrodes of the pixel TFTs for one line, and all the pixel TFTs for one line must be turned on at the same time. Therefore, a buffer circuit having a large current capacity is used. .

As described above, the gate signal line driving circuit 303
The corresponding pixel TFT is switched by the scanning signal from the pixel TFT, the video signal (grayscale voltage) from the source signal line driving circuit A301 and the source signal line driving circuit B302 is applied to the pixel TFT, and the liquid crystal molecules are driven. .

Digital video data division circuit (SPC;
Serial-to-Parallel Conversion Circuit) 305
Set the frequency of digital video data input from the outside to 1
/ X (1 <x). By dividing digital video data input from the outside,
The frequency of the signal required for the operation of the drive circuit can be reduced to 1 / x.

(Embodiment 4) Here, the pixel TFT of the pixel portion
And a method for manufacturing TFTs of driver circuits (a source signal line driver circuit, a gate signal line driver circuit, a D / A conversion circuit, a digital video data time gradation processing circuit, and the like) provided around the pixel portion over the same substrate Will be described in detail according to the steps. However, for the sake of simplicity, the control circuit includes a CMOS circuit, which is a basic circuit such as a shift register circuit, a buffer circuit, and a D / A conversion circuit, and an n-channel TF.
Let T be illustrated.

In FIG. 8A, a substrate (TFT substrate)
For 6001, a low alkali glass substrate or a quartz substrate can be used. In the present invention, smart cut, SIMO
An SOI substrate such as X or ELTRAN may be used. In this embodiment, a low alkali glass substrate was used. In this case, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. TFT of this substrate 6001
A base film 6002 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on a surface on which is formed to prevent impurity diffusion from the substrate 6001. For example, a silicon oxynitride film made of SiH ₄ , NH ₃ , and N ₂ O by plasma CVD is 100 nm, and S
a silicon oxynitride film made of iH ₄ and N ₂ O
The layer is formed to a thickness of 0 nm.

Next, 20 to 150 nm (preferably 30 nm)
Semiconductor film 60 having an amorphous structure with a thickness of
03a is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used.
In addition, since the base film 6002 and the amorphous silicon film 6003a can be formed by the same film formation method, both may be formed continuously. After the formation of the base film, it is possible to prevent the surface from being contaminated by not once exposing it to the atmosphere, thereby reducing the variation in the characteristics of the TFT to be manufactured and the fluctuation of the threshold voltage. (FIG. 8A)

Then, using a known crystallization technique, the amorphous silicon film 6003a is converted to the crystalline silicon film 6003.
b is formed. For example, a laser crystallization method or a thermal crystallization method (solid phase growth method) may be applied. At the time of laser crystallization, a continuous emission excimer laser may be used. Here, a crystalline silicon film 6003b was formed by a crystallization method using a catalytic element according to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652. Prior to the crystallization step, depending on the hydrogen content of the amorphous silicon film, 400 to 500
Heat treatment at ℃ for about 1 hour to reduce hydrogen content to 5 atom%
It is desirable to crystallize after the following. When the amorphous silicon film is crystallized, the rearrangement of atoms occurs and the density of the amorphous silicon film is increased. Also decreased by about 1 to 15%. (FIG. 8 (B))

Then, the crystalline silicon film 6003b is divided into islands to form island-like semiconductor layers 6004 to 6007. After that, a mask layer 6008 made of a silicon oxide film having a thickness of 50 to 100 nm is formed by a plasma CVD method or a sputtering method. (FIG. 8 (C))

Then, a resist mask 6009 is provided, and n
Island-shaped semiconductor layers 6005 to 6 forming a channel type TFT
1 × 10 for the purpose of controlling the threshold voltage over the entire surface of 007
Boron (B) was added as an impurity element imparting p-type at a concentration of about ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ . Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film. Although addition of boron (B) is not always necessary here, the semiconductor layer 6010 to which boron (B) is added is added.
6012 was preferably formed to keep the threshold voltage of the n-channel TFT within a predetermined range.
(FIG. 8 (D))

LDD region of n-channel TFT of drive circuit
In order to form the region, the impurity element imparting n-type
It is selectively added to the semiconductor layers 6010 and 6011. That
Therefore, the resist masks 6013 to 6016 are
Formed. As an impurity element imparting n-type, phosphorus
(P) or arsenic (As) may be used.
Phosphine (PH) to add (P)_Three)
An ion doping method was applied. Impurity region 60 formed
The phosphorus (P) concentration of 17, 6018 is2 × 10 ^{16 to} 5 × 1
0 ¹⁹ atoms / cm ³ Should be within the range. In this specification,
Included in impurity regions 6017 to 6019 formed here
(N) ^-) And table
You. The impurity region 6019 is a pixel matrix circuit.
Semiconductor layer for forming a storage capacitor of
Was also added at the same concentration. (FIG. 9 (A))

Next, a step of removing the mask layer 6008 with hydrofluoric acid or the like and activating the impurity element added in FIGS. 8D and 9A is performed. The activation can be performed by a heat treatment at 500 to 600 ° C. for 1 to 4 hours in a nitrogen atmosphere or a laser activation method. Further, both may be performed in combination. In this embodiment, a KrF excimer laser beam (wavelength 248) is used by using a laser activation method.
nm) to form a linear beam and generate an oscillation frequency of 5 to 5 nm.
50 Hz, energy density 100 to 500 mJ / cm ²
The overlap ratio of the linear beam is 80 to 98%
To process the entire surface of the substrate on which the island-shaped semiconductor layer was formed. There are no particular restrictions on the laser light irradiation conditions, and the conditions may be determined appropriately by the practitioner. Activation may be performed using a continuous light excimer laser.

Then, the gate insulating film 6020 is formed of an insulating film containing silicon with a thickness of 10 to 150 nm by a plasma CVD method or a sputtering method. For example, 12
A silicon oxynitride film is formed with a thickness of 0 nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure. (FIG. 9 (B))

Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed as a single layer, or may be formed as a two-layer or three-layer structure as necessary. In this embodiment, a conductive layer (A) 6021 made of a conductive nitride metal film and a conductive layer (B) 6022 made of a metal film are stacked. Conductive layer (B) 602
2 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the above elements as a main component, or an alloy film combining the above elements (typically, The conductive layer (A) 6021 may be formed of tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), or molybdenum nitride (MoN). Form. The conductive layer (A) 6021 is used as an alternative material.
Tungsten silicide, titanium silicide, or molybdenum silicide may be used. Conductive layer (B) 6022
It is better to reduce the impurity concentration contained in order to reduce the resistance, and it is particularly preferable that the oxygen concentration be 30 ppm or less. For example, when tungsten (W) has an oxygen concentration of 30 ppm or less, a specific resistance of 20 μΩcm or less can be realized.

The conductive layer (A) 6021 has a thickness of 10 to 50 nm.
(Preferably 20 to 30 nm), and the conductive layer (B) 60
22 is 200 to 400 nm (preferably 250 to 350 nm)
nm). In this embodiment, the conductive layer (A) 60
A 21 nm-thick tantalum nitride film was used for 21, and a 350 nm-thick Ta film was used for the conductive layer (B) 6022, both of which were formed by sputtering. In the film formation by the sputtering method, if an appropriate amount of Xe or Kr is added to Ar of the gas for sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 6021. Thereby, the adhesion of the conductive film formed thereon is improved and oxidation is prevented, and at the same time, the conductive layer (A) 60 is formed.
It is possible to prevent a small amount of an alkali metal element contained in the gate insulating film 6020 from being dispersed in the gate insulating film 6020. (FIG. 9 (C))

Next, resist masks 6023 to 6027
Are formed, and a conductive layer (A) 6021 and a conductive layer (B) 602 are formed.
2 and the gate electrodes 6028-60
31 and a capacitor wiring 6032 are formed. Gate electrode 602
8 to 6031 and the capacitor wiring 6032 are formed integrally with 6028a to 6032a made of a conductive layer (A) and 6028b to 6032b made of a conductive layer (B). At this time, gate electrodes 6029 and 603 formed in the driver circuit
0 is formed so as to overlap with part of the impurity regions 6017 and 6018 with the gate insulating film 6020 interposed therebetween. (FIG. 9
(D))

Next, in order to form a source region and a drain region of the p-channel TFT of the driver circuit, a step of adding an impurity element imparting p-type is performed. Here, the impurity region is formed in a self-aligned manner using the gate electrode 6028 as a mask. At this time, the n-channel TFT
Are formed with a resist mask 6033. Then, an impurity region 6034 was formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 6034 formed here is expressed as (p ⁺ ). (FIG. 10A)

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 6035 to 6037 were formed, and an impurity element imparting n-type was added to form impurity regions 6038 to 6042. This is performed by an ion doping method using phosphine (PH ₃ ), and the concentration of phosphorus (P) in this region is set to 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ^3.
And In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 6038 to 6042 formed here is expressed as (n ⁺ ). (FIG. 10B)

Although impurity regions 6038 to 6042 contain phosphorus (P) or boron (B) already added in the previous step, phosphorus (P) is added at a sufficiently high concentration. Therefore, it is not necessary to consider the influence of phosphorus (P) or boron (B) added in the previous step.
The concentration of phosphorus (P) added to impurity region 6038 is １ ／ of the concentration of boron (B) added in FIG.
Since it was １ ／, p-type conductivity was ensured, and there was no effect on the characteristics of the TFT.

Then, a step of adding an impurity for imparting n-type for forming an LDD region of the n-channel TFT of the pixel matrix circuit was performed. Here, the gate electrode 603
Using n as a mask, an impurity element imparting n-type in a self-aligned manner was added by an ion doping method. The concentration of phosphorus (P) to be added is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ , and FIG.
10A and 10A and 10B, the impurity regions 6043 and 6044 are formed substantially by adding the impurity element at a lower concentration than the concentration of the impurity element. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 6043 and 6044 is expressed as (n ⁻ ). (FIG. 10 (C))

Thereafter, a heat treatment step is performed to activate the n-type or p-type imparting impurity elements added at the respective concentrations. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation step was performed by the furnace annealing method. The heat treatment is performed in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, at 400 to 800 ° C, typically 500 to 600 ° C.
In this embodiment, the heat treatment was performed at 550 ° C. for 4 hours. When a substrate having heat resistance such as a quartz substrate is used as the substrate 6001,
The heat treatment may be performed for a long time, and the activation of the impurity element and the junction between the impurity region to which the impurity element is added and the channel formation region can be favorably formed.

In this heat treatment, the gate electrode 6028
Film 6028 for forming the capacitor wiring 6032 with the capacitor wiring 6032
As for b to 6032b, conductive layers (C) 6028c to 6032c are formed with a thickness of 5 to 80 nm from the surface. For example, when the conductive layers (B) 6028b to 6032b are tungsten (W), tungsten nitride (WN) is formed, and when the conductive layers (B) 6028b to 6032b are tantalum (Ta), tantalum nitride (Ta) is formed.
N) can be formed. In the present invention, a laminate of a silicon (Si) film, a WN film and a W film,
A gate electrode may be formed using a stack of a W film having i, a stack of a W film and a W film having Si and Si, a W film having Mo, or a Ta film having Mo. Further, the conductive layers (C) 6028c to 6032c can be formed in the same manner even when the gate electrodes 6028 to 6031 are exposed to a plasma atmosphere containing nitrogen using nitrogen or ammonia. Further, heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the island-shaped semiconductor layer.
In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma or hydrogen converted into plasma) may be performed.

The island-shaped semiconductor layer is formed from the amorphous silicon film.
When produced by the crystallization method using a medium element,
A trace amount of catalytic element remained in the conductor layer. Of course
It is possible to complete the TFT in such a state,
Remove the remaining catalyst element from at least the channel formation region.
I preferred to leave. Remove this catalytic element
Utilizing the gettering action of phosphorus (P) as one of the means
There was a way to do that. Phosphorus (P) required for gettering
The concentration is the impurity region (n ⁺Same as)
Of the activation process performed here.
And n-channel TFT and p-channel TFT.
Gettering of catalytic elements from the channel formation region
did it. (FIG. 10 (D))

When the activation and hydrogenation steps are completed,
A second conductive film serving as a gate wiring is formed. This second conductive film has a conductive layer (D) 6045 mainly composed of aluminum (Al) or copper (Cu), which is a low-resistance material, and titanium (Ti), tantalum (Ta), tungsten (W), Conductive layer (E) 60 made of molybdenum (Mo)
46 is preferable. In this embodiment, titanium (T
An aluminum (Al) film containing i) of 0.1 to 2% by weight was formed as a conductive layer (D) 6045, and a titanium (Ti) film was formed as a conductive layer (E) 6046. Conductive layer (D) 6045
Is 200 to 400 nm (preferably 250 to 350 n
m), and the conductive layer (E) 6046 is 50 to 20
The thickness may be 0 nm (preferably 100 to 150 nm). (FIG. 11A)

The conductive layer (E) 6046 and the conductive layer (D) are formed to form a gate wiring connected to the gate electrode.
6045 and the gate wiring 604
7, 6048 and a capacitor wiring 6049 were formed. First, the conductive layer (E) 6046 is etched by a dry etching method using a mixed gas of SiCl ₄ , Cl ₂ and BCl _3.
Of the conductive layer (D) 6045 from the surface of the conductive layer (D) 6045 and then removing the conductive layer (D) 6045 by wet etching with a phosphoric acid-based etching solution to maintain the selectivity with the base and to form the gate wiring. Could be formed. (FIG. 11B)

The first interlayer insulating film 6050 is 500 to 15
A contact hole which is formed of a silicon oxide film or a silicon oxynitride film with a thickness of 00 nm and reaches a source region or a drain region formed in each of the island-shaped semiconductor layers is formed.
Then, drain wirings 6055 to 6058 are formed. Although not shown, in this embodiment, this electrode is
A three-layer laminated film in which 0 nm, an aluminum film containing Ti, 300 nm, and a Ti film, 150 nm, were continuously formed by a sputtering method.

Next, as the passivation film 6059, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed to a thickness of 50 to 500 nm (typically, 100 to 3 nm).
(00 nm). When hydrogenation was performed in this state, favorable results were obtained with respect to the improvement of TFT characteristics. For example, in an atmosphere containing 3 to 100% hydrogen, 3
It is good to perform heat treatment at 00 to 450 ° C. for 1 to 12 hours,
Alternatively, the same effect was obtained by using the plasma hydrogenation method. Here, at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later,
An opening may be formed in the passivation film 6059. (FIG. 11 (C))

Thereafter, a second interlayer insulating film 6060 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide,
Polyimide amide, BCB (benzocyclobutene) and the like can be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate and baked at 300 ° C. is used. Then, a contact hole reaching the drain wiring 6058 is formed in the second interlayer insulating film 6060, and pixel electrodes 6061 and 6062 are formed. For a pixel electrode, a transparent conductive film may be used for a transmissive liquid crystal panel, and a metal film may be used for a reflective liquid crystal panel. In this embodiment, in order to form a transmissive liquid crystal panel, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by a sputtering method. (FIG. 12)

In this way, the TFT of the driving circuit is formed on the same substrate.
And a substrate having pixel TFTs in the pixel portion. The driving circuit includes a p-channel TFT 6101,
A first n-channel TFT 6102, a second n-channel TFT 6103, a pixel TFT 6104 in the pixel portion, and a storage capacitor 6105 were formed. In this specification, such a substrate is referred to as a TFT substrate for convenience.

P-channel TFT 6101 of Driver Circuit
Are formed in the island-shaped semiconductor layer 6004 in the channel formation region 610.
6, source regions 6107a and 6107b, and drain regions 6108a and 6108b. The first n-channel TFT 6102 has an LD which overlaps the channel formation region 6109 and the gate electrode 6029 in the island-shaped semiconductor layer 6005.
A D region 6110 (hereinafter, such an LDD region is referred to as Lov), a source region 6111, and a drain region 6112 are provided. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. The second n-channel TFT 6103 includes a channel formation region 6113, LDD regions 6114 and 6115, a source region 6116, and a drain region 6117 in the island-shaped semiconductor layer 6006. This LDD region is an LDD region that does not overlap with the Lov region and the gate electrode 6030 (hereinafter referred to as an LDD region).
Such an LDD region is referred to as Loff).
The length of the Loff region in the channel length direction is 0.3 to 2.
0 μm, preferably 0.5 to 1.5 μm. Pixel T
In the FT 6104, channel formation regions 6118 and 6119 and Loff regions 6120 to 61 are formed in the island-shaped semiconductor layer 6007.
23, a source or drain region 6124-6126. The length of the Loff region in the channel length direction is 0.
It is 5-3.0 μm, preferably 1.5-2.5 μm. Further, the capacitor wirings 6032 and 6049, an insulating film made of the same material as the gate insulating film 6020, and a pixel TFT
A storage capacitor 6105 is formed from the semiconductor layer 6127 to which the impurity element imparting n-type is added and which is connected to the drain region 6126 of the semiconductor layer 6104. In FIG. 12, the pixel TF
Although T6104 has a double gate structure, it may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

In this way, a substrate having a driving circuit TFT and a pixel TFT of a pixel portion on the same substrate can be completed. A p-channel TFT 6101, a first n-channel TFT 6102, a second n-channel TFT 6103 are formed in the driver circuit, and a pixel TFT 6104 and a storage capacitor 6105 are formed in the pixel portion (FIG. 12). In this specification, such a substrate is referred to as a TFT substrate for convenience.

Next, the TF produced by the above-described steps
A process for manufacturing a liquid crystal panel based on a T substrate will be described.

The alignment film 607 is formed on the TFT substrate in the state shown in FIG.
0 is formed. In this embodiment, polyimide is used for the alignment film 6070 (FIG. 13A). Next, a counter substrate is prepared. The opposing substrate is a glass substrate 6075, a color filter 6074, and an opposing electrode 607 made of a transparent conductive film.
3, and an alignment film 6072. Note that the color of the color filter 6074 corresponds to each pixel of the pixel portion.

In this embodiment, as the alignment film 6070, a polyimide film in which liquid crystal molecules are aligned in parallel with the substrate is used. After the alignment film was formed, a rubbing treatment was performed so that the liquid crystal molecules were aligned in parallel with a certain pretilt angle.

Next, the TFT substrate and the counter substrate having undergone the above-described steps are bonded together by a known cell assembling step via a sealant, a spacer (both not shown), or the like. Thereafter, a liquid crystal 6071 is injected between the two substrates, and completely sealed with a sealant (not shown). Thus, a reflective liquid crystal panel as shown in FIG. 14 is completed. (FIG. 13 (B))

As described above, in the present embodiment, the TFTs constituting each circuit according to the specifications required by the pixel TFT and the driving circuit.
By optimizing the structure of the FT, it is possible to improve the operation performance and reliability of the semiconductor device. Further, the gate electrode is formed of a conductive material having heat resistance to facilitate activation of the LDD region, the source region, and the drain region, and the wiring resistance can be sufficiently reduced by forming the gate wiring with a low-resistance material. Therefore, the present invention can be applied to a display device having a pixel portion (screen size) of 4 inch class or more.

(Embodiment 5) In this embodiment, an example in which the liquid crystal panel of the present invention is configured using an inverted staggered TFT will be described.

Referring to FIG. FIG. 14 shows an inverted staggered N-channel TF constituting the liquid crystal panel of this embodiment.
A cross-sectional view of T is shown. Although only one N-channel TFT is shown in FIG.
It goes without saying that a CMOS circuit can be formed by the FT and the N-channel TFT. Needless to say, the pixel TFT can be configured by the same configuration.

Reference numeral 3001 denotes a substrate, which is similar to that described in the fourth embodiment. Reference numeral 3002 denotes a silicon oxide film. 3003 is a gate electrode. Reference numeral 3004 denotes a gate insulating film. Reference numerals 3005, 3006, 3007, and 3008 denote active layers made of a polycrystalline silicon film.
In manufacturing the active layer, the same method as in the polycrystallization of the amorphous silicon film described in the fourth embodiment was used.
Alternatively, a method of crystallizing an amorphous silicon film by laser light (preferably, linear laser light or planar laser light) may be employed. Note that 3005 is a source region,
Reference numeral 3006 denotes a drain region, 3007 denotes a low concentration impurity region (LDD region), and 3008 denotes a channel formation region.
Reference numeral 3009 denotes a channel protective film, and 3010 denotes an interlayer insulating film. 3011 and 3012 are a source wiring and a drain wiring, respectively.

Next, reference will be made to FIG. FIG. 15 shows an inversely staggered TFT having a configuration different from that shown in FIG.
The case where the liquid crystal panel is formed by the following will be described.

Also in FIG. 15, one N-channel type T
Although only FT is shown, as described above, the P-channel type TF
It goes without saying that a CMOS circuit can be constituted by the T and N-channel TFTs. Needless to say, the pixel TFT can be configured by the same configuration.

Reference numeral 3101 denotes a substrate. Reference numeral 3102 denotes a silicon oxide film. 3103 is a gate electrode. 310
Reference numeral 4 denotes a benzodiclobutene (BCB) film, the upper surface of which is flattened. Reference numeral 3105 denotes a silicon nitride film. B
A gate insulating film is formed by the CB film and the silicon nitride film.
Reference numerals 3106, 3107, 3108 and 3109 are active layers made of a polycrystalline silicon film. In manufacturing the active layer, the same method as in the polycrystallization of the amorphous silicon film described in the fourth embodiment was used. Alternatively, a method of crystallizing an amorphous silicon film by laser light (preferably, linear laser light or planar laser light) may be employed. 3106 is a source region, 3107 is a rain region, 3108 is a low concentration impurity region (LDD region),
Reference numeral 3109 denotes a channel formation region. Reference numeral 3110 denotes a channel protective film, and 3111 denotes an interlayer insulating film. 311
2 and 3113 are a source wiring and a drain wiring, respectively.

According to this embodiment, since the gate insulating film composed of the BCB film and the silicon nitride film is flattened, the amorphous silicon film formed thereon is also flat. Therefore, when the amorphous silicon film is polycrystallized, a polycrystalline silicon film more uniform than the conventional inverted staggered TFT can be obtained.

(Embodiment 6) The liquid crystal panel of the present invention
Various liquid crystals other than the N liquid crystal can be used.
For example, 1998, SID, "Characteristics and Driving Sc
heme of Polymer-Stabilized Monostable FLCD Exhibit
ing Fast Response Time and High Contrast Ratio wit
h Gray-Scale Capability "by H. Furue et al., 199
7, SID DIGEST, 841, "A Full-Color Thresholdless An
tiferroelectric LCD Exhibiting Wide Viewing Angle
with Fast Response Time "by T. Yoshida et al., 1
996, J. Mater. Chem. 6 (4), 671-673, "Thresholdless
antiferroelectricity in liquid crystals and its ap
The liquid crystals disclosed in S. Inui et al. and U.S. Pat. No. 5,594,569 can be used.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal. As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V (cell thickness is about 1 μm to 2 μm).
m) have also been found.

FIG. 16 shows an example of characteristics of light transmittance with respect to applied voltage of a thresholdless antiferroelectric mixed liquid crystal exhibiting a V-shaped electro-optical response. The vertical axis of the graph shown in FIG. 16 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. The transmission axis of the polarizing plate on the incident side of the liquid crystal panel is set substantially parallel to the normal direction of the smectic layer of the thresholdless antiferroelectric mixed liquid crystal, which substantially coincides with the rubbing direction of the liquid crystal panel. The transmission axis of the exit-side polarizing plate is substantially perpendicular to the transmission axis of the incidence-side polarizing plate (crossed Nicols).
Is set to

As shown in FIG. 16, it can be seen that the use of such a thresholdless antiferroelectric mixed liquid crystal enables low voltage driving and gradation display.

When such a low-voltage driven thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal panel having an analog driving circuit, the power supply voltage of the image signal sampling circuit is, for example, 5 V to 8 V. It can be suppressed to the extent. Therefore, the operating power supply voltage of the driving circuit can be reduced, and low power consumption and high reliability of the liquid crystal panel can be realized.

Further, even when such a low-voltage driven thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal panel having a digital drive circuit, the output voltage of the D / A conversion circuit can be reduced. Therefore, the operation power supply voltage of the D / A conversion circuit can be reduced, and the operation power supply voltage of the drive circuit can be reduced. Therefore, low power consumption and high reliability of the liquid crystal panel can be realized.

Therefore, the use of such a low-voltage-driven thresholdless antiferroelectric mixed liquid crystal can reduce the width of the LDD region (low-concentration impurity region) of a TFT (for example, TFT).
(0 nm to 500 nm or 0 nm to 200 nm) is also effective.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal panel, a relatively large storage capacitor is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization. In addition, by setting the driving method of the liquid crystal panel to line-sequential driving, the writing period of the gray scale voltage to the pixel (pixel feed period)
May be lengthened to compensate for the small storage capacity.

Since low-voltage driving is realized by using such a thresholdless antiferroelectric mixed liquid crystal, low power consumption of the liquid crystal panel is realized.

Note that any liquid crystal having electro-optical characteristics as shown in FIG. 16 can be used as the display medium of the liquid crystal panel of the present invention.

(Embodiment 7) FIG. 17 shows an example in which a liquid crystal panel is constructed using the TFT substrates having the structures shown in Embodiments 1 to 5. FIG. 17 shows a portion corresponding to the main body of the liquid crystal panel, which is also called a liquid crystal panel.

In FIG. 17, reference numeral 8001 denotes a TFT substrate on which a plurality of TFTs are formed. These TFTs are formed on a substrate by a pixel portion 8002, a gate signal line driving circuit 8003, a source signal line driving circuit 8
004, a logic circuit 8005 is formed. Such T
The opposite substrate 8006 is attached to the FT substrate.
A liquid crystal layer (not shown) is sandwiched between the TFT substrate and the opposite substrate 8006.

In the configuration shown in FIG. 17, it is desirable that the side surface of TFT substrate 8001 and the side surface of counter substrate 8006 are all aligned except for one side. This makes it possible to efficiently increase the number of multi-face removal from the large-size substrate. In addition, on one side of the above, a part of the counter substrate 8006 is removed to expose a part of the TFT substrate 8001, and an FPC (flexible print circuit) 800
7 is attached. Here, an IC chip (semiconductor circuit including a MOSFET formed on single crystal silicon) may be mounted as needed.

Since the TFT formed by the manufacturing process shown in Embodiment 4 or Embodiment 5 has an extremely high operation speed, a signal processing circuit driven at a high frequency of several hundred MHz to several GHz is used in the pixel portion. And can be integrally formed on the same substrate. That is, the liquid crystal panel shown in FIG. 17 embodies a system-on-panel.

(Embodiment 8) A CMOS circuit or a pixel matrix circuit formed by implementing the present invention can be used for various electro-optical devices (active matrix type liquid crystal panels). That is, the present invention can be applied to all electronic devices in which these electro-optical devices are incorporated as display media.

Such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a game machine, a car navigation, a personal computer, and a portable information terminal (mobile computer). , A mobile phone or an electronic book).
One example of them is shown in FIG.

FIG. 18A shows a personal computer, which includes a main body 7001, a video input unit 7002, and a display
003 and a keyboard 7004. The present invention can be applied to the video input unit 7002 and the display device 7003.

FIG. 18B shows a video camera, which includes a main body 7101, a display device 7102, an audio input portion 7103, operation switches 7104, a battery 7105, and an image receiving portion 71.
06. The present invention can be applied to the display device 7102 and the voice input portion 7103.

FIG. 18C shows a mobile computer (mobile computer), which comprises a main body 7201, a camera section 7202, an image receiving section 7203, operation switches 7204, and a display device 7205. The present invention relates to a display device 720.
5 is applicable.

FIG. 18D shows a goggle type display, which includes a main body 7301, a display device 7302, and an arm portion 73.
03. The present invention can be applied to the display device 7302.

FIG. 18E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 7401, a display device 7402, and a speaker 74.
03, a recording medium 7404, and operation switches 7405. This device uses a DVD (Di) as a recording medium.
A digital versatile disc), a CD, and the like can be used for music appreciation, movie appreciation, games, and the Internet. The invention can be applied to the display device 7402.

FIG. 18F shows a game machine, and a main body 75.
01, a main body display device 7502, a display device 7503, a recording medium 7504, a controller 7505, a main body sensor unit 7506, a sensor unit 7507, and a CPU unit 7508. Main body sensor 7506, sensor 7507
Can sense infrared rays emitted from the controller 7505 and the main body 7501, respectively. The present invention can be applied to the main body display device 7502 and the display device 7503.

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus according to the present embodiment can be realized by using any combination of the embodiments 1 to 7.

[0170]

According to the present invention, the frame frequency is set to 120 Hz.
Driving was performed by the frame inversion driving method.
Each pixel corresponds to one of R, G, and B of the color filter provided on the TFT substrate side. With the above structure, in a display device of a direct-view type having a short pixel pitch of 20 μm or less, bright display with good contrast without disclination or flicker was observed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a timing chart of a liquid crystal panel of the present invention.

FIG. 2 is a schematic view of a TFT substrate of the present invention.

FIG. 3 is a diagram showing an arrangement of a pixel and a color filter of the present invention.

FIG. 4 is a diagram illustrating an example of a source signal line driver circuit of the present invention.

FIG. 5 is a diagram illustrating an example of a gate signal line driver circuit of the present invention.

FIG. 6 is an equivalent circuit diagram of a shift register circuit and a level shift circuit.

FIG. 7 is a diagram of a TFT substrate having a digital drive circuit.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 12 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 13 is a cross-sectional view illustrating a manufacturing process of a TFT of the present invention.

FIG. 14 is a cross-sectional view illustrating a structure of a TFT of the present invention.

FIG. 15 is a cross-sectional view illustrating a structure of a TFT of the present invention.

FIG. 16 is a graph showing characteristics of light transmittance with respect to an applied voltage of a thresholdless antiferroelectric mixed liquid crystal.

FIG. 17 is an external view of a liquid crystal panel of the present invention.

FIG. 18 is a diagram of an electronic device using the display device of the present invention.

FIG. 19 is a top view and a display pattern of a TFT substrate.

FIG. 20 is a diagram showing polarity patterns of source line inversion driving and gate line inversion driving.

FIG. 21 is an enlarged view of a pixel portion.

FIG. 22 is a diagram showing a mechanism of occurrence of disclination.

FIG. 23 is a diagram showing a polarity pattern of frame inversion driving.

FIG. 24 is a diagram showing a timing chart of a conventional liquid crystal panel.

[Explanation of symbols]

 1801 source signal line driver circuit 1802 gate signal line driver circuit 1803 source signal line 1804 gate signal line 1805 pixel TFT (switching element) 1806 liquid crystal cell 1807 storage capacitor 1808 pixel portion 1809 image signal line

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/20 680 G09G 3/20 680V H01L 29/786 H01L 29/78 612C 21/336 616A 617T 627E

Claims (17)

[Claims] A plurality of gate signal lines, a plurality of source signal lines, and a plurality of pixel electrodes provided at respective intersections of the plurality of gate signal lines and the plurality of source signal lines. In a display device having a substrate, in a first frame period, a first video signal having the same polarity is applied to the plurality of pixel electrodes through the plurality of source signal lines; In the second frame period, a second video signal having a polarity opposite to that of the first video signal is applied to the plurality of pixel electrodes through the plurality of source signal lines. Display device. 2. A plurality of gate signal lines, a plurality of source signal lines, and a plurality of pixel electrodes provided at respective intersections of the plurality of gate signal lines and the plurality of source signal lines. In a display device having a substrate, a video signal of the same polarity is applied to the plurality of pixel electrodes through the plurality of source signal lines, and the polarity of the video signal changes every frame period. Display device. 3. A plurality of gate electrodes, a plurality of source signal lines, a plurality of switching elements and a plurality of pixel electrodes provided at respective intersections of the plurality of gate signal lines and the plurality of source signal lines. A video signal of the same polarity is applied to the plurality of switching elements through the plurality of source signal lines, and the plurality of switching elements are provided through the plurality of gate signal lines. A selection signal for selecting the video signal is applied to the plurality of pixel electrodes through the plurality of switching elements, a video signal selected by the selection signal is applied, and the polarity of the video signal is A display device, wherein the display device changes every frame period. 4. The display device according to claim 1, wherein the first frame period and the second frame period have a length of 8.3 msec or less. 5. The method according to claim 2, wherein
A display device, wherein the length of the frame period is 8.3 msec or less. 6. The display device according to claim 1, wherein an interval between the plurality of gate signal lines or the plurality of source signal lines is 20 μm or less. 7. The switching element according to claim 3, wherein the plurality of switching elements are provided between a gate electrode, a semiconductor layer having a source region, a drain region, and a channel formation region, and between the gate electrode and the semiconductor layer. An insulating film, and any one of the plurality of gate signal lines is connected to the gate electrode; and any one of the plurality of source signal lines is the source region or the drain region A display device, which is connected to a display device. 8. The display device according to claim 1, wherein the display device has a second substrate provided with a color filter including three colors. 9. The display device according to claim 8, wherein each of the plurality of pixel electrodes corresponds to one of three colors included in the color filter. 10. The display device according to claim 8, wherein a liquid crystal is provided between the substrate and the second substrate. 11. A goggle type display having one of the display devices according to claim 1. Description: 12. A goggle type display comprising two of the display devices according to claim 1. Description: 13. A mobile computer having one of the display devices according to claim 1. Description: 14. A notebook personal computer having one of the display devices according to claim 1. Description: 15. A video camera having one display device according to claim 1. Description: 16. A DVD player having one of the display devices according to claim 1. Description: 17. A game machine comprising one of the display devices according to claim 1. Description: