JPH0850277A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To perform displaying operation at high frame frequency by simple constitution by dividing color display data read out from a storage circuit corresponding to X driving circuits constituted by being divided into plural and supplying the data in parallel. CONSTITUTION:This device is provided with 1st and 2nd line memories LM1 and LM2 storing the color display data equivalent to one line of the color display panel LCD. The 1st and the 2nd line memories LM1 and LM2 are controlled to perform write and readout alternately, and the color display data read out from the memories LM1 and LM2 is divided corresponding to the X driving circuits XDVL and XDVR constituted by being divided into plural and supplied in parallel. In such constitution, only two lines of data are stored as the storage circuit storing the color display data, so that the storage capacity of the storage circuit required for the displaying operation is reduced.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color display device, for example, a high resolution color display having a relatively large screen suitable for a display device in a computer system or various control devices. The present invention relates to a technology effectively applied to a device having a liquid crystal panel. 2. Description of the Related Art An example of a color liquid crystal display device is disclosed in JP-A-59-212101. This color liquid crystal display device has a structure in which color display data is once stored in a frame memory, and then color data consisting of red, green, and blue is repeatedly read for each line of the color liquid crystal display panel and given to the color liquid crystal display panel. Has become. In the above-mentioned color liquid crystal display device, when an attempt is made to drive a color liquid crystal display panel having a relatively large screen such as 640 × 200 dots, one screen is correspondingly displayed. Since there is a large amount of display data, there is a problem that the storage capacity of the frame memory becomes large. Further, in the above color display panel,
It is necessary to supply red (R), green (G), and blue (B) color data each consisting of 640 dots in one horizontal period. The liquid crystal display frame frequency is X (signal line) that performs serial / parallel conversion of the color data.
It depends on the data transfer rate of the drive circuit. For example, when "HD66106" sold by Hitachi, Ltd. with a maximum transfer rate of 6 MHz is used, the frame frequency f
Is obtained by [Equation 1]. ## EQU1 ## f = 1 / (1/6 MHz) × (640/4) × (200 × 3) = 62.5 Hz where 640/4 in the second term of the denominator is a 4-bit unit. Means that color data is transferred serially, and the term 200 × 3 in the third term means that one color dot (line) is composed of three primary color lines of R, G, and B. are doing. As described above, the frame frequency f is 62.
If the frequency is only 5 Hz, flickering of the screen and deterioration of the image quality at high temperatures become a problem in the color liquid crystal display panel. That is, in an active matrix liquid crystal display panel, it is necessary to write color data with both positive and negative polarities for AC driving of liquid crystal, and the substantial frame frequency f is about half the frame frequency f. This is because it will drop to 31 Hz. An object of the present invention is to provide a color display device capable of a display operation at a high frame frequency with a simple structure. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings. The outline of typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, first and second storage circuits for storing color display data corresponding to one line of the color display panel are provided, and the first and second storage circuits are alternately controlled to perform writing and reading, and The color display data read out from the first or second storage circuit is divided and supplied in parallel corresponding to the X drive circuit which is divided into a plurality of pieces. According to the above-mentioned means, the storage circuit for storing the color display data can have a small storage capacity because of adopting a configuration for storing the data for the lines, and the X drive circuit can be divided into Correspondingly, since the display data can be input in parallel, the transfer speed in the X drive circuit can be equivalently increased, so that a high quality display screen can be obtained. FIG. 1 is a block diagram showing one embodiment of a color display device according to the present invention. A color liquid crystal display panel LCD having an active matrix structure is used in the color display device of this embodiment. Although not particularly limited, the color liquid crystal display panel LCD has 64 pixels as shown in detail in FIG.
It is possible to display 0 dots × 200 lines of color pixels. One line is formed of a combination of three color filters of red, green and blue in the form of a horizontal stripe.
3, Y4 to Y6 ... Y598, Y599, Y60
Each Y selection (scanning) line is provided like 0. Further, signal lines X1 to X640 are arranged in the vertical direction.
Therefore, the color liquid crystal display panel LCD has 600 Y selection lines in the vertical direction as described above, and the total number of pixels is 640 × 600. In FIG. 1, the color display device includes R, G
And B are provided as color display data. By combining the color data consisting of these three primary colors,
Display of color pixels of eight colors (including white and black) is enabled. The dot clock signal CLK is the display data R,
It is supplied in synchronization with G and B. Display timing signal D
ST is a timing signal that is displayed as visible information (effective display data) in the display data when it is set to the high level and is set to the horizontal blanking period when it is set to the low level. The horizontal synchronizing signal HSYN is a timing signal for controlling one line, and the vertical synchronizing signal VSYN is a timing signal for controlling one frame. The serial / parallel conversion circuit SPC receives the above three color display data R, G and B, and in accordance with the dot clock signal CLK and the display timing signal DST, the color display data R, which is serially input in synchronization with each other. G and B are changed to 4-bit parallel data. These 4-bit parallel data are supplied to the input of a write memory selection circuit (hereinafter simply referred to as a multiplexer) MPX1. The multiplexer MPX1 selectively outputs the color display data converted into the parallel data of 4 bits each in accordance with a control signal R / W described later.
Of the line memory LM1 or the second line memory LM2. The first and second line memories LM1, L
Each M2 has a storage capacity for storing color display data corresponding to one line of the color liquid crystal display panel LCD. That is, since the display panel LCD has 640 dots in the horizontal direction, a storage capacity of 640 × 3 bits is required. Since the parallel data formed by the serial / parallel conversion circuit SPC is input to the line memories LM1 and LM2 as described above, memory access is performed in units of 4 × 3 bits. Therefore, the line memories LM1, LM2
Have addresses 0 to 159 as described later. Although not particularly limited, static RAM (random access memory) is used for the line memories LM1 and LM2. It is also possible to use a dynamic memory cell instead of this structure. Because the line memories LM1 and LM2 are
As will be described later, a writing operation and three reading operations are alternately performed every one horizontal period. Since such a write operation and a read operation are always performed at the extremely short time intervals as described above, the refresh operation is always performed, and even if the dynamic memory cell is used, the static memory cell is Memory access can be performed as used. By doing so, the occupied area of the line memories LM1 and LM2 can be further reduced in combination with the small storage capacity. The first and second line memories LM1, L
A read memory selection circuit (hereinafter simply referred to as a multiplexer) MPX2 is provided on the read output terminal side of M2. The multiplexer MPX2 performs a switching operation complementarily to the write multiplexer MPX1. For example, the write multiplexer MPX1 is provided in one of the line memories LM1 according to the control signal R / W.
When transmitting the parallel display data to (or LM2), the multiplexer MPX2 for reading selects and outputs the read data of the other line memory LM2 (or LM1). The write control circuit WC receives the dot clock signal CLK, the display timing signal DST and the horizontal synchronizing signal HSYN, and generates the control signal R / W and the write address signal WA. In addition, the read control circuit R
The C receives the horizontal synchronizing signal HSYN and generates a read address signal RA and a 2-bit color selection signal CS. For example, by the write control circuit WC,
If the control signal R / W is high level, the multiplexer MP
X1 selects the first line memory LM1. The read / write control circuit RWC responds to the control signal R / W by
The write address signal WA generated by the write control circuit WC is output as the address signal A1 of the line memory LM1. As a result, the color display data R, G and B consisting of the three primary colors serially input for one line are obtained.
Are written in the line memory LM1. On the other hand, the read address signal RA generated by the read control circuit RC is transmitted by the read / write control circuit RWC as the address signal A2 of the second line memory LM2. As a result, the line memory LM2 is read out, and the stored color display data is supplied to the color selection circuit CSEL through the multiplexer MPX2. Since the color selection circuit CSEL outputs the three primary color data R, G and B in parallel in units of 4 bits from the line memory LM2 as described above, it outputs them in accordance with the color selection signal CS. B
Output in time series in the order of. In this embodiment, in order to raise the frame frequency equivalently, each color data which is divided into colors and outputted serially is divided data control circuit DDC.
Is not particularly limited, but is divided into two for each color. Correspondingly, X drive circuits XDVL, XDVR
Is also divided into two. That is, the color liquid crystal display panel L
The display screen of the CD is apparently divided into two parts, the left (L) and the right (R), and the X drive circuits XDVL and XDVR are provided correspondingly. In this configuration, the X drive circuits XDVL and XDVR are provided with the color liquid crystal display panel 640.
Despite having two signal line electrodes, half of that is 320
It has only display data driving capability corresponding to the signal electrodes of the book. Since a configuration is adopted in which two display data are simultaneously read, the transfer speed of the display data can be doubled as viewed from the liquid crystal display panel LCD.
In other words, the time required to fetch the display data for one line can be reduced to half. The timing control circuit TC receives the display timing signal DST and the vertical synchronizing signal VSYN, and receives a data shift clock signal DS necessary for the operation of the X drive circuits XDVL and XDVR and the Y drive circuit YDV.
C, to form a line clock signal LCK. Further, the timing control circuit TC generates a head clock signal LFS supplied to the Y drive circuit YDV. Y drive circuit YDV
Captures the high level of the clock signal LFS at the falling edge of the line clock signal LCK and sets the scanning line Y1 to the high level. Thereafter, in synchronization with the falling edge of the line clock signal CLK, the high level is shifted in correspondence with Y2, Y3, ... Y600 to perform the scanning operation in the vertical direction. FIG. 2 is a timing chart for explaining the operation of the color display device of this embodiment. In the color display device of this embodiment, one frame period is composed of 204 horizontal periods, and the vertical synchronizing signal VSYN is generated almost in synchronization with the first horizontal period. The period from the 203rd horizontal synchronization of the previous frame to the 2nd horizontal period of the frame is defined as a vertical retrace period. Therefore, the display operation in one frame is performed in 200 horizontal periods corresponding to 1 to 200 lines from the third horizontal period to the 202nd horizontal period. One horizontal period includes a horizontal synchronizing signal HSYN.
As shown in the enlarged view of the figure,
While the display timing signal DST is at the high level, the color display data consisting of R, G, and B is regarded as valid display data, and the remaining data is regarded as horizontal blanking data (black display). As the valid display data, red (R), green (G), and blue (B) each consist of 640 dots (bits) as described above. FIG. 3 shows the color liquid crystal display panel LC.
D, its X drive circuits XDVL, XDVR and Y drive circuit YDV are shown. As described above, the color liquid crystal display panel LCD
Has a horizontal stripe-shaped color filter, and one line is composed of three pixel columns of R, G, and B. As described above, the Y drive circuit YDV is
1 to Y600 scan lines, and takes in the line head clock LFS generated at the beginning of the frame,
The Y selection signal is formed by shifting it in synchronization with the line clock signal LCK. Therefore, one horizontal display period is temporally divided into three as described later, and X
R1 of 640 dots from the drive circuits XDVL and XDVR
When data is transmitted, the scanning line Y1 is selected, when G1 data is transmitted, the scanning line Y2 is selected, and when B1 data is transmitted, the scanning line Y3 is selected. As a result, the color image data of the first line 1 in one horizontal period is written in each pixel. In the next horizontal period, X drive circuits XDVL and XD
When the R2 data of 640 dots is transmitted from the VR, the scanning line Y4 is selected, when the G2 data is transmitted, the scanning line Y5 is selected, and when the B2 data is transmitted, the scanning line Y6 is selected. The selected state is set. As a result, the next color image data of line 2 is written in each pixel. Thereafter, similarly, the color pixel data R200, G200, B200 up to the final line 200 is written in each pixel. As a result, one frame is written. The same display data R1, G1, B1 to R200, G200, for the AC driving of the liquid crystal,
The polarity of B200 is inverted and output from the X drive circuits XDVL and XDVR, and the scanning line selection operation similar to the above is performed in synchronization with it. Therefore, the liquid crystal display panel LCD of the active matrix configuration needs to spend two frames to display one screen. FIG. 4 shows the line memory LM1 or L.
A timing diagram is shown for explaining an example of the color display data written in M2. The serial / parallel conversion circuit SPC converts the serially input color display data of each color (R, G and B) into parallel in units of 4 bits to form write parallel data. That is, signals R0 to R159, G0 to G corresponding to each color in units of 4 bits.
159 and B0 to B159 are written in the line memory LM1 or LM2. As a result, 160 × 4 = 640 bits of color display data are written for each color as a whole. FIG. 5 shows the line memories LM1 and LM
2 is shown. In this embodiment, since the write parallel data is input in units of 4.times.3 bits as described above, the line memories LM1 and LM2 store addresses 0 to 1 respectively.
I have 59. In this embodiment, in order to increase the frame frequency as described above, the X drive circuit is divided into two such as XDVL and XDVR as described above. In order to cope with this, signals 0 to R79, G0 to G79 and B0 to B79 to be corresponded to the X drive circuit XDVL are set to the even addresses 0, 2,.
Signals R80 to R159, G80 to be associated with VR
G159 and B80 to B159 are odd addresses 1, 3
..... 159 are assigned respectively. As a result, in the line memories LM1 and LM2, left-side data is stored at odd addresses, right-side data is stored at even addresses, and 4 × 3 = 12-bit color display data is stored at one address. FIG. 6 shows the line memory LM1 or L
A timing diagram is shown to illustrate the read operation from M2. The address signal RA generated by the read control circuit RC is switched by the multiplexer MPX1 according to the level of the control signal R / W and the line memory LM1 (or LM) by the read / write control circuit RWC.
While the above-described writing is being performed on 2), it is transmitted to the other line memory LM2 (or LM1) by the read / write control circuit RWC, and the read signal is output by switching the multiplexer MPX2. At this time, the read control circuit RC generates the address signal RA so that the selected line memory LM2 (or LM1) is read three times in one horizontal period. Therefore, the parallel data read through the multiplexer MPX2 is R0-R159, G0-G159.
And B0 to B159 are repeatedly output three times. A color selection signal CS consisting of two bits is formed according to the number of times of reading by the read control circuit RC. For example, in the first read, the color selection signal CS is 0 (00), and the color selection circuit CSEL is
R of the color display data consisting of the above three primary colors
0 to R159 are output. In the second reading, the color selection signal CS is set to 1 (01) and the color selection circuit C
The SEL outputs G0 to G159 of the color display data composed of the above three primary colors. Then, in the third reading, the color selection signal CS is set to 2 (10), and the color selection circuit CSEL outputs B0 to B159 of the color display data composed of the above three primary colors. Color display data R0 to R159, G0 to G159, and B0 to B1 are divided into odd addresses and even addresses of the line memories LM1 and LM2.
Since 59 is stored, if the read address signals RA are generated in order like 0 to 159, R
Left and right alternate color display data such as 0 and R80 and R1 and R81 are output. Divided data control circuit DDC
Latches the left and right color display data corresponding to the X drive circuits XDVL and XDVR as described above, and supplies them to the X drive circuits XDVL and XDVR. For example, if the serial transfer speed of the X drive circuits XDVL and XDVR is 6 MHz as described above, the line memory L at twice the speed is used.
Reading of M1 and LM2 is performed. The parallel color data divided as described above is synchronized with the data shift clock DSC in units of 4 bits for the color display data of R0 to R79 and R80 to R159 in the X drive circuits XDVL and XDVR, respectively. Then, after the shift is completed and the acquisition is completed, it is distributed to the color display data of X1 to X640 and is output in parallel in synchronization with the line clock LCK. G
0 to G79, G80 to G159 and G0 to G79
Up to G80 to G159, and the output thereof is performed in the same manner as above. However, since the Y drive circuit YDV switches the selection lines from Y1 to Y2 and Y3 in synchronization with the line clock CLK, the display operation corresponding to each color line is performed. In this embodiment, by using two line memories as described above, while the display data is being written to one of the line memories, the other line memory which has already been written can be read. Since the display operation is performed by performing the operation, only a storage circuit having a storage capacity of two lines is provided. Therefore, as compared with the conventional one using the frame memory, the color display device having the large screen and the high image quality as described above can be configured with a small number of memory circuits. That is, when the number of display lines in one screen is N, the storage capacity can be significantly reduced to 2 / N as compared with the conventional case. Since the X drive circuit is divided into two, the time required for the transfer operation is halved. In other words, it is equivalent to doubling the transfer speed of the X drive circuit in the whole display device. Therefore, as is clear from the above description, the frame frequency is 125
Hz and higher frequencies can be achieved. As a result, even if the same display data is written in positive and negative polarities due to the AC drive of the liquid crystal display panel LCD, the frame frequency is 62.5 Hz, and high image quality with less flicker than a home television receiver is obtained. be able to. The operation and effect obtained from the above embodiment are as follows. That is, (1) First and second line memories for storing color display data corresponding to one line of the color display panel are provided, and writing and reading control are alternately performed on these first and second line memories. At the same time, the color display data read out from the first or second line memory is divided and supplied in parallel corresponding to the X drive circuit which is divided into a plurality of pieces. In this configuration, since only the data for two lines is stored as the storage circuit for storing the color display data, the storage capacity of the storage circuit required for the display operation can be reduced. (2) According to the above (1), the liquid crystal display controller can be constituted by a one-chip semiconductor integrated circuit, and the effect of greatly simplifying the system can be obtained. (3) Since the X drive circuit can be divided and the color display data stored in the line memory can be input in parallel corresponding thereto, the transfer rate in the X drive circuit can be equivalently increased, so that the frame frequency can be increased. Therefore, it is possible to obtain a high quality display screen without flicker. (4) In a liquid crystal display panel having an active matrix configuration, a configuration is adopted in which pixels are equivalently regarded as capacitors and display data is held. Therefore, the leakage current increases as the temperature rises. Therefore, by increasing the frame frequency as described above, the number of times of writing per unit time can be increased, and an effect that a display operation up to a high temperature can be realized is obtained. (5) By dividing the above X drive circuit, it is possible to obtain the effect of being able to drive a high-density liquid crystal display panel with a larger screen while using the existing drive circuit. Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
The X drive circuit may be divided into three or more N pieces. In this case, the substantial transfer speed can be increased N times. For example, in FIG. 1, the X drive circuit may be divided into four, and the parallel data formed by the serial / parallel conversion circuit SPC may be changed from 4 bits to 2 bits. With this configuration, the frame frequency is the same, but the serial shift register that constitutes the X drive circuit has a 2-bit configuration, and the circuit can be simplified. Further, in the X drive circuit, the divided X drive circuit may be configured as one semiconductor integrated circuit. That is, a plurality of X drive circuits may be provided in one semiconductor integrated circuit. By doing so, the number of circuit components constituting the color display device can be reduced. Further, the specific configuration of the memory control circuit that causes the two line memories to alternately perform the write / read operation can adopt various embodiments. This can be applied to those using various color display panels having a matrix configuration, in addition to those using a color liquid crystal display panel. The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows. That is, the first and second line memories for storing color display data corresponding to one line of the color display panel are provided, and the first and second line memories are alternately subjected to writing and reading control, and The color display data read from the first or second line memory is divided and supplied in parallel corresponding to the X driving circuit which is divided. In this configuration, since only the data for two lines is stored as the storage circuit for storing the color display data, the storage capacity of the storage circuit required for the display operation can be reduced. Also,
Since the X drive circuit can be divided and the color display data stored in the line memory can be input in parallel correspondingly, the transfer rate in the X drive circuit can be equivalently increased, so that the frame frequency can be increased and flicker can be prevented. It is possible to obtain a high quality display screen.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of a color display device according to the present invention. FIG. 2 is a timing chart for explaining a display operation. FIG. 3 is a configuration diagram showing one embodiment of a color liquid crystal display panel. FIG. 4 is a timing chart for explaining write parallel data to a line memory. FIG. 5 is a memory map diagram showing one embodiment of a line memory. FIG. 6 is a timing chart for explaining parallel data read from a line memory. [Description of Signs] SPC: serial / parallel conversion circuit, MPX1: multiplexer (write memory selection circuit), MPX2: multiplexer (read memory selection circuit), LM1, LM2: line memory, RWC: read / write control circuit, TC ... Timing control circuit, LCD: color liquid crystal display panel, WC: write control circuit, RC: read control circuit, CSEL: color selection circuit, DDC: divided data control circuit, XDVL, XDVR: X drive circuit, YDV: Y drive circuit .

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[Procedure Amendment] [Date of submission] July 17, 1995 [Procedure Amendment 1] [Document name for amendment] Specification [Item name for amendment] Claims [Amendment method] Change [Amendment content] [Patent] Claims: 1. A liquid crystal display panel having a signal line of M dots, and forming a display area of M dots of the liquid crystal display panel,
N data driving circuits for supplying an image signal to each of the signal lines of N (N is a natural number of 2 or more) partial areas each having a continuous display dot, and display data to be displayed on the liquid crystal display panel A memory for storing at least M dots, and the display data input as continuous display data is written in the storage circuit, and the M stored in the storage circuit is stored in the storage circuit.
Of the display data for dots, a memory control circuit for reading, from the storage circuit, N sets of display data consisting of a predetermined unit to be displayed in each of the N partial areas, in a predetermined order, A liquid crystal display device, comprising: a divided data control circuit that sequentially holds the read N sets of display data and outputs the N sets of display data in parallel to the N data driving circuits. 2. The memory control circuit includes two memory circuits, the memory control circuit includes a write switch circuit that supplies write data to one of the two memory circuits, and a read data that is read from one of the two memory circuits. A read-out switching circuit for selecting, during the operation of writing the display data to one of the two storage circuits, the write-in switching circuit and the read-out switching circuit so that the display data reading operation is performed from the other storage circuit. 2. The liquid crystal display device according to claim 1, wherein 3. The liquid crystal according to claim 1, wherein the storage circuit stores, at the same address, each of a plurality of color display data each supplied in a plurality of bits. Display device. 4. The storage circuit outputs the color display data of the plurality of colors stored at the same address simultaneously at the same address, and the memory control circuit reads the color display data of the plurality of colors simultaneously read from the storage circuit. 4. The liquid crystal display device according to claim 3, further comprising a color selection circuit that selects specific color display data from the display data and supplies the selected data to the divided data control circuit. 5. The liquid crystal display device according to claim 4, wherein the liquid crystal display panel is an active matrix liquid crystal display panel provided with color filters in a horizontal stripe shape. 6. The input display data is composed of continuous display data for M dots and non-display data added before and after the display data, and the memory control circuit includes the continuous display data included in the input display data. The display data for M dots corresponding to the display data and the non-display data corresponding to the display timing signal for distinguishing the display data from each other are written in the storage means. Item 5. The liquid crystal display device according to any one of items 5. [Procedure Amendment 2] [Name of Document to be Amended] Specification [Name of Item to Amend] [Correction Method] Change [Details of Amendment] [Means for Solving the Problems] According to the invention, a liquid crystal display panel having a signal line of M dots and N (N number of display dots which form a display region of the M dot of the liquid crystal display panel and which are continuous with each other (N
N data drive circuits for supplying an image signal to each of the signal lines in each of the partial regions of 2 or more natural numbers), a storage circuit for storing at least M dots of display data to be displayed on the liquid crystal display panel, The display data input as continuous display data is written to the storage circuit, and the display data for M dots stored in the storage circuit is to be displayed in each of the N partial regions. A memory control circuit for reading out N sets of display data composed of the following units from the storage circuit in a predetermined order, and sequentially holding the read out sets of N sets of display data, in parallel with the N data drive circuits. And a divided data control circuit for outputting the divided data control circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kazuhiro Fujisawa             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Ceremony Hitachi Microelectronics             Device Development Laboratory (72) Inventor Kaoru Hasegawa             Hitachi, Ltd. 3300 Hayano, Mobara-shi, Chiba             Mobara Factory (72) Inventor Shinzo Matsumoto             Hitachi, Ltd. 3300 Hayano, Mobara-shi, Chiba             Mobara Factory (72) Inventor Mitsuhisa Fujita             Hitachi, Ltd. 3300 Hayano, Mobara-shi, Chiba             Mobara Factory

Claims (1)

[Claims] 1. A liquid crystal display panel, and one horizontal line of the liquid crystal display panel are divided into N (N is a natural number of 2 or more) areas and N X drive circuits for supplying image signals to the respective areas. A storage circuit capable of sequentially reading at least one line of display data to be displayed on the liquid crystal display panel, horizontally addressing and storing the display data, and simultaneously reading out at least one line of display data at the same address; A memory control circuit that supplies a read address so that the display data stored in the storage circuit, which is divided into at least one line of N areas, is sequentially read from each area by a predetermined unit; A liquid crystal display device comprising: a divided data control circuit that sequentially latches display data and outputs N sets of display data in parallel to N X drive circuits. 2. The liquid crystal display device according to claim 1, wherein the input display data is continuously provided with display data for one line, and non-display data is added before and after the display data for one line. A liquid crystal display device, wherein only data to be displayed is written in the storage means.