JP2007193351A - Liquid crystal display device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device having high image quality, and to provide electronic equipment using the liquid crystal display device. <P>SOLUTION: The liquid crystal display device comprises: a plurality of source signal lines, a plurality of gate signal lines and a transistor on the upside of a substrate; an insulating film on the upside of the transistor; an organic resin film on the upside of the insulation film; and a pixel electrode on the upside of the organic resin film, wherein the insulation film includes any of silicon nitride, silicon oxide and silicon oxide-nitride, the pixel electrode is electrically connected to one of the plurality of source signal lines via the transistor, a gate of the transistor is electrically connected to one of the plurality of gate signal lines, a first image signal is supplied to the pixel electrode via one of the plurality of source signal lines during a first frame period, and a second image signal of polarity opposite to the polarity of the first image signal is supplied to the pixel electrode via one of the source signal lines during a frame period next to the first frame period, wherein the frame frequency is at least 120 Hz. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a driving method suitable for a display device in which pixels are arranged in a matrix using a display medium such as liquid crystal. The present invention also relates to a display device that performs display using the driving method. In particular, the present invention relates to a direct-view type active matrix liquid crystal panel (liquid crystal panel).

  In recent years, a technique for manufacturing a semiconductor device in which a semiconductor thin film is formed over an insulating substrate, for example, a thin film transistor (TFT) has been rapidly developed. This is because the demand for liquid crystal panels (typically active matrix liquid crystal panels) has increased.

  An active matrix type liquid crystal panel displays an image by controlling charges entering and exiting dozens to millions of pixels arranged in a matrix by a switching element of the pixels.

  Note that a pixel in this specification mainly includes a switching element, a pixel electrode connected to the switching element, a liquid crystal, and a counter electrode provided to face the pixel electrode through the liquid crystal. It refers to the element that is being used.

  A typical example of the display operation of the active matrix liquid crystal panel will be briefly described below with reference to FIG.

The source signal line drive circuit 103 and the source signal lines S1 to S6 are connected.
Further, the gate signal line driving circuit 104 and the gate signal lines G1 to G5 are connected. A plurality of pixels 106 are provided in a portion surrounded by the source signal lines S1 to S6 and the gate signal lines G1 to G5. The pixel 106 is provided with a switching element 101 and a pixel electrode 102. Note that the number of source signal lines and gate signal lines is not limited to this value (FIG. 19A). Note that FIG. 19B is a diagram (display pattern) illustrating positions of a plurality of pixels 106 included in the pixel portion 105.

  A video signal is applied to the source signal line S1 in accordance with a signal from a shift register circuit or the like (not shown) in the source signal line driver circuit 103. Further, a selection signal is applied from the gate signal line driver circuit 104 to the gate signal line G1, and the switching element of the pixel (1, 1) in the portion where the gate signal line G1 and the source signal line S1 intersect is turned on. . The video signal of the source signal line S1 is applied to the pixel electrode of the pixel (1, 1). The liquid crystal is driven by the potential of the applied video signal to control the amount of transmitted light, and a part of the image (image corresponding to the pixel (1, 1)) is displayed on the pixel (1, 1).

  Next, while the state in which the image is displayed on the pixel (1, 1) is held by a holding capacitor (not shown) or the like, the shift register circuit or the like in the source signal line driver circuit 103 (shown) is held at the next moment. Video signal is input to the source signal line S2. The selection signal is still applied to the gate signal line G1 from the gate signal line driving circuit 104, and the switching element of the pixel (1, 2) at the portion where the gate signal line G1 and the source signal line S2 intersect is turned on. To. Then, the potential of the video signal of the source signal line S2 is applied to the pixel electrode of the pixel (1, 2). The liquid crystal is driven by the potential of the applied video signal, and the amount of transmitted light is controlled. Similarly to the pixel (1, 1), the pixel (1, 2) has a part of the image (pixel (1, 2). (Corresponding image) is displayed.

  Such display operation is sequentially performed to the pixels (1, 1) (1, 2) (1, 3) (1, 4) (1, 5) (1, 6) connected to the gate signal line G1. Display part of the image one after another. During this time, the selection signal continues to be applied to the gate signal line G1.

  When the video signal is applied to all the pixels connected to the gate signal line G1, the selection signal is not applied to the gate signal line G1, and subsequently, the selection signal is applied only to the gate signal line G2. Then, a part of the image is displayed one after another on the pixels (2, 1) (2, 2) (2, 3) (2, 4) (2, 5) (2, 6) connected to the gate signal line G2. To do. During this time, the selection signal continues to be applied to the gate signal line G2. By performing such a display operation on all the gate signal lines, one screen (frame) is displayed in the display area. This period is called one frame period. (Fig. 19B)

  Finally, until a part of the image is displayed on the pixels (4, 6) to which the video signal is applied, all the other pixels hold the state in which the image is displayed with a holding capacitor (not shown) or the like. Yes.

  By sequentially repeating these display operations, an image is displayed on the pixel portion 105.

  In a liquid crystal panel using a TFT or the like as a normal switching element, the polarity of the potential of a signal applied to each pixel is inverted (AC drive) with reference to a common potential in order to prevent deterioration of the liquid crystal material.

  One of the AC driving methods is source line inversion driving. FIG. 20A shows a pixel polarity pattern in source line inversion driving. The polarity pattern shown in FIG. 20 corresponds to the display pattern shown in FIG.

  In the diagrams showing the polarity patterns in this specification (FIGS. 20, 22, and 23), “+” is used when the potential of the video signal applied to the pixel is positive with respect to the common potential. In the figure, when it is negative, it is indicated by “−”.

  In addition, the scanning method includes interlaced scanning that scans in two times (two fields) by skipping the gate signal lines of one screen (one frame) one by one, and without skipping the gate signal lines. Although there is non-interlaced scanning that sequentially scans, an example using non-interlaced scanning will be mainly described here.

  As shown in FIG. 20A, the source line inversion drive is characterized in that video signals having the same polarity are applied to all pixels connected to the same source signal line in any one frame period. That is, a video signal having a reverse polarity is applied between pixels connected to adjacent source signal lines. In the next one frame period, a video signal having a polarity opposite to that of the polarity pattern 1 displayed in the immediately preceding one frame period is applied to each pixel, and the polarity pattern 2 is displayed.

  Another AC driving method is gate line inversion driving. A polarity pattern of the gate line inversion drive is shown in FIG.

  As shown in FIG. 20B, video signals having the same polarity are applied to all the pixels connected to the same gate signal line in any one frame period, and connected to adjacent gate signal lines. That is, a video signal having a reverse polarity is applied between the pixels. In the next one frame period, a video signal having a polarity opposite to that of the polarity pattern 3 displayed in the immediately preceding one frame period is applied to each pixel, and the polarity pattern 4 is displayed.

  That is, as in the conventional source line inversion driving method, two types of polarity patterns (polarity pattern 3 and polarity pattern 4) are repeatedly displayed.

  In recent years, liquid crystal panels are required to be thin and light, and at the same time, high definition, high image quality, and high brightness are also required.

  In order to reduce the thickness and weight of the liquid crystal panel, it is necessary to reduce the substrate size of the liquid crystal panel. In order to reduce the substrate size and not deteriorate the image quality, the pixel pitch must inevitably be shortened to reduce the area of the pixel portion.

  FIG. 21 shows an enlarged view of a pixel of the liquid crystal panel. A pixel TFT (switching element) 15 having a source signal line 12a, a gate signal line 12b, a semiconductor layer 13 and a gate electrode 14 which is a part of the gate signal line 12b, and a pixel electrode 16 are as shown in FIG. Is provided. A black matrix 17 is provided on the source signal line 12a, the gate signal line 12b, and the pixel TFT 15 so as to cover a region that does not need to transmit visible light. The black matrix (BM) refers to a light-shielding film provided above a wiring (source signal line 12a, gate signal line 12b) or the pixel TFT 15 that does not need to transmit visible light.

  The pixel pitch L indicates the shorter one between the distance between the source signal lines 12a facing each other across the pixel 11 and the distance between the gate signal lines 12b facing each other. When the distance between both signal lines is the same, the distance is set as the pixel pitch L.

  When the pixel pitch is shortened, the distance between the pixel electrodes 16 of adjacent pixels is shortened. For this reason, when source line inversion driving and gate line inversion driving are performed, stripes called disclination lines occur between adjacent pixels to which opposite polarities are applied, and the brightness of the entire display screen tends to be reduced. .

  In this specification, liquid crystal alignment state disturbance (disclination) caused by a potential difference generated between a pixel to which a positive polarity video signal is applied and a pixel to which a negative polarity video signal is applied. The display failure due to (a loss of light in the case of normally white, light leakage in the case of normally black) is called a disclination line.

  The potential difference generated between adjacent pixels is generated by the lines of electric force shown in FIG. In FIG. 22A, the effective electric field (positive or negative) in the direction perpendicular to the paper surface applied to the pixel electrodes A and B of two adjacent pixels is between the two pixel electrodes A and B. A top view of a state diagram of the generated lines of electric force is shown, and FIG. 22B shows a cross-sectional view thereof. However, for convenience, FIG. 22A shows only electric lines of force generated between the pixel electrodes A and B generated in the horizontal direction, and FIG. 22B shows liquid crystal molecules whose alignment is controlled in the vertical direction. The phase diagram of the electric lines of force immediately before reacting to the application of is shown.

  The disclination pattern corresponding to FIG. 20A is shown in FIG. In FIG. 22C, although the disclination line is formed at a fixed position and the polarities of the video signals applied to the pixels are different, the disclination pattern 1 and the disclination pattern are practically different. 2 are identical. The disclination line as shown in FIG. 22C can also be seen in the gate line inversion drive. In the case of gate line inversion driving, the disclination line appears between the pixels in parallel with the direction of the gate signal line.

  In addition, although not shown in the drawing, as another AC driving method, a method (dot inversion driving) in which the polarity of a video signal applied to a pixel is inverted between all adjacent pixels has been proposed. Since the polarity of the dot inversion drive is different from that of the adjacent pixel, the influence of the potential difference generated between the adjacent pixels is large. In particular, when the pixel pitch is shortened, the discernment greatly affects the display.

  The shorter the pixel pitch, the shorter the distance between adjacent pixel electrodes. The disclination was particularly remarkable when it was 20 μm or less.

  Therefore, instead of source line inversion driving, gate line inversion driving, and dot inversion driving, disclination is suppressed by using frame inversion driving that inverts the polarity of the video signal applied to all pixels every frame period. It is possible.

  FIG. 23 shows the polarity pattern of each pixel in frame inversion driving. The feature of the frame inversion drive is that a video signal having the same polarity is applied to all pixels within one arbitrary frame period (polarity pattern 5), and an image applied to all pixels in the next one frame period. It is a point (polarity pattern 6) displayed by reversing the polarity of the signal. That is, when attention is paid only to the polarity pattern, the driving method is such that two types of polarity patterns (polar pattern 5 and polarity pattern 6) are repeatedly displayed. For this reason, in the same frame period, the polarities of the video signals applied to adjacent pixels are the same, and the occurrence of disclination is suppressed.

  However, the problem with frame inversion drive is that the screen brightness is slightly different between the display when the polarity of the video signal is positive and the display when it is negative. It is. The cause of this flickering will be described in detail below.

  FIG. 24 is a timing chart of the video signal applied to the source signal lines S1 to Sn, the selection signal applied to the gate signal line G1, and the potential of the pixel electrode (1, 1) included in the pixel (1, 1). Indicated. A period during which the selection signal is applied to the gate signal line G1 is one line period, and a period from when the selection signal is applied to all the gate signal lines until one image is displayed is one frame period.

  When a video signal and a selection signal are applied to the source signal line S1 and the gate signal line G1, respectively, the pixel (1, 1) provided at the intersection of the source signal line S1 and the gate signal line G1 is applied. The potential of the positive polarity video signal selected by the selection signal is applied. Ideally, this potential is held for one frame period by a holding capacitor or the like.

  However, actually, when one line period ends, the selection signal is no longer applied to the gate signal line G1, the potential of the gate signal line G1 changes, and the potential of the pixel electrode also changes. The gate signal line is connected to the gate electrode of the pixel TFT which is a pixel switching element. The source signal line is connected to the source or drain region of the pixel TFT, and the pixel electrode is connected to the one not connected to the source signal line of the source or drain region. A small capacitance is formed between the gate electrode and the pixel electrode. When the potential of the gate signal line G1 changes, the potential of the pixel electrode also changes by ΔV accordingly. In this case, the potential of the pixel electrode changes in the negative direction. In the timing chart shown in FIG. 24, the actual potential of the pixel electrode is indicated by a solid line, and the potential of the pixel electrode when it is assumed that there is no capacitance formed between the gate electrode and the pixel electrode is indicated by a dotted line.

  Next, in the second frame period, a video signal having a negative polarity opposite to that in the first frame period is applied to the pixel electrode included in the pixel (1, 1). When one line period of the second frame period ends, the selection signal is not applied to the gate signal line G1, and the potential of the gate signal line G1 changes. Then, the potential of the pixel electrode is changed by ΔV in the negative direction accordingly.

  That is, if the potential difference V1 between the potential of the pixel electrode after the end of one line period in the first frame period and the common potential is V1, and the potential difference V2 between the pixel electrode after the end of one line period in the second frame period and the common potential, There is a difference of 2 × ΔV between V1 and the potential difference V2. For this reason, the brightness of the screen differs between the first frame period and the second frame period.

  Similarly, in the case of source line inversion driving, gate line inversion driving, and dot inversion driving, the brightness is different between a pixel to which a positive polarity video signal is applied and a pixel to which a negative polarity video signal is applied. However, since pixels having different brightness are adjacent to each other, it is difficult for an observer to visually recognize the pixels. However, in the case of frame inversion driving, the polarities of adjacent pixels are all the same, and the polarity is inverted in one frame period in a frequency range (about 30 Hz) that can be visually recognized by the human eye. It is visually recognized by the observer as a flicker that the display at the time of the image is slightly different from the display when the polarity of the video signal is negative. In particular, the flicker was remarkably confirmed in the halftone display.

  As described above, in the source line inversion driving and the gate line inversion driving, the polarity pattern 1 and the polarity pattern 2 are repeatedly displayed as shown in FIG. 20A and FIG. Since the disclination line is continuously formed at a fixed position between the pixels, the brightness of the screen has been reduced. In addition, the same was true for dot inversion driving.

  In the frame inversion drive, disclination does not occur, but flickering occurs.

  Therefore, the present invention is intended to solve such various problems.

  That is, an object of the present invention is to provide a liquid crystal panel with a short pixel pitch and a driving method thereof that can provide a bright display without flickering.

  According to the present invention, a first substrate having a plurality of gate signal lines, a plurality of source signal lines, and a plurality of pixel electrodes provided at each intersection of the gate signal lines and the source signal lines; And a second substrate having a color filter including one color, wherein a first video signal having the same polarity is applied to the plurality of pixel electrodes through the plurality of source signal lines in a first frame period. Applied to the plurality of pixel electrodes through the plurality of source signal lines in the second frame period subsequent to the first frame period, the second polarity having a polarity opposite to that of the first video signal. A video signal is applied to the display device.

  According to the present invention, a first substrate having a plurality of gate signal lines, a plurality of source signal lines, and a plurality of pixel electrodes provided at each intersection of the gate signal lines and the source signal lines; And a second substrate having a color filter including one color, wherein the video signals having the same polarity are applied to the plurality of pixel electrodes through the plurality of source signal lines, and the polarity of the video signal There is provided a display device characterized in that changes every frame period.

  According to the first aspect of the present invention, a plurality of gate signal lines, a plurality of source signal lines, and a plurality of switching elements and a plurality of pixel electrodes provided at each intersection of the gate signal lines and the source signal lines are provided. And a second substrate having a color filter including three colors, video signals having the same polarity are applied to the plurality of switching elements through the plurality of source signal lines, A selection signal for selecting the video signal is applied to the plurality of switching elements through the plurality of gate signal lines, and an image selected by the selection signal is applied to the plurality of pixel electrodes through the plurality of switching elements. A display device is provided in which a signal is applied and the polarity of the video signal changes every frame period.

  An interval between the plurality of gate signal lines or the plurality of source signal lines may be 20 μm or less.

  The length of the first frame period and the second frame period may be 8.3 msec or less.

  The length of the one frame period may be 8.3 msec or less.

  The plurality of switching elements each include a gate electrode, a semiconductor layer having a source region, a drain region, and a channel formation region, and an insulating film provided between the gate electrode and the semiconductor layer, The gate signal line may be connected to the gate electrode, and the source signal line may be connected to the source region or the drain region.

  A liquid crystal may be provided between the first substrate and the second substrate.

  Each of the plurality of pixel electrodes may correspond to one of three colors included in the color filter.

  A goggle type display having one display device is provided.

  A goggle type display having two display devices is provided.

  A mobile computer having one display device is provided.

  A notebook personal computer having one display device is provided.

  A video camera having one display device is provided.

  A DVD player having one display device is provided.

  A game machine having one display device is provided.

  In the present invention, the frame frequency is set to 120 Hz or more, and driving is performed by the frame inversion driving method. Each pixel corresponds to one of the color filters R, G, and B provided on the TFT substrate side. With the above configuration, in a display device with a direct view pixel pitch as short as 20 μm or less, neither disclination nor flicker was observed, and a bright display with good contrast could be obtained.

  The configuration of the present invention will be described below in comparison with the conventional configuration. Although an example using non-interlaced scanning will be described here, it is needless to say that the present invention is not limited to non-interlaced scanning and can be applied to other scanning methods such as interless scanning. .

  FIG. 2 shows the configuration of the active matrix liquid crystal panel of the present invention. The source signal line driver circuit 1801 and the gate signal line driver circuit 1802 are generally collectively referred to as a driver circuit. In recent years, this driver circuit may be formed over the same substrate as the pixel portion 1808 provided with pixels in a matrix.

  In the pixel portion 1808, the source signal lines 1803 (S1 to Sn) connected to the source signal line driver circuit 1801 and the gate signal lines 1804 (G1 to Gn) connected to the gate signal line driver circuit 1802 intersect. is doing. In a region surrounded by the source signal line 1803 and the gate signal line 1804, a thin film transistor (pixel TFT) 1805 of the pixel, a liquid crystal cell 1806 in which liquid crystal is sandwiched between the counter electrode and the pixel electrode, and a storage capacitor 1807 are provided. Is provided.

  A video signal sampled by the timing signal output from the source signal line driver circuit 1801 is applied to the source signal line 1803.

  The pixel TFT 1805 turns on the pixel TFT 1805 by a selection signal input from the gate signal line driver circuit 1802 via the gate signal line 1804. When the pixel TFT 1805 is turned on, a video signal applied to the source signal line 1803 is applied to the pixel electrode of the liquid crystal cell 1806.

  In the liquid crystal panel shown in FIG. 2, a video signal applied to the source signal lines S1, S2,..., Sn, a selection signal applied to the gate signal line G1, and the source signal line S1 and the gate signal line G1. FIG. 1 shows a timing chart of the potential of the pixel electrode included in the intersecting pixel (1, 1). As a conventional example, the potential of the pixel electrode included in the pixel (1, 1) of the liquid crystal panel driven at a frame frequency of 60 Hz is also shown. A period in which the selection signal is applied to the gate signal line G1 is one line period, and a period until the selection signal is completely applied to all the gate signal lines is one frame period.

  In the present invention, one frame period is set to 8.3 msec or less. That is, it is desirable that the frame frequency is 120 Hz or more. In this embodiment, the frame frequency is 120 Hz.

  When a video signal and a selection signal are applied to the source signal line S1 and the gate signal line G1, respectively, the pixel (1, 1) provided at the intersection of the source signal line S1 and the gate signal line G1 is applied. The potential of the positive polarity video signal selected by the selection signal is applied. Ideally, this potential is held for one frame period by a holding capacitor or the like.

  However, in practice, when one line period ends, the selection signal is no longer applied to the gate signal line G1, and the potential of the pixel electrode changes simultaneously with the change of the potential of the gate signal line G1. The gate signal line is connected to the gate electrode of the pixel TFT which is a pixel switching element. The source signal line is connected to the source or drain region of the pixel TFT, and the pixel electrode is connected to the one not connected to the source signal line of the source or drain region. A small capacitance is formed between the gate electrode and the pixel electrode. When the potential of the gate signal line G1 changes, the potential of the pixel electrode also changes by ΔV accordingly. In this case, the potential of the pixel electrode changes in the negative direction. In the timing chart shown in FIG. 1, the actual potential of the pixel electrode is indicated by a solid line, and the potential of the pixel electrode when there is no capacitance formed between the gate electrode and the pixel electrode is indicated by a dotted line.

  Next, in the second frame period, a video signal having a negative polarity opposite to that in the first frame period is applied to the pixel electrode included in the pixel (1, 1). When one line period of the second frame period ends, the selection signal is not applied to the gate signal line G1, and the potential of the gate signal line G1 changes. Then, the potential of the pixel electrode is changed by ΔV in the negative direction accordingly.

  That is, if the potential difference V1 between the potential of the pixel electrode after the end of one line period in the first frame period and the common potential is V1, and the potential difference V2 between the pixel electrode after the end of one line period in the second frame period and the common potential, There is a difference of 2 × ΔV between V1 and the potential difference V2. For this reason, the brightness of the screen differs between the first frame period and the second frame period.

  However, by setting the frame frequency to 120 Hz or more, the difference in screen brightness between the first frame period and the second frame period cannot be visually recognized by human eyes. Therefore, since the polarity is reversed every frame period, even if the display when the polarity of the video signal is positive and the display when the polarity of the video signal is negative are slightly different, the flicker is visually recognized by the observer. Nothing will happen.

  As described above, in the present invention, a direct-view type liquid crystal panel is driven by using the frame inversion driving method, and the frame frequency is set to 120 Hz or higher at a higher speed than before, so that the direct-view type pixel pitch is as short as 20 μm or less. In the apparatus, neither disclination nor flicker was observed, and a bright display with good contrast could be obtained.

  Embodiments of the present invention will be described with reference to FIGS.

  The pixel arrangement and the color filter arrangement according to the present invention will be described with reference to FIG. In the present invention, the color filter is provided on the TFT substrate side. FIG. 3A illustrates a case where the pixel arrangement of the liquid crystal panel is a delta arrangement. Each pixel corresponds to each of the three colors R (red), G (green), and B (blue). One pixel is composed of three pixels corresponding to the adjacent R (red), G (green), and B (blue).

  FIG. 3B illustrates a case where the pixel array of the liquid crystal panel is a stripe array. Each pixel corresponds to one of the three colors R (red), G (green), and B (blue). One pixel is composed of three pixels corresponding to the adjacent R (red), G (green), and B (blue).

  In this embodiment, an example of a driver circuit used in the present invention will be described.

  FIG. 4 shows an example of a source signal line driver circuit which is one of the driver circuits of the liquid crystal panel of the present invention. Input signal input from the outside of the source signal line driver circuit, in this case, a signal (S-CLb) inverted with respect to the common potential of the source clock signal (S-CL) and the source clock signal (S-CL) Is input to the source signal line driver circuit.

  The source clock signal (S-CL) input to the source signal line driver circuit is input to the source shift register circuit 401. The source shift register circuit 401 operates in response to the input source clock signal (S-CL) and the source start pulse signal (S-SP) input to the source shift register circuit at the same time for sampling the video signal. Are sequentially generated.

  The timing signal is input to the source level shift circuit 402 and its voltage amplitude level is raised. Here, in this specification, the voltage amplitude level means the absolute value of the difference (potential difference) between the highest potential and the lowest potential of the signal, and increasing (raising) the voltage amplitude level increases the potential difference. This means that a lower voltage amplitude level means a smaller potential difference.

  The timing signal whose voltage amplitude level is increased is input to the sampling circuit 403 from the video signal line 404, and the sampling circuit 403 performs an operation of sampling the video signal based on the input timing signal. The sampled video signal is sequentially applied to the corresponding source signal lines S1 and S2.

  Next, FIG. 5 shows a circuit diagram of the gate signal line driving circuit of this embodiment. A signal (G-CLb) inverted from the common potential of the gate clock signal (G-CL) and the gate clock signal (G-CL) is input to the gate signal line drive circuit from the outside of the gate signal line drive circuit. The

  The gate clock signal (G-CL) input to the gate signal line driver circuit is input to the gate shift register circuit 501.

  Based on the gate clock signal (G-CL) input to the gate shift register circuit 501, the gate shift register circuit 501 receives the gate start pulse signal (G-SP) and simultaneously inputs the gate shift register circuit 501. The circuit 501 operates to sequentially generate selection signals for operating all the pixel TFTs connected to the gate signal line. The generated selection signal is input to the gate level shift circuit 502.

  The voltage level of the selection signal input to the gate level shift circuit 502 is raised by the gate level shift circuit 502. This selection signal needs to be raised to a voltage amplitude level necessary for reliably operating all the pixel TFTs. The selection signal with the increased voltage amplitude level is input to the gate signal lines G0, G1, and G2, and the pixel TFT operates to apply the video signal to the liquid crystal. An example of a circuit diagram of a shift register circuit (source shift register circuit 401, gate shift register circuit 501) used for each driver circuit is shown in FIG.

  FIG. 6B shows an equivalent circuit diagram of the level shift circuit (source level shift circuit 402, gate level shift circuit 502) used for each driver circuit. In means that a signal is input, and inb means that an inverted signal of in is input. VDD indicates a positive voltage. The level shift circuit is designed so that a signal obtained by increasing the voltage of the signal input to in and inverting it is output from outb. That is, when Hi is input to in, a signal from outb to Lo is output, and when Lo is input, a signal from Hi to output is output.

  In this embodiment, the case where the TFT substrate has a digital drive circuit will be described with reference to FIG.

  In the display of this embodiment, a source signal line driver circuit A301, a source signal line driver circuit B302, a gate signal line driver circuit 303, a digital video data division circuit 305, and a plurality of pixel TFTs are provided in a matrix form on a TFT substrate. The pixel portion 304 is provided. The source signal line driver circuit B302 has the same configuration as the source signal line driver circuit A301.

  The source signal line driver circuit 301 and the gate signal line driver circuit 303 drive a plurality of pixel TFTs provided in the pixel portion 304. Various signals are input to the pixel portion 304 in the source signal line driver circuit 301 and the gate signal line driver circuit 303 from the outside through the FPC terminal.

  The source signal line driver circuit A301 includes a source signal line side shift register circuit (240 stage × 2 shift register circuit) 301-1, a latch circuit 1 (960 × 8 digital latch circuit) 301-2, and a latch circuit 2 (960 × 8 digital latch circuit) 301-3, selector circuit 1 (240 selector circuit) 301-4, D / A converter circuit (240 DAC) 301-5, selector circuit 2 (240 selector circuit) 301-6 is doing. In addition, a buffer circuit and a level shift circuit (both not shown) may be included. For convenience of explanation, the D / A conversion circuit 301-5 includes a level shift circuit.

  The gate signal line driver circuit 303 includes a shift register circuit, a buffer circuit, a level shift circuit, and the like (all not shown).

  The pixel unit 304 has (640 × RGB) × 1080 (horizontal × vertical) pixels. A pixel TFT is disposed in each pixel. A source signal line is electrically connected to the source region of each pixel TFT, and a gate signal line is electrically connected to the gate electrode. A pixel electrode is electrically connected to the drain region of each pixel TFT. Each pixel TFT controls application of a video signal (gradation voltage) to a pixel electrode electrically connected to each pixel TFT. A video signal (gradation voltage) is applied to each pixel electrode, and a voltage is applied to the liquid crystal sandwiched between each pixel electrode and the counter electrode to drive the liquid crystal.

  Here, the operation and signal flow of the TFT substrate of this embodiment will be described.

  First, the operation of the source signal line driver circuit A301 will be described. Note that the operation of the source signal line driver circuit B302 may be referred to for the operation of the source signal line driver circuit A301.

  A clock signal (CK) and a start pulse (SP) are input to the source signal line side shift register circuit 301-1. The shift register circuit sequentially generates timing signals based on the clock signal (CK) and the start pulse (SP), and sequentially applies the timing signals to subsequent circuits through a buffer circuit or the like.

  The timing signal from the source signal line side shift register circuit 301-1 is buffered by a buffer circuit or the like. Since many circuits or elements are connected to the source signal line to which the timing signal is applied, the load capacitance (parasitic capacitance) is large. This buffer circuit is formed in order to prevent “dullness” of the rise of the timing signal caused by the large load capacity.

  The timing signal buffered by the buffer circuit is applied to the latch circuit 1 (301-2). The latch circuit 1 (301-2) has 960 stages of latch circuits for processing 8-bit digital video data. When the timing signal is input, the latch circuit 1 (301-2) sequentially captures and holds 8-bit digital video data applied from the digital video data dividing circuit 305.

  The time until the digital video data is completely written in the latch circuit in all the stages of the latch circuit 1 (301-2) is called a line period. That is, the writing of the digital video data to the latch circuit of the rightmost stage is completed from the time when the writing of the digital video data to the latch circuit of the leftmost stage in the latch circuit 1 (301-2) is started. The time interval until the point in time is the line period. Actually, a period obtained by adding a horizontal blanking period to the line period may be called a line period.

  After the end of one line period, a latch signal is applied to the latch circuit 2 (301-3) in accordance with the operation timing of the source signal line side shift register circuit 301-1. At this moment, the digital video data written and held in the latch circuit 1 (301-2) is sent all at once to the latch circuit 2 (301-3), and latches of all stages of the latch circuit 2 (301-3) are performed. It is written and held in the circuit.

  The latch circuit 1 (301-2) that has finished sending the digital video data to the latch circuit 2 (301-3) again receives the digital video data dividing circuit based on the timing signal of the source signal line side shift register circuit 301-1. The digital video data applied from is sequentially written.

  During this second line period, the digital video data written and held in the latch circuit 2 (301-3) is sequentially selected by the selector circuit 1 (301-4), and is subjected to D / A conversion. Applied to the circuit. In this embodiment, in the selector circuit 1 (301-4), one selector circuit corresponds to four source signal lines.

  As the selector circuit, one described in Japanese Patent Application No. 11-167373, which is a patent application by the present applicant, can be used.

  The 8-bit digital video data from the latch circuit 2 (301-3) selected by the selector circuit is applied to the D / A conversion circuit.

  The D / A conversion circuit converts 8-bit digital video data into a video signal (gradation voltage) and sequentially applies it to the source signal line selected by the selector circuit 2 (301-6).

  The video signal applied to the source signal line is applied to the source region of the pixel TFT of the pixel portion connected to the source signal line.

  In the gate signal line driving circuit 303, a timing signal (scanning signal) from the shift register is applied to the buffer circuit and applied to the corresponding gate signal line (gate signal line). A gate electrode of a pixel TFT for one line is connected to the gate signal line, and all the pixel TFTs for one line must be turned on at the same time. Therefore, a buffer circuit having a large current capacity is used. .

  In this manner, the corresponding pixel TFT is switched by the scanning signal from the gate signal line driving circuit 303, and the video signal (grayscale voltage) from the source signal line driving circuit A301 and the source signal line driving circuit B302 is converted into the pixel TFT. To drive the liquid crystal molecules.

  A digital video data dividing circuit (SPC) 305 is a circuit for reducing the frequency of digital video data input from the outside to 1 / x (1 <x). By dividing the digital video data input from the outside, the frequency of the signal necessary for the operation of the driving circuit can be reduced to 1 / x.

  Here, the pixel TFT of the pixel portion and the TFTs of the driving circuits (source signal line driving circuit, gate signal line driving circuit, D / A conversion circuit, digital video data time gradation processing circuit, etc.) provided around the pixel portion are provided. A method for manufacturing the same substrate will be described in detail according to the steps. However, in order to simplify the description, a CMOS circuit, which is a basic circuit such as a shift register circuit, a buffer circuit, and a D / A conversion circuit, and an n-channel TFT are illustrated in the control circuit.

In FIG. 8A, a low alkali glass substrate or a quartz substrate can be used as the substrate (TFT substrate) 6001. In the present invention, an SOI substrate such as smart cut, SIMOX, or ELTRAN may be used. In this example, a low alkali glass substrate was used. In this case, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. A base film 6002 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 6001 where a TFT is formed in order to prevent impurity diffusion from the substrate 6001. For example, a silicon oxynitride film made of SiH ₄ , NH ₃ , and N ₂ O by plasma CVD is formed to a thickness of 100 nm, and a silicon oxynitride film made of SiH ₄ and N ₂ O is laminated to a thickness of 200 nm. To do.

  Next, a semiconductor film 6003a having an amorphous structure with a thickness of 20 to 150 nm (preferably 30 to 80 nm) is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film having a thickness of 55 nm is formed by plasma CVD. As the semiconductor film having an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. Further, since the base film 6002 and the amorphous silicon film 6003a can be formed by the same film formation method, they may be formed continuously. After the formation of the base film, it is possible to prevent contamination of the surface by not exposing it to the air atmosphere, and it is possible to reduce variations in characteristics of TFTs to be manufactured and variations in threshold voltage. (Fig. 8 (A))

  Then, a crystalline silicon film 6003b is formed from the amorphous silicon film 6003a using a known crystallization technique. For example, a laser crystallization method or a thermal crystallization method (solid phase growth method) may be applied. A continuous light excimer laser may be used for laser crystallization. Here, the crystalline silicon film 6003b is formed by a crystallization method using a catalytic element in accordance with the technique disclosed in Japanese Patent Laid-Open No. 7-130552. Prior to the crystallization step, depending on the amount of hydrogen contained in the amorphous silicon film, heat treatment is performed at 400 to 500 ° C. for about 1 hour, and the amount of hydrogen contained is reduced to 5 atom% or less for crystallization. desirable. When the amorphous silicon film is crystallized, the rearrangement of atoms occurs and the film is densified. Therefore, the thickness of the produced crystalline silicon film is larger than the thickness of the initial amorphous silicon film (55 nm in this embodiment). Also decreased by about 1 to 15%. (Fig. 8 (B))

  Then, the crystalline silicon film 6003b is divided into island shapes, and island-shaped semiconductor layers 6004 to 6007 are formed. Thereafter, a mask layer 6008 made of a silicon oxide film having a thickness of 50 to 100 nm is formed by plasma CVD or sputtering. (Fig. 8 (C))

Then, a resist mask 6009 is provided, and p at a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ for the purpose of controlling the threshold voltage over the entire surface of the island-like semiconductor layers 6005 to 6007 forming the n-channel TFT. Boron (B) was added as an impurity element imparting a mold. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of an amorphous silicon film. Although boron (B) is not necessarily added here, the semiconductor layers 6010 to 6012 to which boron (B) is added are preferably formed in order to keep the threshold voltage of the n-channel TFT within a predetermined range. It was good. (Fig. 8 (D))

In order to form the LDD region of the n-channel TFT of the driver circuit, an impurity element imparting n-type conductivity is selectively added to the island-shaped semiconductor layers 6010 and 6011. Therefore, resist masks 6013 to 6016 are formed in advance. As an impurity element imparting n-type conductivity, phosphorus (P) or arsenic (As) may be used. Here, an ion doping method using phosphine (PH ₃ ) is applied to add phosphorus (P). The phosphorus (P) concentration of the formed impurity regions 6017 and 6018 may be in the range of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 6017 to 6019 formed here is expressed as (n ⁻ ). The impurity region 6019 is a semiconductor layer for forming a storage capacitor of the pixel matrix circuit, and phosphorus (P) is added to this region at the same concentration.
(Fig. 9 (A))

Next, the mask layer 6008 is removed with hydrofluoric acid or the like, and a step of activating the impurity element added in FIGS. 8D and 9A is performed. The activation can be performed by a heat treatment at 500 to 600 ° C. for 1 to 4 hours or a laser activation method in a nitrogen atmosphere. Moreover, you may carry out using both together. In this embodiment, a laser activation method is used, a KrF excimer laser beam (wavelength 248 nm) is used to form a linear beam, and an oscillation frequency of 5 to 50 Hz and an energy density of 100 to 500 mJ / cm ² are used. The entire surface of the substrate on which the island-shaped semiconductor layer was formed was processed by scanning with an overlap ratio of 80 to 98%. Note that there are no particular limitations on the irradiation conditions of the laser beam, and the practitioner may make an appropriate decision. Alternatively, activation may be performed using a continuous emission excimer laser.

  Then, the gate insulating film 6020 is formed with an insulating film containing silicon with a thickness of 10 to 150 nm by a plasma CVD method or a sputtering method. For example, a silicon oxynitride film is formed with a thickness of 120 nm. As the gate insulating film, another insulating film containing silicon may be used as a single layer or a stacked structure. (Fig. 9 (B))

  Next, a first conductive layer is formed to form a gate electrode. The first conductive layer may be formed as a single layer, but may have a laminated structure such as two layers or three layers as necessary. In this example, a conductive layer (A) 6021 made of a conductive nitride metal film and a conductive layer (B) 6022 made of a metal film were laminated. The conductive layer (B) 6022 is an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the element as a main component, or an alloy film in which the elements are combined. (Typically, a Mo—W alloy film or a Mo—Ta alloy film). The conductive layer (A) 6021 is a tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN) film, or nitride. It is made of molybdenum (MoN). Alternatively, tungsten silicide, titanium silicide, or molybdenum silicide may be applied to the conductive layer (A) 6021 as an alternative material. In the conductive layer (B) 6022, the concentration of impurities contained in the conductive layer (B) 6022 is preferably reduced in order to reduce the resistance. In particular, the oxygen concentration is preferably 30 ppm or less. For example, tungsten (W) was able to realize a specific resistance value of 20 μΩcm or less by setting the oxygen concentration to 30 ppm or less.

  The conductive layer (A) 6021 may be 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 6022 may be 200 to 400 nm (preferably 250 to 350 nm). In this embodiment, a 30 nm thick tantalum nitride film is used for the conductive layer (A) 6021 and a 350 nm Ta film is used for the conductive layer (B) 6022, both of which are formed by sputtering. In film formation by this sputtering method, if an appropriate amount of Xe or Kr is added to the sputtering gas Ar, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 6021. This improves adhesion and prevents oxidation of the conductive film formed thereon, and at the same time, an alkali metal element contained in a trace amount in the conductive layer (A) 6021 or the conductive layer (B) 6022 is added to the gate insulating film 6020. It can be prevented from spreading. (Figure 9 (C))

  Next, resist masks 6023 to 6027 are formed, and the conductive layers (A) 6021 and (B) 6022 are etched together to form gate electrodes 6028 to 6031 and capacitor wirings 6032. The gate electrodes 6028 to 6031 and the capacitor wiring 6032 are integrally formed of 6028a to 6032a made of a conductive layer (A) and 6028b to 6032b made of a conductive layer (B). At this time, the gate electrodes 6029 and 6030 formed in the driver circuit are formed so as to overlap with part of the impurity regions 6017 and 6018 with the gate insulating film 6020 interposed therebetween. (Figure 9 (D))

Next, in order to form a source region and a drain region of the p-channel TFT of the driver circuit, a step of adding an impurity element imparting p-type is performed. Here, impurity regions are formed in a self-aligning manner using the gate electrode 6028 as a mask. At this time, a region where the n-channel TFT is formed is covered with a resist mask 6033. Then, an impurity region 6034 was formed by an ion doping method using diborane (B ₂ H ₆ ). The boron (B) concentration in this region is set to 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting p-type contained in the impurity region 6034 formed here is expressed as (p ⁺ ). (Fig. 10 (A))

Next, in the n-channel TFT, an impurity region functioning as a source region or a drain region was formed. Resist masks 6035 to 6037 were formed, and an impurity element imparting n-type conductivity was added to form impurity regions 6038 to 6042. This was performed by ion doping using phosphine (PH ₃ ), and the phosphorus (P) concentration in this region was set to 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 6038 to 6042 formed here is expressed as (n ⁺ ). (Fig. 10 (B))

  The impurity regions 6038 to 6042 already contain phosphorus (P) or boron (B) added in the previous step, but phosphorus (P) is added at a sufficiently high concentration, so that The influence of phosphorus (P) or boron (B) added in the previous step may not be considered. Further, since the phosphorus (P) concentration added to the impurity region 6038 is 1/2 to 1/3 of the boron (B) concentration added in FIG. 10A, p-type conductivity is ensured, and TFT characteristics are obtained. It had no effect on.

Then, an impurity adding step for imparting n-type for forming the LDD region of the n-channel TFT of the pixel matrix circuit was performed. Here, an impurity element imparting n-type in a self-aligning manner is added by an ion doping method using the gate electrode 6031 as a mask. The concentration of phosphorus (P) to be added is 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^3, which is based on the concentration of the impurity element added in FIGS. 9A, 10A, and 10B. In addition, by adding at a low concentration, substantially only impurity regions 6043 and 6044 are formed. In this specification, the concentration of the impurity element imparting n-type contained in the impurity regions 6043 and 6044 is represented by (n ⁻ ). (Fig. 10 (C))

  Thereafter, a heat treatment process is performed to activate the impurity element imparting n-type or p-type added at each concentration. This step can be performed by a furnace annealing method, a laser annealing method, or a rapid thermal annealing method (RTA method). Here, the activation process was performed by furnace annealing. The heat treatment is performed at 400 to 800 ° C., typically 500 to 600 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, heat treatment is performed at 550 ° C. for 4 hours. went. Further, in the case where a substrate 6001 having heat resistance such as a quartz substrate is used, heat treatment may be performed at 800 ° C. for 1 hour, and activation of the impurity element, impurity region to which the impurity element is added, and A good junction with the channel formation region could be formed.

  In this heat treatment, the conductive layers (C) 6028c to 6032c are formed to have a thickness of 5 to 80 nm from the surface of the metal films 6028b to 6032b forming the gate electrodes 6028 to 6031 and the capacitor wiring 6032. For example, when the conductive layers (B) 6028b to 6032b are tungsten (W), tungsten nitride (WN) can be formed, and when tantalum (Ta) is used, tantalum nitride (TaN) can be formed. In the present invention, a laminate of a silicon (Si) film, a WN film and a W film, a laminate of a W film and a W film having Si, or a laminate of a W film and Si having a W film and Si A gate electrode may be formed using a W film containing Mo or a Ta film containing Mo. The conductive layers (C) 6028c to 6032c can be formed in the same manner even when the gate electrodes 6028 to 6031 are exposed to a plasma atmosphere containing nitrogen using nitrogen or ammonia. Further, a heat treatment was performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma or hydrogenated plasma) may be performed.

In the case where the island-shaped semiconductor layer was formed from an amorphous silicon film by a crystallization method using a catalytic element, a trace amount of the catalytic element remained in the island-shaped semiconductor layer. Of course, it is possible to complete the TFT even in such a state, but it is more preferable to remove at least the remaining catalyst element from the channel formation region. As one of means for removing the catalyst element, there is a means for utilizing the gettering action by phosphorus (P). The concentration of phosphorus (P) necessary for gettering is approximately the same as that of the impurity region (n ⁺ ) formed in FIG. 10B. The catalytic element could be gettered from the channel formation region of the channel TFT. (Figure 10 (D))

When the activation and hydrogenation steps are completed, a second conductive film to be a gate wiring is formed. This second conductive film includes a conductive layer (D) 6045 mainly composed of aluminum (Al) or copper (Cu), which is a low-resistance material, and titanium (Ti), tantalum (Ta), tungsten (W), A conductive layer (E) 6046 made of molybdenum (Mo) may be used. In this embodiment, an aluminum (Al) film containing 0.1 to 2% by weight of titanium (Ti) is formed as the conductive layer (D) 6045, and a titanium (Ti) film is formed as the conductive layer (E) 6046. The conductive layer (D) 6045 may be 200 to 400 nm (preferably 250 to 350 nm), and the conductive layer (E) 6046 may be 50 to 200 nm (preferably 100 to 150 nm). (FIG. 11 (A)
)

Then, in order to form a gate wiring connected to the gate electrode, the conductive layer (E) 6046 and the conductive layer (D) 6045 were etched to form gate wirings 6047 and 6048 and a capacitor wiring 6049. In the etching process, first, the surface of the conductive layer (E) 6046 is removed from the surface of the conductive layer (E) 6046 to the middle of the conductive layer (D) 6045 by a dry etching method using a mixed gas of SiCl ₄ , Cl ₂ and BCl ₃ . By removing the conductive layer (D) 6045 by wet etching using an etching solution, a gate wiring can be formed while maintaining selective processability with the base. (Fig. 11 (B))

  The first interlayer insulating film 6050 is formed of a silicon oxide film or a silicon oxynitride film with a thickness of 500 to 1500 nm, and then a contact hole reaching the source region or the drain region formed in each island-shaped semiconductor layer is formed. Then, source wirings 6051 to 6054 and drain wirings 6055 to 6058 are formed. Although not shown, in this embodiment, this electrode is a laminated film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film is 150 nm continuously formed by sputtering.

  Next, a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film is formed as the passivation film 6059 with a thickness of 50 to 500 nm (typically 100 to 300 nm). When the hydrogenation treatment was performed in this state, favorable results were obtained with respect to the improvement of TFT characteristics. For example, heat treatment may be performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen, or the same effect can be obtained by using a plasma hydrogenation method. Note that an opening may be formed in the passivation film 6059 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later. (Fig. 11 (C))

  Thereafter, a second interlayer insulating film 6060 made of an organic resin is formed to a thickness of 1.0 to 1.5 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Here, it was formed by baking at 300 ° C. using a type of polyimide that is thermally polymerized after being applied to the substrate. Then, a contact hole reaching the drain wiring 6058 is formed in the second interlayer insulating film 6060, and pixel electrodes 6061 and 6062 are formed. The pixel electrode may be a transparent conductive film when a transmissive liquid crystal panel is used, and a metal film may be used when a reflective liquid crystal panel is used. In this example, an indium tin oxide (ITO) film was formed to a thickness of 100 nm by sputtering in order to obtain a transmissive liquid crystal panel. (Fig. 12)

  In this way, a substrate having the TFT of the driving circuit and the pixel TFT of the pixel portion on the same substrate was completed. A p-channel TFT 6101, a first n-channel TFT 6102, and a second n-channel TFT 6103 are formed in the driver circuit, and a pixel TFT 6104 and a storage capacitor 6105 are formed in the pixel portion. In this specification, such a substrate is called a TFT substrate for convenience.

  A p-channel TFT 6101 of the driver circuit includes a channel formation region 6106, source regions 6107a and 6107b, and drain regions 6108a and 6108b in an island-shaped semiconductor layer 6004. The first n-channel TFT 6102 includes an LDD region 6110 (hereinafter, such an LDD region is referred to as Lov) overlapping a channel formation region 6109 and a gate electrode 6029 on an island-shaped semiconductor layer 6005, a source region 6111, and a drain region 6112. Have. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm. The second n-channel TFT 6103 has a channel formation region 6113, LDD regions 6114 and 6115, a source region 6116, and a drain region 6117 in the island-shaped semiconductor layer 6006. The LDD region is formed with an LDD region that does not overlap the Lov region and the gate electrode 6030 (hereinafter, such LDD region is referred to as Loff), and the length of the Loff region in the channel length direction is 0.3-2. It is 0 μm, preferably 0.5 to 1.5 μm. The pixel TFT 6104 has channel formation regions 6118 and 6119, Loff regions 6120 to 6123, and source or drain regions 6124 to 6126 in an island-shaped semiconductor layer 6007. The length of the Loff region in the channel length direction is 0.5 to 3.0 μm, preferably 1.5 to 2.5 μm. Further, the capacitor wirings 6032 and 6049, an insulating film made of the same material as the gate insulating film 6020, and a semiconductor layer 6127 which is connected to the drain region 6126 of the pixel TFT 6104 and to which an impurity element imparting n-type conductivity is added. 6105 is formed. Although the pixel TFT 6104 has a double gate structure in FIG. 12, it may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

  In this way, a substrate having the driving circuit TFT and the pixel TFT of the pixel portion can be completed on the same substrate. A p-channel TFT 6101, a first n-channel TFT 6102, and a second n-channel TFT 6103 are formed in the driver circuit, and a pixel TFT 6104 and a storage capacitor 6105 are formed in the pixel portion (FIG. 12). In this specification, such a substrate is called a TFT substrate for convenience.

  Next, a process for manufacturing a liquid crystal panel based on the TFT substrate manufactured by the above process will be described.

  An alignment film 6070 is formed on the TFT substrate in the state shown in FIG. In this embodiment, polyimide is used for the alignment film 6070 (FIG. 13A). Next, a counter substrate is prepared. The counter substrate includes a glass substrate 6075, a color filter 6074, a counter electrode 6073 made of a transparent conductive film, and an alignment film 6072. Note that each color of the color filter 6074 corresponds to each pixel in the pixel portion.

  In this embodiment, the alignment film 6070 is a polyimide film in which liquid crystal molecules are aligned parallel to the substrate. Note that after the alignment film is formed, a rubbing process is performed so that the liquid crystal molecules are aligned in parallel with a certain pretilt angle.

Next, the TFT substrate and the counter substrate that have undergone the above-described steps are bonded to each other through a sealing material, a spacer (both not shown), or the like by a known cell assembling step. Thereafter, liquid crystal 6071 is injected between both substrates and completely sealed with a sealant (not shown). Therefore, a reflective liquid crystal panel as shown in FIG. 14 is completed. (Fig. 13B)
)

  As described above, in this embodiment, it is possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel TFT and the drive circuit, and to improve the operation performance and reliability of the semiconductor device. Can do. Further, the gate electrode is formed of a heat-resistant conductive material to facilitate activation of the LDD region, the source region, and the drain region, and the wiring resistance can be sufficiently reduced by forming the gate electrode from a low-resistance material for the gate wiring. Therefore, the present invention can be applied to a display device having a pixel portion (screen size) of 4 inches class or more.

  In this embodiment, an example in which the liquid crystal panel of the present invention is configured using an inverted stagger type TFT is shown.

  Refer to FIG. FIG. 14 shows a cross-sectional view of an inverted staggered N-channel TFT constituting the liquid crystal panel of this embodiment. Although only one N-channel TFT is shown in FIG. 14, it goes without saying that a CMOS circuit can be constituted by a P-channel TFT and an N-channel TFT. It goes without saying that the pixel TFT can be configured with the same configuration.

  Reference numeral 3001 denotes a substrate, which is as described in the fourth embodiment. Reference numeral 3002 denotes a silicon oxide film. Reference numeral 3003 denotes a gate electrode. Reference numeral 3004 denotes a gate insulating film. Reference numerals 3005, 3006, 3007 and 3008 denote active layers made of a polycrystalline silicon film. In the production of this active layer, the same method as the polycrystallization of the amorphous silicon film described in Example 4 was used. Alternatively, a method of crystallizing the amorphous silicon film with laser light (preferably linear laser light or planar laser light) may be used. Note that reference numeral 3005 denotes a source region, 3006 denotes a drain region, 3007 denotes a low concentration impurity region (LDD region), and 3008 denotes a channel formation region. Reference numeral 3009 denotes a channel protective film, and 3010 denotes an interlayer insulating film. Reference numerals 3011 and 3012 denote a source wiring and a drain wiring, respectively.

  Reference is now made to FIG. FIG. 15 illustrates a case where a liquid crystal panel is configured with an inverted stagger type TFT having a configuration different from that illustrated in FIG.

  In FIG. 15, only one N-channel TFT is shown, but it goes without saying that a CMOS circuit can be constituted by the P-channel TFT and the N-channel TFT as described above. It goes without saying that the pixel TFT can be configured with the same configuration.

  Reference numeral 3101 denotes a substrate. Reference numeral 3102 denotes a silicon oxide film. Reference numeral 3103 denotes a gate electrode. Reference numeral 3104 denotes a benzodiclobutene (BCB) film whose upper surface is flattened. Reference numeral 3105 denotes a silicon nitride film. The BCB film and the silicon nitride film constitute a gate insulating film. Reference numerals 3106, 3107, 3108 and 3109 denote active layers made of a polycrystalline silicon film. In the production of this active layer, the same method as the polycrystallization of the amorphous silicon film described in Example 4 was used. Alternatively, a method of crystallizing the amorphous silicon film with laser light (preferably linear laser light or planar laser light) may be used. Reference numeral 3106 denotes a source region, 3107 denotes a rain region, 3108 denotes a low concentration impurity region (LDD region), and 3109 denotes a channel formation region. Reference numeral 3110 denotes a channel protective film, and 3111 denotes an interlayer insulating film. Reference numerals 3112 and 3113 denote a source wiring and a drain wiring, respectively.

  According to this embodiment, since the gate insulating film composed of the BCB film and the silicon nitride film is planarized, the amorphous silicon film formed thereon is also planarized. Therefore, when the amorphous silicon film is polycrystallized, it is possible to obtain a polycrystalline silicon film that is more uniform than the conventional inverted stagger type TFT.

  In the liquid crystal panel of the present invention, various liquid crystals can be used in addition to the TN liquid crystal. For example, 1998, SID, "Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability" by H. Furue et al., 1997, SID DIGEST, 841, "A Full -Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time "by T. Yoshida et al., 1996, J. Mater. Chem. 6 (4), 671-673," Thresholdless antiferroelectricity in liquid crystals and its application to The liquid crystal disclosed in "displays" by S. Inui et al. or US Pat. No. 5,945,569 can be used.

  A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal. Among mixed liquid crystals having antiferroelectric liquid crystals, there is a so-called thresholdless antiferroelectric mixed liquid crystal that exhibits electro-optic response characteristics in which transmittance continuously changes with respect to an electric field. This thresholdless antiferroelectric mixed liquid crystal has a V-shaped electro-optic response characteristic, and a drive voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) is also found. ing.

  Here, FIG. 16 shows an example of the light transmittance characteristics of the thresholdless antiferroelectric mixed liquid crystal exhibiting a V-shaped electro-optic response with respect to the applied voltage. The vertical axis of the graph shown in FIG. 16 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. Note that the transmission axis of the polarizing plate on the incident side of the liquid crystal panel is set to be substantially parallel to the normal direction of the smectic layer of the thresholdless antiferroelectric mixed liquid crystal that substantially coincides with the rubbing direction of the liquid crystal panel. Further, the transmission axis of the output-side polarizing plate is set to be substantially perpendicular (crossed Nicols) to the transmission axis of the incident-side polarizing plate.

  As shown in FIG. 16, it can be seen that when such a thresholdless antiferroelectric mixed liquid crystal is used, low voltage driving and gradation display are possible.

  When such a low-voltage driven thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal panel having an analog drive circuit, the power supply voltage of the image signal sampling circuit is suppressed to, for example, about 5V to 8V. It becomes possible. Therefore, the operating power supply voltage of the drive circuit can be lowered, and low power consumption and high reliability of the liquid crystal panel can be realized.

  Further, even when such a thresholdless antiferroelectric mixed liquid crystal driven at a low voltage is used for a liquid crystal panel having a digital drive circuit, the output voltage of the D / A conversion circuit can be lowered. The operating power supply voltage of the / A converter circuit can be lowered, and the operating power supply voltage of the drive circuit can be lowered. Therefore, low power consumption and high reliability of the liquid crystal panel can be realized.

  Therefore, using such a thresholdless antiferroelectric mixed liquid crystal driven at a low voltage makes it possible to use a TFT (for example, 0 nm to 500 nm or 0 nm to 200 nm) having a relatively small LDD region (low concentration impurity region). It is also effective when used.

  In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization, and the dielectric constant of the liquid crystal itself is high. For this reason, when thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal panel, a relatively large storage capacitor is required for the pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization. Further, the driving method of the liquid crystal panel may be line-sequential driving so that the gradation voltage writing period (pixel feed period) to the pixel is lengthened, and this may be compensated for even if the storage capacitor is small.

  In addition, since low voltage driving is realized by using such a thresholdless antiferroelectric mixed liquid crystal, low power consumption of the liquid crystal panel is realized.

  Any liquid crystal having electro-optical characteristics as shown in FIG. 16 can be used as the display medium of the liquid crystal panel of the present invention.

  An example in which a liquid crystal panel is configured using the TFT substrate having the structure shown in Examples 1 to 5 is shown in FIG. FIG. 17 shows a portion corresponding to the main body of the liquid crystal panel, which is also called a liquid crystal panel.

  In FIG. 17, reference numeral 8001 denotes a TFT substrate, and a plurality of TFTs are formed on the TFT substrate 8001. These TFTs constitute a pixel portion 8002, a gate signal line driver circuit 8003, a source signal line driver circuit 8004, and a logic circuit 8005 on the substrate. A counter substrate 8006 is attached to such a TFT substrate. A liquid crystal layer (not shown) is sandwiched between the TFT substrate and the counter substrate 8006.

  In the configuration shown in FIG. 17, it is desirable that the side surface of the TFT substrate 8001 and the side surface of the counter substrate 8006 are all aligned except for one side. By doing so, the number of multiple chamfers from the large substrate can be increased efficiently. On the one side, a part of the counter substrate 8006 is removed to expose a part of the TFT substrate 8001, and an FPC (flexible printed circuit) 8007 is attached thereto. Here, an IC chip (semiconductor circuit composed of MOSFETs formed on single crystal silicon) may be mounted as necessary.

  Since the TFT formed by the manufacturing process shown in Embodiment 4 or Embodiment 5 has an extremely high operation speed, a signal processing circuit that is driven at a high frequency of several hundred MHz to several GHz is the same as the pixel portion. It can be formed integrally on the substrate. That is, the liquid crystal panel shown in FIG. 17 embodies a system-on-panel.

  The CMOS circuit and the pixel matrix circuit formed by implementing the present invention can be used for various electro-optical devices (active matrix liquid crystal panels). That is, the present invention can be implemented in all electronic devices in which these electro-optical devices are incorporated as display media.

Such electronic devices include video cameras, digital cameras, projectors (rear type or front type), head mounted displays (goggles type displays), game consoles, car navigation systems, personal computers, personal digital assistants (mobile computers, mobile phones) Or an electronic book).
An example of these is shown in FIG.

  FIG. 18A illustrates a personal computer, which includes a main body 7001, a video input portion 7002, a display device 7003, and a keyboard 7004. The present invention can be applied to the video input unit 7002 and the display device 7003.

  FIG. 18B illustrates a video camera which includes a main body 7101, a display device 7102, an audio input portion 7103, operation switches 7104, a battery 7105, and an image receiving portion 7106. The present invention can be applied to the display device 7102 and the voice input unit 7103.

  FIG. 18C illustrates a mobile computer, which includes a main body 7201, a camera portion 7202, an image receiving portion 7203, operation switches 7204, and a display device 7205. The present invention can be applied to the display device 7205.

  FIG. 18D illustrates a goggle type display which includes a main body 7301, a display device 7302, and an arm portion 7303. The present invention can be applied to the display device 7302.

  FIG. 18E shows a player using a recording medium (hereinafter referred to as a recording medium) on which a program is recorded. The player includes a main body 7401, a display device 7402, a speaker portion 7403, a recording medium 7404, and operation switches 7405. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display device 7402.

  FIG. 18F illustrates a game machine, which includes a main body 7501, a main body display device 7502, a display device 7503, a recording medium 7504, a controller 7505, a main body sensor portion 7506, a sensor portion 7507, and a CPU portion 7508. The main body sensor portion 7506 and the sensor portion 7507 can sense infrared rays emitted from the controller 7505 and the main body 7501, respectively. The present invention can be applied to the main body display device 7502 and the display device 7503.

  As described above, the application range of the present invention is extremely wide and can be applied to electronic devices in various fields. Moreover, the electronic apparatus of a present Example is realizable even if it uses the structure which consists of what combination of Examples 1-7.

The figure which shows the timing chart of the liquid crystal panel of this invention. Schematic of the TFT substrate of the present invention. The figure which shows arrangement | positioning of the pixel and color filter of this invention. FIG. 6 illustrates an example of a source signal line driver circuit of the present invention. FIG. 6 illustrates an example of a gate signal line driver circuit of the present invention. The equivalent circuit diagram of a shift register circuit and a level shift circuit. The figure of the TFT substrate which has a digital drive circuit. Sectional drawing which shows the manufacturing process of TFT of this invention. Sectional drawing which shows the manufacturing process of TFT of this invention. Sectional drawing which shows the manufacturing process of TFT of this invention. Sectional drawing which shows the manufacturing process of TFT of this invention. Sectional drawing which shows the manufacturing process of TFT of this invention. Sectional drawing which shows the manufacturing process of TFT of this invention. Sectional drawing which shows the structure of TFT of this invention. Sectional drawing which shows the structure of TFT of this invention. The figure which shows the characteristic of the light transmittance with respect to the applied voltage of a thresholdless antiferroelectric mixed liquid crystal. The external view of the liquid crystal panel of this invention. FIG. 16 is a diagram of an electronic device using the display device of the invention. The figure which shows the upper side figure and display pattern of a TFT substrate. The figure which shows the polarity pattern of a source line inversion drive and a gate line inversion drive. The enlarged view of a pixel part. The figure which shows the mechanism of generation | occurrence | production of disclination. The figure which shows the polarity pattern of a frame inversion drive. The figure which shows the timing chart of the conventional liquid crystal panel.

Explanation of symbols

1801 Source signal line driver circuit 1802 Gate signal line driver circuit 1803 Source signal line 1804 Gate signal line 1805 Pixel TFT (switching element)
1806 Liquid crystal cell 1807 Holding capacitor 1808 Pixel portion 1809 Image signal line

Claims (11)

A plurality of source signal lines, a plurality of gate signal lines, and transistors above the substrate;
An insulating film above the transistor;
An organic resin film above the insulating film;
A pixel electrode above the organic resin film,
The insulating film includes any one of silicon nitride, silicon oxide, and silicon oxynitride,
The pixel electrode is electrically connected to one of the plurality of source signal lines through the transistor,
A gate of the transistor is electrically connected to one of the plurality of gate signal lines;
During the first frame period, a first video signal is supplied to the pixel electrode through one of the plurality of source signal lines,
During a frame period subsequent to the first frame period, a second video signal having a polarity opposite to that of the first video signal is supplied to the pixel electrode through one of the source signal lines,
A liquid crystal display device having a frame frequency of 120 Hz or more. A plurality of source signal lines, a plurality of gate signal lines, and transistors above the substrate;
An insulating film above the transistor;
An organic resin film above the insulating film;
A pixel electrode above the organic resin film,
The insulating film includes any one of silicon nitride, silicon oxide, and silicon oxynitride,
The plurality of source signal lines include aluminum,
The pixel electrode is electrically connected to one of the plurality of source signal lines through the transistor,
A gate of the transistor is electrically connected to one of the plurality of gate signal lines;
During the first frame period, a first video signal is supplied to the pixel electrode through one of the plurality of source signal lines,
During a frame period subsequent to the first frame period, a second video signal having a polarity opposite to that of the first video signal is supplied to the pixel electrode through one of the source signal lines,
A liquid crystal display device having a frame frequency of 120 Hz or more. In claim 1 or 2,
The liquid crystal display device, wherein the organic resin film has a flat surface. In any one of Claims 1 thru | or 3,
The organic resin film has a thickness of 1.0 to 1.5 μm. In any one of Claims 1 thru | or 4,
The liquid crystal display device, wherein the organic resin film includes any one of polyimide, acrylic, polyamide, polyimide amide, and benzocyclobutene. In any one of Claims 1 thru | or 5,
The liquid crystal display device, wherein the plurality of gate signal lines include aluminum or copper. In any one of Claims 1 thru | or 6,
The liquid crystal display device, wherein the plurality of gate signal lines include any of titanium, tantalum, and tungsten. In any one of Claims 1 thru | or 7,
The plurality of gate signal lines include a first layer mainly composed of aluminum or copper and a second layer mainly composed of titanium, tantalum, or tungsten. apparatus. In any one of Claims 1 thru | or 8,
A liquid crystal display device comprising a second substrate provided with a color filter. In claim 9,
A liquid crystal display device comprising a liquid crystal between the first substrate and the second substrate.   An electronic apparatus using the liquid crystal display device according to claim 1.

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