JPH10105133A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable display operation in a high frame frequency with simple configuration by dividing one line of a display panel into plural sections and outputting devided display data to a display panel in parallel by each of plural X driving circuits. SOLUTION: A serial/parallel conversion circuit SP converts color display data R, G, B inputted serially to parallel data of four bits respectively. Each color data classified with color by a color selecting circuit CSEL and outputted serially is divided into two parts for each color by a division data control circuit DDC. A display screen of a color liquid crystal display panel LCD is divided into two parts of apparent left (L) and right (L), and X (signal line) driving circuits XDVL and XDVR are provided corresponding to each part. As the X driving circuits XDVL and XDVR take simultaneously divided display data, transfer speed of display data is increased double for a display panel LCD.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color display device, for example, a high-resolution color display having a relatively large screen suitable for a display device in a computer system or various control devices. The present invention relates to technology that is effective when used with a liquid crystal panel. 2. Description of the Related Art An example of a color liquid crystal display device is disclosed in JP-A-59-212101. This color liquid crystal display device has a structure in which color display data is once stored in a frame memory, and thereafter, color data consisting of red, green and blue is repeatedly read out for each line of the color liquid crystal display panel, and given to the color liquid crystal display panel. Has become. In the above-described color liquid crystal display device, when a color liquid crystal display panel having a relatively large screen such as 640 × 200 dots is driven, one screen area is correspondingly driven. There is a problem that the storage capacity of the frame memory increases because the display data increases. [0004] In the above color display panel,
In one horizontal period, it is necessary to supply each color data of red (R), green (G), and blue (B) each composed of 640 dots. The liquid crystal display frame frequency is X (signal line) for performing serial / parallel conversion of the color data.
It depends on the data transfer speed of the drive circuit. For example, when using “HD66106” sold by Hitachi, Ltd. with a maximum transfer rate of 6 MHz, the frame frequency
f is obtained by the following equation (1). F = 1 / (1/6 MHz) × (640/4) × (200 × 3) = 62.5 Hz (1) Here, 640/4 of the second term of the denominator is The color data is serially transferred in units of 4 bits, and the third term, 200 × 3, forms one color dot (line) by three primary color lines of R, G and B. It means to do. As described above, when the frame frequency f is 62.
If the frequency is only 5 Hz, flickering of the screen and deterioration of the image quality at high temperatures become a problem in the color liquid crystal display panel. That is, in a liquid crystal display panel having an active matrix configuration, it is necessary to write color data in both positive and negative polarities for AC driving of the liquid crystal, and the substantial frame frequency f is about half of the frame frequency f. This is because the frequency drops to 31 Hz. An object of the present invention is to provide a color display device capable of performing a display operation at a high frame frequency with a simple configuration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Means for Solving the Problems The following is a brief description of an outline of typical inventions disclosed in the present application. That is, first and second storage circuits for storing color display data corresponding to one line of a color display panel are provided, and the first and second storage circuits are alternately controlled to write and read. The color display data read from the first or second storage circuit is divided and supplied in parallel corresponding to a plurality of divided X drive circuits. According to the above-described means, the storage circuit for storing the color display data has a configuration for storing one line of data, so that the storage capacity can be reduced. Since the display data can be input in parallel, the transfer speed in the X drive circuit can be equivalently increased, so that a high quality display screen can be obtained. FIG. 1 is a block diagram showing one embodiment of a color display device according to the present invention. The color display device of this embodiment uses an active matrix color liquid crystal display panel LCD. Although not particularly limited, as shown in FIG.
Display of color pixels of 0 dots × 200 lines is enabled. One line is composed of a combination of red, green, and blue color filters on three horizontal stripes, and correspondingly, Y1 to Y shown as examples.
3, Y4 to Y6 ... Y598, Y599, Y60
A Y selection (scanning) line such as 0 is provided. Further, signal lines X1 to X640 are arranged in the vertical direction.
Therefore, the color liquid crystal display panel LCD has 600 Y selection lines in the vertical direction as described above, and the total number of pixels is 640 × 600. In FIG. 1, the color display device includes R, G
And B are provided. By combining the color data consisting of these three primary colors,
Display of color pixels of eight colors (including white and black) is enabled. The dot clock signal CLK is equal to the display data R,
It is supplied in synchronization with G and B. Display timing signal D
ST is a timing signal that is displayed as visible information (valid display data) of display data when it is set to a high level, and is set as a horizontal blanking period when it is set to a low level. The horizontal synchronizing signal HSYN is a timing signal for controlling one line, and the vertical synchronizing signal VSYN is a timing signal for controlling one frame. The serial / parallel conversion circuit SPC receives the above three color display data R, G, and B, and in synchronization with the dot clock signal CLK and the display timing signal DST, the serially input color display data R, G, and B, respectively. G and B are each changed to 4-bit parallel data. These 4-bit parallel data are supplied to the input of a write memory selection circuit (hereinafter simply referred to as a multiplexer) MPX1. The multiplexer MPX1 selectively converts the color display data converted into the 4-bit parallel data into a first signal in accordance with a control signal R / W described later.
To the write input terminal of the line memory LM1 or the second line memory LM2. The first and second line memories LM1, L
M2 has a storage capacity for storing color display data corresponding to one line of the color liquid crystal display panel LCD. That is, since the display panel LCD has 640 dots in the horizontal direction, a storage capacity of 640 × 3 bits is required. The line memories LM1, LM2
Since the parallel data formed by the serial / parallel conversion circuit SPC is input as described above, 4 ×
Memory access is performed in units of 3 bits. Therefore,
The line memories LM1 and LM2 have addresses 0 to 159, respectively, as described later. Although not particularly limited, the line memories LM1 and LM2 are
A static RAM (line-dumb access memory) is used. Instead of this configuration, a dynamic memory cell can be used. This is because the line memories LM1 and LM2 alternately perform a write operation and three read operations every one horizontal period, as described later. Since such a write operation and a read operation are always performed at the extremely short time interval as described above, a refresh operation is also always performed, and even if a dynamic memory cell is used, a static memory cell can be used. Memory access can be performed in the same manner as used. By doing so, the occupied area of the line memories LM1 and LM2 can be further reduced in combination with the small storage capacity. The first and second line memories LM1, L
On the read output terminal side of M2, a read memory selection circuit (hereinafter simply referred to as a multiplexer) MPX2 is provided. The multiplexer MPX2 performs a switching operation complementarily to the multiplexer MPX1 for writing. For example, the multiplexer MPX1 for writing makes one of the line memories LM1 according to the control signal R / W.
When transmitting the parallel display data to (or LM2), the multiplexer MPX2 used for the read data selects and outputs the read data of the other line memory LM2 (or LM1). The write control circuit WC receives the dot clock signal CLK, the display timing signal DST and the horizontal synchronizing signal HSYN, and generates the control signal R / W and the write address signal WA. Also, the read control circuit R
C receives the horizontal synchronizing signal HSYN and generates a read address signal RA and a 2-bit color selection signal CS. For example, by the write control circuit WC,
If the control signal R / W is at a high level, the multiplexer MP
X1 selects the first line memory LM1. The read / write control circuit RWC responds to the control signal R / W,
The write address signal WA generated by the write control circuit WC is output as the address signal A1 of the line memory LM1. Thus, color display data R, G, and B composed of three primary colors serially input for one line.
Is written to the line memory LM1. On the other hand, the read address signal RA generated by the read control circuit RC is transmitted by the read / write control circuit RWC as the address signal A2 of the second line memory LM2. As a result, the line memory LM2 performs a read operation, and supplies the stored color display data to the color selection circuit CSEL through the multiplexer MPX2. As described above, since the three primary color data R, G, and B are output in parallel in units of 4 bits from the line memory LM2, the color selection circuit CSEL outputs the three primary color data R, G, and B in response to the color selection signal CS. B
Output in chronological order. In this embodiment, in order to increase the frame frequency equivalently, each color data serially output by being divided into colors is divided data control circuit DDC.
Although there is no particular limitation, the image is divided into two for each color. Correspondingly, X drive circuits XDVL, XDVR
Is also divided into two. That is, the color liquid crystal display panel L
The display screen of the CD is apparently divided into two parts, left (L) and right (R), and the X drive circuits XDVL and XDVR are provided correspondingly to the two. In this configuration, the X driving circuits XDVL and XDVR are provided with a color liquid crystal display panel of 640.
Despite having one signal line electrode, half of it has 320
It has only display data driving capability corresponding to the signal electrodes. Since a configuration is adopted in which two display data are simultaneously read, the transfer speed of the display data can be doubled as viewed from the liquid crystal display panel LCD.
In other words, the time required for capturing one line of display data can be reduced by half. The timing control circuit TC receives the display timing signal DST and the vertical synchronizing signal VSYN, and receives a data shift clock signal DS necessary for the operation of the X drive circuits XDVL and XDVR and the Y drive circuit YDV.
C, forming a line clock signal LCK. Further, the timing control circuit TC generates a line head clock signal LFS supplied to the Y drive circuit YDV. The Y drive circuit YDV captures the high level of the clock signal LFS at the falling edge of the line clock signal LCK,
The scanning line Y1 is set to a high level. Then, in synchronization with the falling edge of the line clock signal CLK, the high level is shifted in correspondence with Y2, Y3,... FIG. 2 is a timing chart for explaining the operation of the color display device of this embodiment. In the color display device of this embodiment, one frame period is composed of 204 horizontal periods, and the vertical synchronizing signal VSYN is generated almost in synchronization with the first horizontal period. The vertical blanking period is from the 203rd horizontal period of the previous frame to the 2nd horizontal period of the frame. Therefore, the display operation in one frame is performed in 200 horizontal periods corresponding to 1 to 200 lines from the third horizontal period to the 202nd horizontal period. One horizontal period includes a horizontal synchronizing signal HSYN.
As shown in the figure in an enlarged manner,
While the display timing signal DST is at the high level, the color display data consisting of R, G, and B is regarded as valid display data, and the remaining data is regarded as horizontal blanking data (black display). As described above, the effective display data includes red (R), green (G), and blue (B) each composed of 640 dots (bits). FIG. 4 shows the color liquid crystal display panel LC.
D and its X drive circuits XDVL, XDVR and Y drive circuit YDV are shown. As described above, the color liquid crystal display panel LCD
Has a color filter on a horizontal stripe, and one line is composed of three pixel columns consisting of R, G and B. As described above, the Y drive circuit YDV
It has scanning lines 1 to Y600 and captures a line head clock LFS generated at the beginning of a frame,
In synchronization with the line clock signal LCK, a Y selection signal is formed by shifting it. Therefore, one horizontal display period is temporally divided into three as described later, and X
From the driving circuits XDVL and XDVR, 640-dot R1
When data is transmitted, the scanning line Y1 is selected, when G1 data is transmitted, the scanning line Y2 is selected, and when B1 data is transmitted, the scanning line Y3 is selected. Thus, the color image data of the first line 1 is written to each pixel in one horizontal period. In the next horizontal period, X driving circuits XDVL and XDVL
When R2 data of 640 dots is transmitted from VR, the scanning line Y4 is selected, when G2 data is transmitted, the scanning line Y5 is selected, and when B2 data is transmitted, the scanning line Y6 is switched. It is selected. Thus, the color image data of the next line 2 is written to each pixel. Similarly, the color pixel data R200, G200, and B200 up to the last line 200 are written to each pixel. Thus, writing of one frame is performed. The same display data R1, G1, B1 to R200, G200, B
200 is inverted and the X drive circuits XDVL and XD
The output is output from the DVR, and the same scanning line selection operation as described above is performed in synchronization with the output. Therefore, the liquid crystal display panel LCD of the active matrix configuration needs to spend two frames to display one screen. FIG. 4 shows the line memory LM1 or L
A timing chart for explaining an example of the color display data written in M2 is shown. The serial / parallel conversion circuit SPC converts the serially input color display data of each color (R, G, and B) into parallel in 4-bit units to form write parallel data. That is, signals R0 to R159, G0 to G corresponding to each color in units of 4 bits.
159 and B0 to B159 are written to the line memory LM1 or LM2. As a result, color display data of 160 × 4 = 640 bits is written for each color as a whole. FIG. 5 shows the line memories LM1 and LM
2 is shown. In this embodiment, since the write parallel data is input in units of 4 × 3 bits as described above, the line memories LM1 and LM2 store addresses 0 to 1 respectively.
It is made to have 59. In this embodiment, in order to increase the frame frequency as described above, the X drive circuit is divided into two as described above, such as XDVL and XDVR. In order to cope with this, signals R0 to R79, G0 to G79 and B0 to B79 to be made to correspond to the X drive circuit XDVL are:
158, X drive circuit X
Signals R80 to R159, G80 to be corresponding to DVR
G159 and B80 to B159 are odd addresses 1,
.. 159. As a result, in the line memories LM1 and LM2, odd-numbered addresses store left-side data, even-numbered addresses store right-side data, and one address stores 4 × 3 = 12-bit color display data. FIG. 6 shows the line memory LM1 or L
A timing chart for explaining the read operation from M2 is shown. The address signal RA formed by the read control circuit RC is supplied to the line memory LM1 (or LM) by the switching operation of the multiplexer MPX1 according to the level of the control signal R / W and the read / write control circuit RWC.
While the above-described writing is performed in response to 2), the read / write control circuit RWC transmits the read signal to the other line memory LM2 (or LM1), and the read signal is output by switching the multiplexer MPX2. . At this time, the read control circuit RC generates the address signal RA so that the selected line memory LM2 (or LM1) is read three times in one horizontal period. Therefore, the parallel data read through the multiplexer MPX2 is R0-R159, G0-G159.
And B0 to B159 are repeatedly output three times. A 2-bit color selection signal CS is formed according to the number of times of reading by the read control circuit RC. For example, in the first reading, the color selection signal CS is set to 0 (00), and the color selection circuit CSEL is
Of the color display data composed of the three primary colors as described above, R
0 to R159 are output. In the second read, the color selection signal CS is set to 1 (01), and the color selection circuit C
The SEL outputs G0 to G159 among the color display data including the three primary colors as described above. In the third reading, the color selection signal CS is set to 2 (10), and the color selection circuit CSEL outputs B0 to B159 among the color display data including the three primary colors as described above. The color display data R0 to R159, G0 to G159 and B0 to B1 are divided into odd addresses and even addresses of the line memories LM1 and LM2.
59 are stored, and if the read address signal RA is generated in order from 0 to 159, R
Left and right alternate color display data such as 0 and R80 and R1 and R81 are output. Divided data control circuit DDC
Temporarily latches the left and right color display data corresponding to the X drive circuits XDVL and XDVR as described above, and supplies the data to the X drive circuits XDVL and XDVR. For example, if the serial transfer speed of the X drive circuits XDVL and XDVR is 6 MHz as described above, the line memories LM1 and LM2 are read at twice the speed. The parallel color data divided as described above is used to synchronize the color display data R0 to R79 and R80 to R159 with the data shift clock DSC in units of 4 bits in the X drive circuits XDVL and XDVR, respectively. Then, when the capture is completed, the data is divided into color display data of X1 to X640 and output in parallel in synchronization with the line clock LCK. G
0 to G79, G80 to G159 and G0 to G79
G80 to G159 and G0 to G79, and G
Capture of color display data from 80 to G159,
The output is performed in the same manner as described above. However, since the Y drive circuit YDV switches the selection line from Y1 to Y2 and Y3 in synchronization with the line clock CLK, the display operation corresponding to each color line is performed. In this embodiment, by using two line memories as described above, while the display data is being written to one of the line memories, the other line memory which has already been written can be read. Since the display operation is performed by performing the operation, only a storage circuit having a storage capacity of two lines is provided. Therefore, as compared with a conventional device using a frame memory, a color display device having a large screen and high image quality can be configured with a small number of storage circuits. That is, if the number of display lines on one screen is N, the storage capacity can be greatly reduced to 2 / N as compared with the related art. Further, since the X drive circuit is divided into two, the time required for the transfer operation is halved. In other words, from the viewpoint of the entire display device, this is equivalent to doubling the transfer speed of the X drive circuit. Therefore, as apparent from the above description, the frame frequency is 125
Hz and a higher frequency can be achieved. by this,
Even if the same display data is written in positive and negative polarities for AC driving of the liquid crystal display panel LCD, a frame frequency of 62.5 Hz and high image quality with less flicker than a home television image machine can be obtained. . The operation and effect obtained from the above embodiment are as follows. That is, (1) First and second line memories for storing color display data corresponding to one line of a color display panel are provided, and the first and second line memories are alternately written and read controlled. At the same time, the color display data read from the first or second line memory is divided and supplied in parallel corresponding to a plurality of divided X drive circuits. In this configuration, since only two lines of data are stored as a storage circuit for storing color display data, an effect is obtained that the storage capacity of the storage circuit required for the display operation can be reduced. (2) According to the above (1), the liquid crystal display controller can be constituted by a one-chip semiconductor integrated circuit, and the effect that the system can be greatly simplified can be obtained. (3) Since the X drive circuit can be divided and the color display data stored in the line memory can be input in parallel corresponding thereto, the transfer speed in the X drive circuit can be equivalently increased, so that the frame frequency And a high-quality display screen without flicker can be obtained. (4) In a liquid crystal display panel having an active matrix configuration, since a configuration is adopted in which pixels are regarded as capacitances and display data is held, the leakage current increases as the temperature rises. Therefore, by increasing the frame frequency as described above, the number of times of writing per unit time can be increased, and an effect that a display operation up to a high temperature can be realized is obtained. (5) By dividing the X drive circuit, it is possible to drive a liquid crystal display panel having a larger screen and a higher density while using an existing drive circuit. Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example,
The X driving circuit may be divided into three or more N circuits. In this case, the substantial transfer speed can be increased N times. For example, in FIG. 1, the X drive circuit may be divided into four parts, and the parallel data formed by the serial / parallel conversion circuit SPC may be changed from four bits to two bits. In this configuration, the frame frequency is the same, but the serial shift register constituting the X drive circuit has a 2-bit configuration, and the circuit can be simplified. Further, in the X drive circuit, the divided X drive circuits may be configured in one semiconductor integrated circuit. That is, a plurality of X drive circuits may be provided in one semiconductor integrated circuit. By doing so, the number of circuit components constituting the color display device can be reduced. The specific configuration of the memory control circuit for alternately performing the write / read operation of the two line memories can employ various embodiments. This can be applied to those using various color display panels having a matrix configuration, in addition to those using a color liquid crystal display panel. The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows. That is, first and second line memories for storing color display data corresponding to one line of a color display panel are provided, and the first and second line memories are alternately controlled for writing and reading. The color display data read from the first or second line memory is divided and supplied in parallel corresponding to a plurality of divided X drive circuits. In this configuration, since only two lines of data are stored as the storage circuit for storing the color display data, the storage capacity of the storage circuit required for the display operation can be reduced. Also,
Since the X drive circuit can be divided and the color display data stored in the line memory can be input in parallel corresponding thereto, the transfer speed in the X drive circuit can be equivalently increased, so that the frame frequency can be increased and the flicker can be reduced. It is possible to obtain a high quality display screen without any.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of a color display device according to the present invention. FIG. 2 is a timing chart for explaining a display operation of the color display device shown in FIG. FIG. 3 is a configuration diagram showing one embodiment of a color liquid crystal display panel. FIG. 4 is a timing chart for explaining write parallel data to a line memory; FIG. 5 is a memory map diagram showing one embodiment of a line memory. FIG. 6 is a timing chart for explaining parallel data read from a line memory; [Explanation of Symbols] SPC: serial / parallel conversion circuit, MPX1: multiplexer (write memory selection circuit), MPX2: multiplexer (read memory selection circuit), LM1, LM2: line memory, RWC: read / write control circuit, TC ... Timing control circuit, LCD: color liquid crystal display panel, W
C: write control circuit, RC: read control circuit, CSEL: color selection circuit, DDC: divided data control circuit, XDV
L, XDVR ... X drive circuit, YDV ... Y drive circuit.

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[Procedure amendment] [Date of submission] August 26, 1997 [Procedure amendment 1] [Document name to be amended] Description [Item name to be amended] Name of invention [Amendment method] Change [Content of amendment] name] liquid crystal display device [Amendment 2] [range of the correction target document name] specification [correction target item name] range [correction method of the claims] change [correction content] [claims] 1. The liquid crystal display panel of a matrix type and one line of the liquid crystal display panel are divided into a plurality of
A plurality of X drive circuits corresponding to each section , and one line of display data for each of the plurality of X drive circuits.
Of the display data of the corresponding category
A divided data control circuit, wherein each of the plurality of X driving circuits is a divided data control circuit.
Display data imported from the LCD panel
A liquid crystal display device characterized by outputting to a liquid crystal display. 2. Matrix type liquid crystal display panel and display data corresponding to one line of the liquid crystal display panel
Is divided into a plurality, and each of the divided plurality of display data is
And import the corresponding section display data.
The number of X drive circuits, and the liquid crystal display panel includes a plurality of X drive circuits.
Display divided display data output in parallel from the
Liquid crystal display device. 3. The liquid crystal display panel of a matrix type and one line of the liquid crystal display panel are divided into a plurality of
A plurality of X drive circuits respectively corresponding to each section, and display of one line for each of the plurality of X drive circuits
Divide the data into multiple parts and display the divided display data.
Data to be output in parallel to the plurality of X drive circuits.
A liquid crystal display device comprising a data processing circuit. 4. Color display data of three primary colors is stored in a plurality of X drive circuits.
Is converted from parallel to serial and then divided into multiple
Claims that are supplied
4. The liquid crystal display device according to claim 1, 2, or 3. 5. The liquid crystal display panel has a horizontal stripe color filter.
Color liquid with active matrix configuration
Claims characterized by being a crystal display panel
5. The liquid crystal display device according to 1, 2, 3, or 4. [Procedure amendment 3] [Document name to be amended] Description [Item name to be amended] 0009 [Amendment method] Change [Content of amendment] [Means for Solving the Problems] To achieve the above object, the present invention Is characterized in that a matrix-type liquid crystal display panel, a plurality of X drive circuits that divide one line of the liquid crystal display panel into a plurality of sections, and correspond to each of the sections, Each of the X drive circuits includes a divided data control circuit that divides and supplies the display data of a corresponding section out of the display data for one line, and each of the plurality of X drive circuits includes the divided data control circuit. A liquid crystal display device outputs display data taken from a circuit in parallel to the liquid crystal display panel. A feature of the present invention is that a matrix-type liquid crystal display panel and display data corresponding to one line of the liquid crystal display panel are divided into a plurality of pieces, and each of the plurality of divided pieces of display data is made to correspond to each of the divided pieces of display data. , A plurality of X's to take in the corresponding section display data
A driving circuit, wherein the liquid crystal display panel includes the plurality of Xs.
The liquid crystal display device displays the divided display data output in parallel from each of the drive circuits. Further, a feature of the present invention is that a matrix type liquid crystal display panel, a plurality of X drive circuits which divide one line of the liquid crystal display panel into a plurality of sections and correspond to each of the sections, A data processing circuit that divides one line of display data into a plurality of pieces of display data for each of the plurality of X drive circuits and outputs the divided display data to the plurality of X drive circuits in parallel; The liquid crystal display device comprises: According to a preferred embodiment of the present invention, the color display data of the three primary colors is converted into parallel data and then supplied to the plurality of X drive circuits after being converted into a plurality of data. Further, according to a preferred embodiment of the present invention, the liquid crystal display panel is a color liquid crystal display panel having an active matrix structure provided with color filters of a horizontal stripe shape. [Procedure amendment 4] [Document name to be amended] Description [Item name to be amended] 0010 [Correction method] Change [Contents of amendment] With the above configuration, the X drive circuit can be divided into a plurality of parts. Since the display data can be input in parallel corresponding thereto, the data capture speed of the X drive circuit can be equivalently increased, so that a high definition display screen can be obtained. [Procedure amendment 5] [Document name to be amended] Description [Item name to be amended] 0046 [Amendment method] Change [Content of amendment] Effect of the present invention The effect obtained is briefly described as follows. That is, by dividing the X drive circuit into a plurality of parts, display data can be input in parallel corresponding to the plurality of X drive circuits, so that the data capture speed of the X drive circuit can be equivalently increased, so that a high definition display screen is obtained. Can be. More specifically, the X drive circuit having a transfer rate of 6 MHz described in the present application is divided into right and left, and each X drive circuit is divided into two parts.
It is possible to display 640 dots per line by associating the drive circuit with color display data for one line divided into two parts on the left and right. In addition, it is possible to display 1280 dots per line by dividing the X drive circuit into four parts on the left and right and making each X drive circuit correspond to one part of the color display data for one line divided into four parts on the left and right. is there. Similarly, the X drive circuit is divided into a plurality of parts, and each X drive circuit is made to correspond to a plurality of divided pieces of color display data for one line, thereby increasing the number of display dots per line according to the divided number. It is possible to obtain a higher definition display screen.

Continuation of front page    (72) Inventor Kazuhiro Fujisawa             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi, Ltd. microelectronics machine             Instrument development laboratory (72) Inventor Kaoru Hasegawa             3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd.             Sakusho Mobara Factory (72) Inventor Shinzo Matsumoto             3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd.             Sakusho Mobara Factory (72) Inventor Mitsuhisa Fujita             3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd.             Sakusho Mobara Factory

Claims (1)

[Claims] 1. A first and second storage circuit for storing color display data corresponding to one line of the color display panel, and a memory control circuit for alternately performing writing and reading operations in the first and second storage circuits. The color display data read from the first or second storage circuit is divided into a plurality of pieces and supplied, and an image signal corresponding to one line is serially captured and output in parallel to the color display panel. X divided into multiple
A color display device comprising a driving circuit. 2. The input sections of the first and second storage circuits are provided with a switching circuit for writing, the output section is provided with a switching circuit for reading, and the memory control circuit is adapted to respond to input of write data. 2. A write control circuit for generating an address signal and a control signal, and a read control circuit for generating an address signal and a color selection signal in response to a display operation. Color display device. 3. 3. The color display device according to claim 2, wherein color display data of three primary colors is serially / parallel-converted and supplied in units of a plurality of bits to an input of said switching circuit for writing. Display device. 4. The color display data read from the first or second storage circuit is output in chronological order for each color in response to a color selection signal, and is divided into corresponding X
4. The color display device according to claim 1, wherein the color display devices are supplied to the drive circuits in parallel. 5. 5. The color display panel according to claim 1, wherein said color display panel is an active matrix color liquid crystal display panel provided with horizontal stripe color filters. Display device.