JPH07193679A - Plural line simultaneous drive liquid crystal display device - Google Patents

Abstract

PURPOSE:To reduce number of components and power consumption by reading picture element data by one pattern stored in a DRAM by plural lines and storing plural lines of data in a memory B while a memory A stores the picture element data by one pattern and the data are displayed. CONSTITUTION:A control section 15 controls the entire display device to write 16-picture elements of pixel data(PD) to a video RAM 16a and a register 17a is provided with a memory latch sections A, B and an upper and lower patterns are processed for the operation similarly. When the latch section A reads 16PD of 1st to 7th lines of the RAM 16a, the PD in each bit is outputted from each line. An arithmetic processing section 9a makes arithmetic operation between an orthogonal function stored in the register 8a and the PD to provide an output of the result to a DAC 11a. The latch section B reads and stores succeeding 7-lines of 16PD from the RAM 16a sequentially and provides an output similarly when the output of the latch section A is finished, and the operations above are repeated by the latch sections A, B. Thus, an upper pattern 14a is formed by row/column data generated by row/column drivers to reduce number of components and power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-line simultaneous drive liquid crystal display device, and more particularly, to a multi-line simultaneous drive liquid crystal display device for displaying information using an active addressing system for simultaneously selecting a plurality of lines of a simple matrix liquid crystal display device. Regarding display device.

[0002]

2. Description of the Related Art In a conventional simple matrix liquid crystal display device, data for one row is stored in columns in a row electrode.
Each time it came out of the driver, the voltage was sequentially applied to form one frame. However, in such a system, in the case of an N-row liquid crystal display device, a voltage is applied during one frame only for a time of 1 / n, so that there is a drawback that the contrast is low.

Therefore, in recent liquid crystal display devices,
A method based on the active addressing method is used. In this method, since the density of a pixel of a liquid crystal display device is proportional to the potential difference √Vrms ² applied to the pixel,
It is sufficient that Vrms in one frame is proportional to the pixel to be displayed. In the active addressing method, a Walsh function, which is a kind of orthogonal function, is used for the row electrodes, and pixel data to be displayed and Wa
The sum of products of lsh functions is used.

FIG. 12 is a block diagram showing a liquid crystal display device using a conventional active addressing system, and the simultaneous scanning lines will be described below as 7 lines. 12
In FIG. 1, the display controller 1 is connected to a CPU (not shown) via the bus 2 and performs control for displaying data given from the CPU on the liquid crystal display device 14. A video RAM 3 is connected to the display controller 1, and the display controller 1 temporarily stores the data given from the CPU in the video RAM 3. The memory management unit 4 generates a clock signal and an address signal necessary for displaying data on the liquid crystal display device 14.

The liquid crystal display device 14 is composed of a 640 × 480 dot matrix and is divided into an upper screen 14a of 640 × 240 dots and a lower screen 14b of 640 × 240 dots. And these upper screen 14a and lower screen 1
4b is individually display-controlled by the structure described below. The display control unit of the upper screen 14a is the orthogonal function generator 6a.
In addition, the orthogonal function generator 6a generates the aforementioned Walsh function as an orthogonal function according to the clock signal given from the memory management unit 4 and stores it in the register 8a.
The frame buffer 5a stores pixel data and is composed of seven SRAMs. The pixel data stored in the frame buffer 5a is stored in the register 7a. The arithmetic processing unit 9a has a function of performing an exclusive OR operation and a total operation, and obtains an exclusive OR of the orthogonal function stored in the register 8a and the pixel data stored in the register 7a. rear,
The sum of the bits is taken and given to the D / A converter 11a. The D / A converter 11a converts the input digital signal into an analog signal, and the upper screen column driver 1
Give to 2a. The upper screen column driver 12a drives the column electrodes of the upper screen 14a. Further, the orthogonal function stored in the register 8a is given to the row data generation circuit 10a to generate row data, and the upper screen row driver 13a drives the row electrodes of the upper screen 14a.

The display control unit of the lower screen 14b is also configured in the same manner, and includes the frame buffer 5b, the orthogonal function generator 6b, the registers 7b and 8b, the arithmetic processing unit 9b, the row data generation circuit 10b, the D / A converter 11b, and the lower unit. It includes a screen column driver 12b and a lower screen row driver 13b.

Next, the operation will be described. When serial data is input to the display controller 1 from the CPU via the bus, the display controller 1 stores the serial data in the video RAM 3. The memory management unit 4 writes the data from the video RAM 3 into the frame buffers 5a and 5b as pixel data. In the example shown in FIG. 12, a plurality of scan lines, for example, 7 lines are simultaneously driven as one block. In this case, the time allowed for the data processing of the pixels of 7 lines is calculated as follows. That is, if the frame frequency is 60 Hz and the period of the orthogonal function is 8 periods, then 1 / {60 [Hz] × (INT (240/7) +1)
[Number of blocks] × 8 [Cycle] × 640 (columns)} ≈93
[Nsec]. During this 93 nsec, one block of data has to be read and operated. In order to satisfy the above conditions, the frame buffers 5a and 5b have 7 lines arranged at different bits of the same address, and realize high-speed reading. In this case, seven SRAMs are used only for the upper screen.

The memory management unit 4 reads the 7-bit pixel data from the frame buffer 5a and the orthogonal function from the orthogonal function generator 6a in a predetermined display cycle and stores them in the registers 7a and 8a, respectively. The arithmetic processing unit 9a performs an exclusive OR operation on each data output from the registers 7a and 8a, and sums the bits to obtain the D / A converter 11a.
Give to. The D / A converter 11a converts the digital signal into an analog signal, and the upper screen column driver 1
2a drives the column electrode of the upper screen 14a. On the other hand, the row data generation circuit 10a generates row data by the orthogonal function output from the register 8a and supplies the row data to the upper screen row driver 13a, and the upper screen row driver 13a drives the row electrodes. This operation is sequentially performed during the display cycle period.

[0009]

In the conventional active addressing method shown in FIG. 12, seven SRAs are provided for each of the upper screen 14a and the lower screen 14b.
Since the frame buffers 5a and 5b made of M are used, there are disadvantages that the cost is high and the power consumption is large. Further, when trying to display multi-values on the liquid crystal display device 14, it is necessary to increase the memory capacity of the frame buffers 5a and 5b in that portion in parallel, which results in higher power consumption and higher cost. Furthermore, since the number of parts is large, there is a problem in that it is difficult to expand to portable and small devices.

Therefore, a main object of the present invention is to provide a multi-line simultaneous drive liquid crystal display device which can be reduced in the number of parts to reduce power consumption and cost and is suitable for downsizing.

[0011]

The invention according to claim 1 is
In a simple matrix liquid crystal display device in which electrodes are arranged in a plurality of rows and a plurality of columns, it is a multiple line simultaneous drive liquid crystal display device that selects and drives electrodes of a plurality of rows at the same time. A dynamic random access memory for storing pixel data for the screen,
While the pixel data stored in the first memory holding unit that stores pixel data for a plurality of lines read from the dynamic random access memory and the first memory holding unit are displayed, the next plurality of lines are displayed. Register means having a second memory holding portion for storing pixel data for one minute, orthogonal function generating means for generating an orthogonal function, and the generated orthogonal function and output from the first or second memory holding portion of the register means. Arithmetic means for performing exclusive OR with the pixel data of a plurality of lines and total operation thereof, column driving means for simultaneously driving the column electrodes of the simple matrix liquid crystal display according to the arithmetic result, and the orthogonal function On the basis of this, a row driving means for simultaneously driving row electrodes of a plurality of lines of the simple matrix liquid crystal display is provided.

According to a second aspect of the present invention, there is provided address conversion means for converting a row address and a column address of the dynamic random access memory according to the first aspect.

According to the invention of claim 3, the dynamic random access memory of claim 1 includes a dual port dynamic random access memory.

In the invention according to claim 4, the dual port dynamic random access memory according to claim 3 outputs pixel data serially in a time division manner.

According to a fifth aspect of the present invention, the dynamic random access memory according to the first aspect includes a writing means for writing a plurality of values of pixel data whose gradation is controlled.

According to the invention of claim 6, the dynamic random access memory of claim 5 includes a dual port dynamic random access memory.

[0017]

In the liquid crystal display device simultaneously driven by a plurality of lines according to the present invention, the dynamic random access memory which stores the pixel data for one screen to be displayed reads the pixel data for a plurality of lines and the first register means. Of the pixel data and the orthogonal function, and performs the exclusive OR of the pixel data and the orthogonal function, and simultaneously drives the column electrodes of the simple matrix liquid crystal display according to the result. The row electrodes of a plurality of lines are simultaneously driven while the pixel data of the next plurality of lines are stored in the second memory holding unit of the register means.

[0018]

1 is a block diagram of an embodiment of the present invention. The embodiment shown in FIG. 1 is similar to that shown in FIG.
It is constructed in the same manner as the conventional example shown in FIG. That is,
The control unit 15 includes the display controller 1, the video RAM 3 and the memory management unit 4 shown in FIG. Then, instead of the frame buffers 5a, 5b, the video RAMs 16a, 1
6b is provided, and registers 17a and 17b are provided instead of the registers 7a and 7b. Video RAM 16a, 1
A 64k × 16-bit DRAM is used as 6b, and a register having two memory holding units A and B is used as registers 17a and 17b.

FIG. 2 is a diagram showing an area of the register shown in FIG. As shown in FIGS. 2A and 2B, the registers 17a and 17b shown in FIG. 1 can store 16-bit pixel data corresponding to 7 lines, respectively. 16), 16-bit pixel data is stored for each line, and 16-bit pixel data is collectively read in parallel.

FIG. 3 is a diagram for explaining address conversion in the embodiment shown in FIG. 1, and FIG. 4 is a time chart for explaining page mode and normal access.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. The control unit 15 is a CPU
The serial data input from the bus via the bus 2 is sequentially stored in the video RAM 16a. Then, the control unit 15 reads pixel data bit by bit from the video RAM 16a in one display cycle. When one display cycle has a frame frequency of 60 Hz, the period of the orthogonal function is 8 periods, and the number of lines that can be simultaneously scanned by a plurality of lines is 7, 1 / {60 [Hz] × (INT (240) / 7 + 1)
[Block] x 7 [lines] x 8 [cycle] x (640 /
16) [column]} ≈212 [nsec]. Normally, the cycle time of DRAM is 150ns
Since it is ec, it can be used.

Next, the operation of the display cycle will be described. The upper screen and the lower screen operate at the same timing. The control unit 15 reads the data of the first 16 pixels of the first line from the video RAM 16a and registers it in the register 17a.
It is stored in the memory holding unit A of. Next, the control unit 15 reads the first 16-pixel data of the second line from the video RAM 16 and stores it in the memory holding unit A of the register 17a. Similarly, the control unit 15 sequentially reads pixel data up to the 7th line and stores the pixel data in the memory holding unit. When 7 lines of data are stored in the memory holding unit A of the register 17a, pixel data of 1 bit from each line is serially output to the arithmetic processing unit 9a. At this time,
The orthogonal function stored in the register 8a is given to the arithmetic processing unit 9a. The arithmetic processing unit 9a performs an arithmetic operation on the pixel data and the orthogonal function to perform D / A converter 11 operation.
output to a.

Therefore, while the pixel data is being output from the memory holding unit A to the arithmetic processing unit 9a, the following 16
The first to seventh lines of pixel data are sequentially read from the video RAM 16a and stored in the memory holding unit B. When the serial output of the pixel data from the memory holding unit A is completed, the serial data from the memory holding unit B is output, and the data of the next 16 pixels is stored in the memory holding unit A this time. This operation is repeated. As a result, seven memory read cycles are performed within 212 nsec × 7 = 1484 nsec, and CP is executed in the idle time.
Access from U is permitted. At this time, in order to increase the access time from the CPU, it is necessary to set
Lines need to be accessed at high speed. As a solution to this, there is a method of converting a column address and a row address and using a page mode for accessing 7 lines. As shown in FIG. 3, the control unit 15 converts the row address and the column address to use the page mode in the display cycle to access the DRAM at high speed. By this conversion, the page mode can be used for accessing the data from the first line to the seventh line, and the cycle time is shortened.

Now, the page mode will be described with reference to FIG. In the normal cycle, as shown in FIG. 4A, after -RAS falls to the "L" level,
As shown in (b), -CAS falls to "L" level. In the page mode cycle, -RAS is set to "L" level as shown in FIG.
As shown in (d), the column address can be accessed a plurality of times with respect to the same row address by repeating the "-CAS" -H level and "L" level a plurality of times.

Here, comparing memory read cycles for seven lines in an access time DRAM of 150 nsec, 150 × 7 = 1050 nsec and 150 + 50 ×
At 6 = 450 nsec, the access time is about half. The address conversion is performed by the control unit 15 exchanging the upper 8 bits and the lower 8 bits of the display RAM address.

As described above, the D / A converter 11a converts the supplied digital signal into an analog signal, the upper screen column driver 12a drives the column electrode of the upper screen 14a, and the row data generating circuit 10a causes the register 8a to register. Row data based on the orthogonal function stored in the upper screen 1 is generated by the upper screen row driver 13a.
The row electrode 4a is driven.

The upper screen column drivers 12a, 1
When 2b correspond to digital signals respectively, the D / A converters 11a and 11b are omitted and the 3-bit digital signals are directly supplied from the arithmetic processing units 9a and 9b to the upper screen column driver 12a and the lower screen, respectively. You may make it output to the column driver 12b.

In the above description, one block consists of seven lines, but it is possible to cope with a change in the number of lines.

FIG. 5 is a block diagram showing another embodiment of the present invention. The embodiment shown in FIG. 5 uses special dual-port DRAMs 20a and 20b instead of the video RAMs 16a and 16b of FIG. 1 to permit access from the CPU during the display cycle in the embodiment shown in FIG. It is an improvement of the part that was not done.

FIG. 6 is a block diagram showing the structure of the special dual port DRAM shown in FIG. 6, the dual port DRAM includes an internal timing generation circuit 201, a refresh counter 202, a row address buffer 203, a row decoder 204, and a memory array 2.
05, serial address pointer 206, serial register 207, transfer gate 208, column address buffer 209, column decoder 210, and I / O gate 211.
And sense amplifier 212 and write per bit control unit 213
And a data input / output buffer 214 and a serial input / output buffer 215. Since this dual port DRAM 20 is already known, the description of its operation will be omitted.

In this embodiment, a dual port DRAM
By using 20a and 20b, multi-value display and color display of liquid crystal are possible with a small number of memories. Control unit 1
5 controls the dual port DRAMs 20a and 20b,
A read / write cycle from the CPU is performed. Also,
In the display cycle, the row address and column address at the beginning of one block are transferred in the dual port DRA in the transfer cycle.
This is done by notifying M20a and M20b. CPU
The access from is not accepted only in the transfer cycle for this display cycle and in the refresh cycle. Here, the display cycle will be described. When the serial port address is notified in the transfer cycle, the dual port DRAM 20a transfers the data of the row address of the specified memory array 205 from the row address buffer 203 shown in FIG. 6 to the serial register 207 via the row decoder 204. And store.
A normal dual port RAM stores data of one row address, but the dual port DR shown in FIG.
In the AM 20, the row address data suitable for the size of one block is stored in the serial register 207.
The dual-port DRAM 20 has a memory configuration of 256 bits × 256 bits × 8 bits when it corresponds to monochrome binary, and has a 256-bit × 512-bit × 8-bit memory to correspond to monochrome multi-value (4 bits). In order to correspond to the color (8 bits), the memory structure is 256 bits × 1024 bits × 8 bits. Although FIG. 6 shows the case where monochrome binary is supported, monochrome multi-value and color can be supported if the number of pixels per address changes and the number of bits of the column address increases.

Next, the specific operation of the embodiment shown in FIG. 5 will be described. In the display cycle, 7 lines of data are output from the serial input / output pins of the dual port DRAM 20a. This data is stored in the register 17a
Are stored in the memory and are given to the arithmetic processing unit 9a bit by bit. The arithmetic processing unit 9a calculates the exclusive OR of the pixel data stored in the register 17a and the orthogonal function stored in the register 8a and the sum thereof, and D /
It is given to the A converter 11a. On the other hand, the row data generation circuit 10a generates row data based on the orthogonal function stored in the register 8a, and the upper screen row driver 13a.
Give to.

Similar to the above description, the upper screen column driver 12a drives the column electrodes of the upper screen 14a by the output of the D / A converter, and the upper screen row driver 1 is driven.
3a drives the row electrode.

Here, in the embodiment shown in FIG. 5, the dual port DRAMs 20a and 20b and the registers 17a and 1 are used.
Since the number of pins of 7b becomes very large, consider reducing the number of pins. Therefore, the data from the dual port DRAM is output in a time division manner.

FIG. 7 shows such a dual port DRAM.
It is a block diagram of. The dual port DRAM shown in FIG. 7 has the serial address pointer 2 shown in FIG.
The time-division serial data selector 216 is inserted between 06 and the serial register 207, the serial register 207 is further transferred by the serial clock SC1, and the data is selected by the time-division serial data selector 216 by the serial clock SC2. It was done. The dual port DRAM 21 is
By outputting the data serially in a time-division manner by the time-division serial data selector 216, in the case of monochrome binary, the transfer time of one block of data bits is 93 nsec as described above, but the monochrome multi-value (4
In the case of (bit), one pixel is made up of 4 bits, so that 93/4 takes about 23 nsec. Also, color 8
In the case of bits, since each pixel consists of 8 bits,
The transfer time is about 11 nsec. In the case of color, considering the balance between the transfer speed and the number of pins, by increasing the serial output a little more and making the transfer speed seemingly slow,
There is a prospect of practical application. At this time, the time division unit is built in the registers 17a and 17b of FIG.

FIG. 8 is a block diagram showing still another embodiment of the present invention, and FIG. 9 is a concrete block diagram of the arithmetic processing / memory control section shown in FIG.

In FIG. 8, a VGA controller 23 is provided. The VGA controller 23 supplies a binary liquid crystal display signal whose gradation is controlled to the arithmetic processing / memory control section 25. The arithmetic processing / memory control unit 25 is configured as shown in FIG. 9, and its configuration is almost the same as that in FIG. That is, the control unit 22 writes a binary liquid crystal display signal in the dual port DRAMs 21a and 21b for the upper screen and the lower screen. At this time, the dual port DRAMs 21a, 21
For b, the same address is designated by the control unit 22. Then, the pixel data for the upper and lower screens are serially output for 7 lines from the dual port DRAMs 21a, 21b and given to the registers 17a, 17b. Below, FIG.
In the same manner as in the embodiment of FIG.
The exclusive OR operation of the orthogonal function given by the above and the pixel data and the total operation thereof are performed and given to the upper screen column driver 12a. The exclusive OR operation with the data and the total operation thereof are performed and output to the lower screen column driver 12b. The row data generation circuit 10a generates row data based on the orthogonal function given from the register 8a and outputs the row data to the upper screen row driver 13a, and the row data generation circuit 10b generates the row data based on the orthogonal function from the register 8b. It is generated and output to the lower screen row driver 13b.

FIG. 10 is a block diagram showing still another embodiment of the present invention. The embodiment shown in FIG. 10 corresponds to the special dual port DRAM 21 shown in FIG.
Ordinary dual port DRAM 1 in place of a and 21c
6a and 16b are used, and other configurations are the same as those in FIG.

FIG. 11 is a diagram for explaining a method of writing data in the normal dual port DRAM shown in FIG. As the dual port DRAMs 16a and 16b, monochrome binary 128k × 8 bit storages are used, and pixel data are serially converted to dual port DRAMs by the arithmetic processing / memory control unit 25.
The data is output to 16a and 16b, and serial data is written bit by bit in the same row address. As a result, as shown in FIG. 11, 8-bit data corresponding to an address includes D7 as the first line, D6 as the second line, ...
D1 is mapped on the 7th line, and D0 is mapped so as not to be used.

[0040]

As described above, according to the present invention, by providing a dynamic RAM and some RAM portions in the register, in the case of monochrome binary, a half screen worth of DRAM is provided.
Since only one is required, the power consumption is low, the cost is reduced, the number of parts can be reduced, and the size can be easily reduced. In addition, monochrome multi-valued (4 bits) dual port RA
By adding the function of M, one RAM for half screen
The power consumption can be reduced, the number of parts can be reduced, and the size can be easily reduced. Furthermore, by using the output of the existing liquid crystal controller and adding a circuit, it becomes possible to drive by the active addressing method. Therefore,
Compatibility with existing systems can be easily achieved simply by inserting an additional circuit in the liquid crystal unit.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an area of a register shown in FIG.

FIG. 3 is a diagram for explaining address conversion in the embodiment shown in FIG.

FIG. 4 is a time chart for explaining a page mode and a normal access mode.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a special dual port DRAM shown in FIG.

FIG. 7 is a block diagram of a dual port DRAM that outputs data serially in a time division manner.

FIG. 8 is a block diagram showing still another embodiment of the present invention.

FIG. 9 is a specific block diagram of the arithmetic processing / memory control unit shown in FIG.

FIG. 10 is a block diagram showing still another embodiment of the present invention.

11 is a typical dual port DRA shown in FIG.
FIG. 6 is a diagram for explaining a method of writing data in M.

FIG. 12 is a block diagram of a liquid crystal display device using a conventional active addressing method.

[Explanation of symbols]

 6a, 6b Orthogonal function generator 8a, 8b, 17a, 17b Register 9a, 9b Arithmetic processing unit 10a, 10b Row data generation circuit 11a, 11b D / A converter 12a Upper screen column driver 12b Lower screen column driver 13a Upper screen Row driver 13b Lower screen Row driver 14a Upper screen 14b Lower screen 14 Liquid crystal display device 15 Control unit 16a, 16b Video RAM 20a, 20b Dual port DRAM

Front page continued (72) Inventor Hiroyoshi Toda 22-22 Nagaike-cho Naganocho, Abeno-ku, Osaka, Osaka (72) Inventor Toyoshi Horikawa 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Prefecture

Claims (6)

[Claims] 1. A simple matrix liquid crystal display device in which electrodes are arranged in a plurality of rows and a plurality of columns, wherein the electrodes of a plurality of rows are selected and driven at the same time. Dynamic random access memory for storing pixel data of one screen to be displayed on a display, a first storage holding unit for storing pixel data of a plurality of lines read from the dynamic random access memory, and the first Register means having a second memory holding portion for storing pixel data of a plurality of lines while displaying the pixel data stored in the memory holding portion, orthogonal function generating means for generating an orthogonal function, Pixels for a plurality of lines output from the first or second memory holding unit of the register unit and the orthogonal function generated by the orthogonal function generating unit Calculating means for performing an exclusive OR with the data and its total calculation, a column driving means for simultaneously driving the column electrodes of the simple matrix liquid crystal display in accordance with the calculation result of the calculating means, and the orthogonal function generating means. A multi-line simultaneous drive liquid crystal display device comprising row drive means for simultaneously driving the row electrodes of a plurality of lines of the simple matrix liquid crystal display based on the orthogonal function output from the above. 2. The multi-line simultaneous drive liquid crystal display device according to claim 1, further comprising an address conversion means for converting a row address and a column address of the dynamic random access memory. 3. The multi-line simultaneous driving liquid crystal display device according to claim 1, wherein the dynamic random access memory includes a dual port dynamic random access memory. 4. The multiple line simultaneous drive liquid crystal display device according to claim 3, wherein the dual port dynamic random access memory outputs the pixel data serially in a time division manner. 5. The multi-line simultaneous drive liquid crystal display device according to claim 1, further comprising a writing means for writing a plurality of values of pixel data of which gradation is controlled in said dynamic random access memory. 6. The multi-line simultaneous driving liquid crystal display device of claim 5, wherein the dynamic random access memory includes a dual port dynamic random access memory.