JPH09244594A - Liquid crystal display driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display driving circuit in which storage capacity of a storage device can be reduced and the number of times of access of data to a storage device of a CPU can be decreased in gradation display. SOLUTION: In this circuit 1, when display data of, for example, 3 bits (8 gradations) is supplied from a signal source, a CPU 2 stores this display data of 3 bits in a memory 3, successively, data of lower-order bits, intermediate- order bits, and upper-order bits of this display data of 3 bits is respectively stored in a first frame memory, a second frame memory, and a third frame memory of, a frame memory 4. And in a liquid crystal display panel 13, a second frame in which intermediate-order bits of display data are displayed is displayed with length of two times of a first frame in which lower-order bits are displayed, while a third frame in which upper-order bits of display data is displayed with length of four times of a first frame.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display drive circuit, and more particularly to a liquid crystal display drive circuit for displaying gray scales.

[0002]

2. Description of the Related Art Recently, liquid crystal display devices perform not only binary display of white and black but also multi-gradation display for displaying an intermediate state between "white" and "black" with the spread of liquid crystal. This improves the sense of reality.

It is called the number of gradations whether this intermediate state is divided into several levels. The larger the number of gradations, the more various images can be represented.

For such high gradation display, conventionally, for example, when an STN (Super Twisted Nematic) type liquid crystal cell is used, the liquid crystal is displayed when one display data is displayed with a plurality of frames as one cycle. Frame decimation method FRC which expresses gradation by changing the number of times of lighting
(Frame Rate Control) is used.

[0005]

However, in the liquid crystal display drive circuit adopting the conventional frame thinning method, as the display data has a high gradation, the required frame memory is increased and the storage is increased. There is a problem that the cost required for the device is high.

Further, there has been a problem that the number of accesses by which the CPU writes and reads the display data into the storage device increases as the display data has a higher gradation.

The present invention has been made in view of the above problems, and it is possible to reduce the storage capacity of the storage device and the number of times data is accessed to the storage device of the CPU when performing high gradation display. The present invention aims to provide a liquid crystal display driving circuit.

[0008]

According to another aspect of the present invention, there is provided a liquid crystal display drive circuit, wherein gray scale data of one pixel is represented by n as display data.
A memory for storing a binary number of bits, n frame memories for storing the n-bit display data for each bit in association with a pixel, and displaying a frame corresponding to the least significant bit of the display data. With respect to the timing, with respect to the frame in which the m-th bit of the display data is displayed, there is provided control means for giving a display timing having a length of 2 (m-1) th power.

That is, according to the liquid crystal display device of the first aspect, first, the gradation data of one pixel is stored in the memory as display data in an n-bit binary number, and then in the n frame memories. , The n-bit display data stored in the memory is stored for each bit in association with each pixel, and the control means stores the display data with respect to the display timing of the frame corresponding to the least significant bit of the display data. For a frame in which the mth bit of
Gives the display timing of the length of the square.

Therefore, it is possible to reduce the storage capacity of the storage device of the liquid crystal display drive circuit and the number of times of data access to the storage device of the CPU.

Further, in this case, like the liquid crystal display drive circuit according to claim 2, the memory has 3 bits (8 gradations).
Display data is stored, and the lower bit, the middle bit, and the upper bit of the 3-bit display data stored in the memory are stored in the first frame memory, the second frame memory, and the third frame memory, respectively. The control means displays the second frame, in which the middle bit of the display data is displayed, twice as long as the first frame in which the lower bit is displayed, while displaying the upper bit of the display data. It is effective to display the third frame which is four times as long as the first frame.

That is, according to the liquid crystal display drive circuit of the second aspect, the memory stores the display data of 3 bits (8 gradations), and the first frame memory, the second frame memory, and the third frame memory. Respectively stores the lower bit, the middle bit, and the upper bit of the 3-bit display data stored in the memory, and the control means stores the lower frame in the lower frame in which the middle bit of the display data is displayed. The bit is displayed twice as long as the first frame, while the third frame in which the upper bits of the display data are displayed is displayed four times as long as the first frame.

Therefore, when 8 gradations are displayed by 3-bit data, it is possible to reduce the storage capacity of the storage device of the liquid crystal display drive circuit and the number of times of data access to the storage device of the CPU.

Further, in this case, as in the liquid crystal display drive circuit according to claim 3, the memory has 2 bits (4 gradations).
Display data is stored, the lower bit and the upper bit of the 2-bit display data stored in the memory are stored in the first frame memory and the second frame memory, respectively, and the control means stores the upper bit of the display data. The second frame in which the bits are displayed is the first frame in which the lower bits are displayed.
It is effective to display the frame twice as long.

That is, according to the liquid crystal display drive circuit of the third aspect, display data of 2 bits (4 gradations) is stored in the memory, and 2 bits each are stored in the first frame memory and the second frame memory. The control unit stores the lower bit and the upper bit of the display data, and the control unit displays the lower bit in the second frame in which the upper bit of the display data is displayed.
Display at twice the length of the frame.

Therefore, when four gradations are displayed by 2-bit data, it is possible to reduce the storage capacity of the storage device of the liquid crystal display drive circuit and the number of times of data access to the storage device of the CPU.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the concept of the present invention will be described with reference to FIGS.
It is shown using. Conventionally, in order to perform gradation display by the frame thinning method, a plurality of frames corresponding to a display screen are prepared, and regarding display of each pixel, “1” is considered to be lighting of a selected pixel, and “0” is considered not lighting. Then, the effective voltage applied to the liquid crystal is changed according to the number of "1" stored corresponding to each pixel of each frame, and gradation display is performed.

For example, in order to display 4-gradation data, 1-bit data corresponding to each gradation is stored in three frames for each pixel as shown in FIG. In the case of 8 gradations, 1-bit data is stored in 7 frames as shown in FIG.

Here, as shown in FIGS. 2 and 4, when the allocation of "1" and "0" data to each frame is defined, some frames have exactly the same data. That is, in FIG. 2, the second frame and the third frame
It is the same as the frame, and in FIG.
The two frames are the same, and further, the third, fifth, and sixth
And the 7th four frames have the same data.

Therefore, if the same data is shared, in the case of 4 gradations, as shown in FIG.
If there is frame data, it will be sufficient, and if there are 8 gradations, then there will be enough data for the first, second and third frames as shown in FIG.

On the other hand, if the display data has 4 gradations, the gradations 0 to 3 are represented by a 2-bit binary number, and if the display data is 8 gradations, the gradations 0 to 7 are represented by a 3-bit binary number. . The relationship between this binary number and the frame data is as shown in FIGS. 2 and 4, and it can be seen that the two match.

Focusing on this point, the present invention develops the display data (gradation pixel data) in the frame memory as it is, and controls the display time length of the frame memory to drive the liquid crystal as obtained by the frame thinning method. It is intended to create an effective voltage value and display a gradation.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a liquid crystal display drive circuit 1 according to an embodiment of the present invention. In particular, in the present embodiment, an example in which display data of 4 gradations (2 bits) is displayed with 2 frames as one cycle, and 8 gradations (3
An example is shown in which display data of (bit) is displayed with three frames as one cycle. FIG. 6 is a timing diagram when displaying display data of 4 gradations (2 bits). FIG.
FIG. 6 is a timing chart of signals of respective parts when displaying display data of 8 gradations (3 bits).

In FIG. 1, the liquid crystal display drive circuit 1 has a C
PU 2, memory 3, frame memory 4, data reading circuit 5, frame number register 6, frame counter 7, matching circuit 8, LCD control circuit 9, timing signal generating circuit 1
0, a scan electrode drive circuit 11, a signal electrode drive circuit 12, and a liquid crystal display panel 13.

As the liquid crystal display panel 13, a simple matrix type liquid crystal display panel is used here, and a plurality of scanning electrodes (common electrodes) X1 to Xn and a plurality of signal electrodes (segment electrodes) Y1 to Ym are used. STN (Super Twis
ted Nematic) are arranged opposite to each other with a liquid crystal layer in between, and are arranged in a matrix. Then, the scan electrodes X1 to Xn are sequentially scanned by the scan signal and the display signal supplied from the scan electrode drive circuit 11 and the signal electrode drive circuit 12 described later.
The signal electrodes Y1 to Ym are selectively driven, and gradation display according to display data is performed. Here, the display data is 4
In the case of gradation (2 bits), gradation is displayed according to the display data with 2 frames as one cycle, while when the display data is 8 gradations (3 bits), 3 frames are 1
Grayscale display according to display data is performed as a cycle.

The scan electrode drive circuit 11 is an LCD described later.
The scan signal is sequentially output to the scan electrodes X1 to Xn based on the scan timing signal CK2 as shown in FIG.
To Xn are sequentially selected and driven.

The signal electrode drive circuit 12 is supplied from the LCD control circuit 9, for example, the scanning timing signal CK2 shown in FIG. 7B, and the timing signal generation circuit 10 is supplied with a clock signal shown in FIG. 7A, for example. A display signal corresponding to the binary data supplied from the data read circuit 5 is supplied to the signal electrodes Y1 to Ym based on CK1.

The timing generation circuit 10 is based on the scanning timing signal CK2 as shown in FIG. 7B supplied from the LCD control circuit 9, and the clock signal C as shown in FIG. 7A.
K1 (m read clocks for one line signal electrode) is generated and supplied to the read circuit 5 and the signal electrode drive circuit 12. Further, the timing generation circuit 10 is based on the scanning timing signal CK2 as shown in FIG. 7B supplied from the LCD control circuit 9, and the frame timing signal CK3 as shown in FIG. A signal that is output after counting several n) is generated and supplied to the frame counter 7.

The CPU 2 stores display data supplied from a signal source (not shown) in the memory 3, and the liquid crystal display panel 7
In the case of displaying at, the display data stored in the memory 3 is stored in a plurality of frame memories of the frame memory 4 in units of binary data (1 bit).

For example, in the case of 4-gradation (2-bit) display data, the display data represented by a 2-bit binary number stored in the memory 3 is converted into two frame memories (frame 1, frame 1) of the frame memory 4. 2) binary data (1
Store in bit units. Also, 8 gradations (3 bits)
In the case of the display data of, the 3-bit data is stored in the three frame memories (frame 1, frame 2, frame 3) of the frame memory 4 in units of binary data (1 bit).

The data read circuit 5 reads binary data from the corresponding frame memory of the frame memory 4 in response to the clock signal CK1 and the like as shown in FIG. It is supplied to the electrode drive circuit 12.

The frame number register 6 is a register for storing the data of the number of frames of the frame memory 4 for storing the display data. When the display data of 4 gradations is displayed on the liquid crystal panel 13, the number of frames is displayed. “2” is stored as data, and display data of 8 gradations is displayed on the liquid crystal panel 1.
When displaying in 3, "3" is stored as the frame number data.

The frame counter 7 supplies a count value obtained by counting the frame signal CK3 as shown in FIG. 7C supplied from the timing signal generation circuit 10 to the coincidence circuit 8 and the LCD control circuit 9. Then, the counter value of the frame counter 7 is reset by the reset signal R supplied from the coincidence circuit 8.

The coincidence circuit 8 supplies a reset signal R to the frame counter 7 when the counter value supplied from the frame counter 7 and the frame number data stored in the frame number register 6 match, and The counter value of the counter 7 is reset and set to "0".

The LCD control circuit 9 includes a frame counter 7
The data output cycle is changed according to the frame counter value supplied from. In this case, when the frame counter value is "0", the scanning timing signal CK2 is output in the cycle of T1 in order to display the frame 1, and when the frame counter value is "1", the frame 2 is displayed. The scanning timing signal CK2 is output at a cycle twice that of T1, and when the frame counter value is "2", the scanning timing signal CK2 is output at a cycle T3 which is four times T1 in order to display frame 3. Configure. Further, the LCD control circuit 9 generates a scanning timing signal CK2 as shown in FIG. 7B in accordance with each frame based on the counter value supplied from the frame counter 7, and the timing signal generation circuit 10 and the scanning signal CK2 are generated. It is supplied to the electrode drive circuit 11 and the signal electrode drive circuit 12.

Next, the operation of displaying the display data of 8 gradations (3 bits) on the liquid crystal display panel 13 will be described with reference to the timing chart of FIG.

The 8-gradation 3-bit binary display data stored in the memory 3 is expanded and stored in the frame memory 4 according to the relationship shown in FIG. And frame 1
When the time for displaying the data of T1 is T1, the frame 2 is displayed for a time T2 that is twice the length of T1, and the frame 3 is displayed for a time T3 that is four times the length of T1. As a result, a liquid crystal driving effective voltage similar to that displayed by the frame thinning method is obtained.

That is, when the scanning timing signal CK2 is output from the LCD control circuit 9 in the state (A) of FIG. 7 (while the n-2th row of the frame 3 is being displayed), the timing signal generation circuit which receives the scanning timing signal CK2 10 generates m clock signals CK1 corresponding to the number of signal electrodes, and the data of the nth row of the frame 3 is taken into the signal electrode drive circuit 12.

At the same time, the signal electrode drive circuit 12 drives the signal electrodes based on the previously fetched data of the (n-1) th row. At this time, the data reading circuit 5 switches to the designation of the frame 1 since the reading of the frame 3 is completed.

Next, the LCD control circuit 9 measures a predetermined time and at the timing of (i), the next scanning timing signal CK.
When 2 is generated, the data read circuit 5 reads the data of the first row of frame 1 and supplies it to the signal electrode drive circuit 12. At this time, the signal electrode drive circuit 12 is driving to display the data of the last row of the frame 3 previously fetched.

In this state, the frame counter 7 is counting "2", the LCD control circuit 9 outputs CK2 in the cycle of T3, and the liquid crystal display panel 14 displays the last line of the frame 3 at this time. Scanned in long.

The timing signal generation circuit 10 outputs the frame timing signal CK3 at the timing of (U) when counting n scanning timing signals CK2. As a result, the frame counter 7 becomes "3", but this value is judged by the matching circuit 8 to match the content of the frame number register 6, and as a result, it becomes "0" by resetting. Therefore, the LCD control circuit 9 switches the cycle from T3 to T1 after generating the scanning timing signal CK2 at the timing of (e), and corresponds to the display of the frame 1.

Therefore, after (e), the display of the frame 1 is scan-driven in the cycle of T1, and when the display of the frame 1 is completed, the frame 2 is similarly scan-driven in the cycle of T2, and thereafter, the frame 3 is driven. Is driven in the cycle of T3, the effective voltage for each pixel as described above is obtained, and 8-gradation display is performed.

In the case of 4-gradation display, "2" is written in the frame number register 6 and the display data is written in the frames 1 and 2, but the display operation is the same as that described above. , Frame 1 has a cycle of T1, frame 2
Will be driven in the cycle of T2 (see FIG. 6).

As described above, in the present embodiment,
When displaying 8-gradation (3-bit data) display data, the 3-bit display data is first stored in the memory 3, and then the low-order bit, the middle-order bit of the 3-bit display data stored in the memory 3, And the upper bit data are stored in the first frame, the second frame, and the third frame of the frame memory 4, respectively, and the second frame is stored in the first frame.
This is a configuration in which the liquid crystal panel 13 displays the second frame and the third frame four times as long as the first frame.

In the case of displaying 4-gradation (2-bit) display data, the 2-bit display data is first stored in the memory 3, and then the display data (2-bit) stored in the memory 3 is stored. Each of the data of the lower bit and the upper bit is stored in the first frame and the second frame of the frame memory 4, respectively, and the second frame is displayed on the liquid crystal panel 13 in a display time twice as long as that of the first frame. is there.

That is, when displaying display data of m gradations (n bits), first, display data of n bits is stored in the memory 3.
Then, each bit data of the n-bit display data stored in the memory 3 is stored in each of the n frame memories corresponding to the pixel, and the frame in which the m-th bit is displayed is stored in the lowest order. The liquid crystal display panel 13 is configured to display the bit (Bit 0) in a display time that is 2 (m-1) times the frame in which the bit is displayed.

Therefore, the capacity of the frame memory can be reduced, and the number of times of writing and reading data to and from the frame memory can be reduced.

In the above embodiment, an example of displaying 2-bit (4 gradations) or 3-bit (8 gradations) display data has been shown, but the present invention is not limited to this. For example, it is also applicable when displaying display data of 4 bits (16 gradations) or 5 bits (32 gradations).

In the above embodiment, the STN liquid crystal is used as the liquid crystal, but the present invention is not limited to this, and for example, the TN liquid crystal may be used.

Further, in the above-mentioned embodiment, an example of monochrome display has been described, but it goes without saying that the present invention is also applicable to color display.

[0053]

According to the liquid crystal display drive circuit of the first aspect, n-bit display data is stored in the memory, and then,
With respect to the n-bit display data stored in the memory 3, each bit data is stored in each of n frame memories corresponding to pixels, and the frame in which the m-th bit is displayed is the frame in which the least significant bit is displayed. The liquid crystal display panel has a structure in which the display time is multiplied by 2 (m-1) times. Therefore, the storage capacity of the storage device of the liquid crystal display drive circuit is reduced and C
It is possible to reduce the number of times data is accessed to the PU storage device.

Further, according to the liquid crystal display drive circuit of the second aspect, when displaying 8 gradations by 3 bit data, the storage capacity of the storage device of the liquid crystal display drive circuit is reduced and the storage capacity of the CPU is increased. It is possible to reduce the number of times data is accessed.

Further, according to the liquid crystal display drive circuit of the third aspect, when displaying four gradations by 2-bit data, the storage capacity of the storage device of the liquid crystal display drive circuit is reduced and the storage device of the CPU is reduced. It is possible to reduce the number of times data is accessed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a liquid crystal display drive circuit according to an embodiment.

FIG. 2 is a combination diagram of each frame in the case of performing the conventional 4-gradation display.

FIG. 3 is a combination diagram of each frame in the case of performing 4-gradation display according to the present embodiment.

FIG. 4 is a combination diagram of each frame when the conventional 8-gradation display is performed.

FIG. 5 is a combination diagram of each frame in the case of performing 8-gradation display in the present embodiment.

FIG. 6 is a schematic diagram of the liquid crystal display drive circuit of FIG.
(Bit) Display data when displaying display data.

FIG. 7 is a timing chart of signals of respective parts when displaying display data of 8 gradations (3 bits) in the liquid crystal driving device of FIG.

[Explanation of symbols]

 1 Liquid Crystal Display Driving Circuit 2 CPU 3 Memory 4 Frame Memory 5 Data Reading Circuit 6 Frame Number Register 7 Frame Counter 8 Matching Circuit 9 LCD Control Circuit 10 Timing Signal Generating Circuit 11 Scan Electrode Driving Circuit 12 Signal Electrode Driving Circuit 13 Liquid Crystal Display Panel

Claims (3)

[Claims] 1. Gray scale data for one pixel is displayed as n as display data.
A memory for storing a binary number of bits, n frame memories for storing the n-bit display data corresponding to each pixel for each bit, and a display of a frame corresponding to the least significant bit of the display data. With respect to the timing, with respect to the frame in which the m-th bit of the display data is displayed, a control means for giving a display timing of a length of (m-1) to the power of 2, and a liquid crystal display, Drive circuit. 2. The display data of 3 bits (8 gradations) is stored in the memory, and the lower bit, middle bit and upper bit of the display data of 3 bits stored in the memory are respectively The first frame memory, the second frame memory, and the third frame memory are stored, and the control unit controls the second frame in which the middle bit of the display data is displayed and the second frame in which the lower bit is displayed. 2. The liquid crystal display driving circuit according to claim 1, wherein the third frame in which the upper bits of the display data are displayed is displayed four times as long as the first frame while the display is performed with double the length. . 3. The display data of 2 bits (4 gradations) is stored in the memory, and the lower bit and the upper bit of the display data of 2 bits stored in the memory are respectively the first frame memory and the first frame memory. It is stored in a two-frame memory, and the control means displays the second frame in which the upper bits of the display data are displayed with a length twice that of the first frame in which the lower bits are displayed. Claim 1
The liquid crystal display driving circuit as described in the above.