JPS622298A - Display control system for liquid crystal display crt controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention uses a CRT controller (CRTC) that exclusively controls a cathode ray tube (CRT).
The present invention relates to a two-screen display system using a CRTC that can control not only a CRT but also a liquid crystal panel (LCD).

In a CRT display device using the raster scan method, the raster is scanned from the upper left to the lower right of the screen, approximately 200 lines at a time, and the address of the video RAM (VRAM) corresponding to the pixel position of each scanned screen is set on the screen. It is accessed only once per scan. On the other hand, liquid crystal display (LC)
D) Due to the characteristics of the panel, there is a phenomenon in which the brightness of 9 characters becomes extremely low unless raster scanning is performed once every 100 lines or so.

The present invention applies an offset to the VRAM address output by the CRTC so that two corresponding pixels in each of the upper and lower half areas of the nine screen screens are simultaneously displayed per one screen scan by the CRTC, and the corresponding two pixels in the other half areas are displayed simultaneously. A VRAM address corresponding to the pixel position is generated. Namely.

It has a circuit means that selects a VRAM memory address output from the CRTC and an address obtained by multiplying the address by an offset, and supplies the two selected resultant addresses to the VRAM, and supplies the output data of the VRAM to a character generator.

Two character pattern data corresponding to the memory address and an address obtained by applying an offset to the memory address are generated and latched respectively, and the CRTC
A CRTC is characterized in that a character pattern is generated on an LCD panel twice in each of the upper and lower halves of the screen per one scan of one screen using control signals such as a horizontal synchronization signal and a vertical synchronization signal generated from the LCD panel. We provide a two-split screen display method using the following methods. Even if CRTC is used in this way.

1 character corresponding to both the memory address and its offset address on the LCD panel.
Because they are displayed simultaneously within the screen scan.

This has the effect that the characters are not displayed too faintly.

[Industrial application field]

CR as a display device for personal computers
Although T-displays are commonly used, there is a need for the ability to connect to LCD panels. In this case, CR
The T controller is also required to control the display on the LCD panel.

The present invention not only controls CRT, but also controls liquid crystal LC.
Video RAM where CRTC corresponds to pixels in either the top or bottom half of the screen so that the D panel can also be controlled
When accessing the (VRAM) address, the CRTC outputs a V
By applying an offset to the RAM address,
Screen 2 using CRTC that can control both CRT and LCD
Regarding split display method.

[Conventional technology]

Raster scan type CRT display device uses CPU
In addition to decoding commands from the interface section and keyboard section, it can store received data in the VRAM memory section, transfer data read from the memory section to the CPU via the interface, and also control editing of two display screens. It has a control unit that can do this.

The VRAM memory stores one screen worth of display data, and sequentially reads out the display data from this memory, converts one character code into a character pattern, and generates a video signal for forming two characters. Therefore, in order to drive the deflection circuit of one display section, horizontal and vertical synchronization signals must be generated in the synchronization generator. Therefore, CRT
C has an address generation section that can access VRAM addresses in a random manner, and also has a function of generating the horizontal and vertical synchronization signals. In addition, in the raster scan method, a set of deflection circuits for the X and Y axes is used to perform high-speed horizontal scanning similar to a television, and the brightness is controlled by the video signal to control characters. Horizontal scanning has the function of scanning from the upper left corner of the screen to the lower right corner at once.

On the other hand, in an LCD device, there is a limit to the number of lines that can be displayed in one display scan due to the characteristics of the liquid crystal panel.In a CRT, horizontal scanning is possible up to about 200 lines, but in an LCD panel.

The limit is about 100 lines. Therefore, conventionally 20
Even if an LCD panel was scanned using a CRTC that performs control such that about 0 lines are scanned at a time, a high-quality display could not be obtained.

[Problem that the invention seeks to solve]

In order to eliminate such conventional drawbacks, the present invention
Multiply the offset to the memory address where the TC occurs by 1
One point on the top half of the screen and one point on the bottom half can be displayed at the same time.

CRTC is a control circuit that displays each pixel twice in one scan.
CRT and LCD using CRTC.
The present invention provides a two-screen display system that allows control of both.

According to the present invention, not only the CRT but also the LCD can be controlled using the CRTC, so the cost performance of the CRTC is improved, and even if the CRTC is used in place of the LCD controller, the same effect can be achieved per horizontal scan of 100 lines. Since each pixel is always displayed once, each pixel will not be displayed dimly. Therefore, a personal computer or the like that can be connected to both a CRT and an LCD panel can be realized at low cost.

[Means for solving problems]

Generates memory addresses and horizontal synchronization signals.

CR that generates vertical synchronization signal, display period instruction signal, etc.
a VRAM that receives an address generated from the selection means;
Character generation means inputs RAM output data, and control signals such as the horizontal synchronization signal, vertical synchronization signal and display period instruction signal are input, and display data generated from the character generation means is inputted to the top or bottom of two screens. By simultaneously scanning a pixel designated according to the memory address in one half region of the memory address and a pixel designated by the offset address on the other half region simultaneously, two characters are simultaneously generated per screen scan. It has video control circuit means for controlling the video.

[For production]

The present invention provides VRAM data that is read from a memory address by adding an offset to the memory address generated from the CRTC.

The VRAM data specified by the offset address is given to each character generator in a time-sharing manner, and each character generated from the character generator is controlled based on control signals such as a horizontal synchronization signal and a vertical synchronization signal generated from the CRTC. Thus, both the character corresponding to the memory address and the character corresponding to the offset address are displayed simultaneously within one screen scan.

〔Example〕

Hereinafter, two embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit configuration diagram according to the two-screen split screen display method using the CRTC of the present invention. CRTCI is a circuit that generally controls a CRT display device that uses a cathode ray tube. As for the CRT spot scanning method, character displays use the same rask scan method as for television broadcasting, as shown in FIG. 2(a). CRTCI follows this Rusk scan method.
It is a controller and troller of RT. In this case, the code for the character or symbol to be displayed is written from the CPU to the VRAM 4 via the keyboard or interface. Then, in synchronization with the horizontal and vertical scanning of the CRT, the V
When the address of the RAM 4 is scanned and the address is given to the VRAM 4, the code and rask address stored in the VRAM 4 are added to the character generator≦ and converted into dot data constituting a character. The signal is amplified by a video amplifier and then
is applied to the cathode or grid and intensity modulated to display two characters or symbols on a display device. therefore,
Such a CRT controller generates a memory address MA to access the video RAM or VRAM4, and also generates a horizontal synchronization signal (H3YN
C) and a vertical synchronization signal (VSYNC).

This horizontal synchronization signal is a signal that is output every time one screen is scanned horizontally, and the vertical synchronization signal is a signal that is output every time one screen is scanned. Also.

1 display period indication signal (DISPTMG) from CRTC
This signal is a control signal that becomes logic 1 only during the period when nine screens are displayed.

The present invention uses the CRTCI, which is a controller that controls only the CRT, to control the liquid crystal panel, that is, the LC.
A circuit as shown in FIG. 1 is added to the output section of the CRTC 1 so that the D panel device can also be controlled. As shown in FIG. 2(b).

By dividing the screen into two parts and displaying characters at the same time in each of the upper and lower halves of the screen during one scan of 8 screens, the CRTC
The LCD device can also be controlled using I. for that.

Input the memory address MA generated from the CRTC1, and as shown in FIG. 2(C) and (d),
An offset address generation circuit 2 is provided which generates an offset address for accessing a pixel corresponding to the upper or lower half area of the screen when the address is an address for accessing a pixel corresponding to the upper or lower half area of the screen. The memory address MA and the offset address are input, and the memory address MA 13, the offset address 20, or the Selection circuit 3 for selecting address 30 from CPU. and a VRAM 4 to which the output 31 of the selection circuit 3 is input as an address signal. Furthermore, the output data 40 from the VRAM 4 is input to the character generator 5 as part of the address, and
The signal output from I is input to the character generator 5 as a rask address 42 via a rask address conversion circuit 41, and the output 50 of the character generator 5 accessed by the output data 40 and the rask address 41 is used for video control. It is input to circuit 6.

This video control circuit 6.

Each control signal of a horizontal synchronization signal 10°, a vertical synchronization signal 11 and a display period instruction signal 12 output from the CRTCI is input, and the display period instruction signal 12 is in a logic 1 state;
In other words, CRTCI has one screen.

While controlling the spot scan from the upper left corner to the lower right corner of the screen, two characters, a character corresponding to the memory address MA13 and a character corresponding to the offset address 20, are displayed on the display device, especially the LCD. Output to the panel device 7. and,
While the CRTCI itself accesses VRAM4 for 1 byte, it forcibly applies an offset of 1 so that it can access 2 bytes.

The timing generation circuit 8 supplies the CRTCI with a basic clock (
CRTCCLK) and at the same time, this CRTCCCL
The K signal is also given to the selection circuit 3. Furthermore, a signal CRTS I DB times the signal which becomes a pulse once during each period of the basic clock CRTCCLK signal and is delayed by half a cycle from the basic clock CRTCCLK is also provided to the selection circuit 3 .

Using these signals, the 2 selection circuit 3 selects either the memory address MA generated from the CRTCI or the offset address signal 20 generated via the offset generation circuit 2 as the address of the VRAM 4, and selects the memory address 13 as the address of the VRAM 4. or offset address 20 in time-sharing VR
It is given to AM4. The corresponding codes outputted from the VRAM 4 are given to the character generator 5 in a time-sharing manner. At this time, VRAM4 has one word for each pixel on one screen, so
The number of characters displayed on one screen of the LCD and the number of words of the VRAM are the same. Therefore, corresponding to the case where one screen is divided into upper and lower halves, the VRAM address space is divided into a lower address area and an upper address area depending on the logical state of 0 or 1 of the most significant bit of the address signal 31 applied to the VRAM4. It will be divided into two parts.

Therefore, when the most significant bit of the address is "0", a positive offset is applied by the offset circuit 2,
When the most significant bit is "1", a negative offset is applied. In addition.

A VRAM may be configured with a lower chip and an upper chip corresponding to the two divided address areas. In this embodiment, the output of the 2 selection circuit 9 is applied to the VRAM 4 as a chip select signal via a selection circuit 9 that selects chip select signals 80 and 82 for the MA address and VRAM offset address of the VRAM 4. . At this time.

A control signal 83 for selecting the input chip select signal of the selection circuit 9 is provided from the timing generation circuit 8. In this case, when one of the two memory chips making up the VRAM 4 is enabled, the other is disabled. Current consumption can be reduced by using a memory chip that enters a power-down mode when disabled.

The operation of each circuit in the circuit configuration diagram of FIG. 1 will be explained with reference to the timing chart of FIG. 3.

In the timing chart of FIG. 2, waveform A is.

Timing generation circuit 8 to CRTCI and selection circuit 3
This is the basic clock CRTCCLK signal given to the.

Waveform B is a clock (CRTS IDE) obtained by delaying the CRTCCLK clock of waveform A, and is a rectangular wave that becomes a pulse between two consecutive falling edges of the CRTCCLK signal, that is, within one cycle period. C
RTCI is.

Since a memory address is generated starting from each falling edge of the basic clock CRTCCLK, as shown in the memory address signal of waveform C, MA a and MA + are generated in each cycle of the CRTCCLK signal, respectively.

It generates memory addresses such as MA2 and MA2.

In each cycle of each CRTCCLK, the memory address MA generated from CRTCI is
Therefore, offset addresses 0FFAO, 0FFI, and 0FF2 as shown in the waveform are generated starting slightly later than each MA address, but are generated one by one in the same CRTCCLK cycle. These address signals C and D are respectively M
Select circuit 3 as A address and offset address
is input. In the selection circuit 3, the CRTC of waveform A
The memory address MA of waveform C is output to the output line 31 in the period from the falling edge of CLK to the falling edge of the CRTS I DE times signal of waveform B, that is, in the first half of each cycle of CRTCCLK.

On the other hand, the period from the falling edge of the CRTS IDE signal of waveform B to the falling edge of CRTCCLK of the next waveform A,
That is, in the latter half of each cycle of CRTCCLK of the waveform A, the offset address signal having the waveform is applied to the selection circuit 3.
It is outputted to the output 31 in a time-division manner. Therefore, VR
AM4 inputs these address signals, that is, the MA address and the offset address, in a time-sharing manner in the first half cycle and the second half cycle of each cycle of CRTCCLK, respectively, so that the data corresponding to the MA address, (for example, @31” in 1-byte ophthalmic display
) and data corresponding to the offset address (for example, "32" in ophthalmic representation) are output to the output 40 of the VRAM 4, respectively.

During the period when VRAM4 is accessed by MA address and offset address respectively.

The chip select signal output from the selection circuit 9 is as follows.

Either a VRAMMA address chip select signal 80 or a VRAM offset address chip select signal 82 generated from timing generation circuit 8 is applied, and these have waveforms as shown in waveforms E and F, respectively. MA address chip select signal E is C of waveform B.
This signal is activated to logic 0 when the RTS I DE signal pulse is output, and is activated to logic 0 when the CRTCCLK pulse shown in VRAM offset address chip select signal F signal waveform A is generated. .

When VRAM4 has an MA address generated,
It becomes enabled in the second half of the first half cycle of the basic clock CRTCCLK.

On the other hand, if the offset address is output, C
It is enabled in the second half of the second half of each period of RTCCLK. therefore.

From VRAM4, the data specified by the MA address is
It is output at the timing shown in waveform G.

On the other hand, the output data of VRAM4 specified by the offset address, that is, the offset address data has a waveform of H
It is output at the timing shown in . The MA data from the VRAM 3 and the offset address data shown in waveform H, which are output according to the timing shown in waveform G, are given as addresses to the character generator 5 in a time-sharing manner, and the corresponding character data 50
is output. The character data corresponding to the MA address data and the character data corresponding to the offset address data are stored in the latch circuit in the video control circuit 6 with the UPLCK clock shown in the waveform ◯ and the L P shown in the waveform J. , LCK are latched at the rising edge of the clock. In other words, with waveform ■, M
Latch A data.

Latch the offset data with waveform J. Each character is simultaneously displayed at one point in the upper half of the screen and one corresponding point in the lower half of the screen on the LCD panel via a panel drive circuit.

Incidentally, if the number of lines that can be displayed on one screen is an even number, does the output address of the CRTC point to the upper half of the screen?

It is sufficient to determine whether the lower half is pointed to and add or subtract the offset value to the output address of the CRTC, but if the number of display lines is an odd number, it is not enough to simply add or subtract one type of offset value. cannot be displayed. The reason for this will be explained below.

Assume that one character is composed of a pattern of 4 dots x 4 dots as shown in FIG. 4(a). Also.

On one screen of the display, there are two characters × as shown in Figure 4 (b).
Assume that seven lines can be displayed.

Note that ① to ② in FIG. 4(b) indicate addresses output from the CRTC.

For example, if the CRTC outputs address l and is scanning the first line of the corresponding character pattern, then 9
According to the present invention, the third line of the character pattern corresponding to address 7 on the lower half of the screen is scanned. Therefore, the offset value is +6. On the other hand, when scanning the third line of the character pattern corresponding to address 1, the first line of the character pattern corresponding to address 9 is scanned. In other words, the offset value is +8. Therefore, two types of offset values are required as indicated by the arrows in FIG. 4(b). The relationship between the CRTC address and offset value in FIG. 4(b) is as follows.

Examples of offset circuits that enable such offset value control are shown in FIGS. 5(a) and 5(b).

Next, regarding the offset generation circuit 2 that offsets the memory address MA output by the CRTCI in the two-screen display system using the CRTC of the present invention, the fifth
This will be explained using Figure (al).

Here, it is assumed that an 8 dot x 8 dot character is displayed on an LCD panel capable of displaying 620 dots x 200 dots. Therefore, 80 characters x 4 lines will be displayed.

Furthermore, the rask address given to the character generator is 3 bits (RAo to RA2).

The offset value in this case is as follows.

When CRTC memory address MA points to the upper half of the screen, if RA2="O", offset value = +
311. If RA 2 = ``1'', the offset value - 13
It is 37.

On the other hand, if the memory address MA of the CRTC points to the lower half of the screen and RA="O", the offset value=", 337
．． If RA 2 = “1”, offset value = +331
It is.

In this embodiment, the offset generation circuit 24 outputs the offset value 331 as binary data.

The offset circuit 23 is configured to output the offset value 337 as binary data.

Each of the address conveyor circuits 21 and 22 compares the memory address MA of the CRTC with a preset value, and the output thereof is input to the determination circuit 25.

Then, the output 250 of the judgment circuit switches the calculation unit 26 between addition and subtraction. Then, when CRTC address MA-h<points to the upper half of the screen, RA=
When RA="1", the offset generation circuit 24 is activated and the output of the offset circuit 23 is inhibited.On the other hand, when RA="1", the output of 24 is inhibited and the output of 23 is activated.

When the CRTC address points to the bottom half of the screen,
When RA="0", 23 is activated and the output of 24 is prohibited.
When RA="1", output of 23 is prohibited.

24 is activated. The offset value generated in this manner is added to or subtracted from the memory address MA to obtain the offset address 20.

A circuit configuration diagram showing the offset generating circuit 2 shown in FIG. 5+a) in further detail is shown in FIG. 5 (bl).

MB2, 33, 34, and 35 of the IC are comparison circuits that compare the A input and B input, respectively, and 1M32 and M
The address conveyor circuit 21 is composed of two ICs of M34. The two M2S ICs constitute the address conveyor circuit 22. B for MB2 B input
Logic 1 is input only to 2, and all other inputs are set to 0. Therefore, the 14th bit and the 15th, 16.17°, 18.19.2 bit of the upper address MA signal are respectively applied to the upper 7 bits of the memory address bus, that is, the address lines MA4.5.6°7.8, 9.10.
When 0-bit logic is input, the most significant bit, that is, the 20th bit of the address (since the 2x64 byte on the screen is accessed by the upper 17 bits of the MA address, the 20th bit selects the top and bottom of the screen) The 9M32 compares whether or not is 1, and outputs a logic 1 to the A=B output only when the other bits are O and the 20th bit of the address is 1. If MAIO, that is, address 20 of the most significant bit, is 1 and at least one other bit is 1, the output of A>H becomes logical 1, and the MA address specifies a half area of the screen. Also M3
4. The 20th most significant bit of the address, 19.18, and 17.16 are input to the A input of M2S, respectively. On the other hand, for the B input, 1M34 is all 0, and 2M35's B input is all 1. Therefore, MAIO, that is, the 20th bit of the address is O, and 16.1? , 18° If the 19th bit address is all 1.

The A=B output of M34 becomes 1. Therefore, the address conveyor circuits of 2M32 and M33 detect a half screen area where the most significant bit of address 20 is 1 and A>B, and when the scan moves from the top half of the screen to the bottom half of the screen, A= B output becomes 1. while 3M34 and M2
The address conveyor circuit consisting of S can detect whether 01111 has arrived at the upper five bits of the MA address in the half area where the most significant bit of address 20 corresponds to O, by outputting A=B. Further, the AND gate and OR gate of MB2°M27 and the two demultiplexers of M2C are connected to offset value generation circuits 23, 24. and an offset value generation circuit and a determination circuit that constitute the determination circuit 25.

Furthermore, M38, 39, 40, 41, 42, and 43 are adder circuits, respectively. The A input of the adder circuit M38, 39°42 has the memory address MA address as the upper address;
That is, 11 bits from the 20th bit to the 10th bit are input to six inputs. On the other hand, the B input is connected to the first demultiplexer M36 of the offset value generating circuit and the Yo small output or the Y1 output of the second M2O through a connection as shown in FIG. Now, if the MA address specifies the top of the screen, the highest bins 1 to 1 of the MA address are O, so the A>B output of M32 is 0,
Assuming that the A=B output is also 0 and the A=B output of 1M34 is also 0, the outputs of the AND circuit 37 are both 0 and the output of the OR gate of 1M27 is also O, so the output below the demultiplexer M36 is O for the A input of the demultiplexer
is input. Since the logic O is fixedly inputted to the B input, the Yo is activated to a small output O, and the 82 input of the adder circuit M39 and the B4.B of M2O are activated. B3. All 0s are input to B2°BI. On the other hand, the IAl input of the demultiplexer on the 2M36 is the Rask address RA from the CRTC.
2 signals are input, but assuming that this signal is now logic 1.

As for the output of the demultiplexer above M2O, only the Y1 output is activated and becomes 0, and the Yo small output becomes 1.

Therefore, the 83 human power of the 1M38 adder is 1. O is input to the B2 input and Bl input, respectively, and as for the M39 adder, the B4 output is 0. The B3 output also becomes 0. Therefore, the B input whose most significant bit is 1 is added to the MA address by the adder M38.39.40 with respect to the upper 11 bits from address 20 to address 10.

That is, the address corresponding to the number of characters for 100 lines is added to the MA address and output. In addition, to the adder M41゜42.43 in the subsequent stage, all A inputs are forced to be logical 0, but 2
M43's A! In other words, since the Yo small output of 9M36 is input to the least significant bit of the upper address, this signal is currently O, so the output of M41, 42.43 is M38
, 39°40 has the same logical state as the addition output.

Therefore, offset address 20 is the MA address that specifies one point in the upper half of one screen.

An address corresponding to the number of characters for 100 lines is added, and this is output as an offset address. On the other hand, if the MA address is specified at one point in the bottom half of the screen.

The A>B output of M32 becomes 1 when Af:B.

Therefore, the 2A input of the demultiplexer M36 below the offset value generation circuit becomes 1. Therefore, its output, 2Yo output, also becomes 1. Furthermore, assuming that the input RA2 of the above demultiplexer M36 is now 0, the Yo small output is O, and the Y+ ratio output is 1. Therefore, the B input of the adder M38°39.40 is 0.1, 1, 1, 1, 0 in order from the most significant bit, that is, the 20th bit of the address.
゜1.1, 1.1 are input. Also, the Yo small output of M2O of the lower demultiplexer is 1.

This is input to the least significant bit A+ of the adder of M43. Therefore, the adder M3B, 39.40 at the previous stage adds the logical series 0, 1.1.1 .
1.1.0.1.1.1.1 is added, and the lowest pitch is added by the adder M41.42゜43 in the subsequent stage.
1 will be added to + and output. This is M
If address A specifies one point in the bottom half of the screen,
The offset value is subtracted from the MA address by adding this multiple display created by inverting the address corresponding to the number of characters for 100 lines, that is, the bit pattern corresponding to a positive offset value and adding 1 to the MA address. Action is being taken.

Next, the video control circuit 6 shown in the block diagram shown in FIG. 1 will be explained in detail. Figure 6 shows the video control circuit 6.
The block diagram is shown below. The MA address output from the CRTCI or the offset address generated by the offset generating circuit 2 for the MA address is given to the VRAM 4 in a time-sharing manner for each scan of two screens, and the corresponding VRAM data is sent to the character generator 5.
, the character generator 5 is given.

As shown in FIG. 4, display data 50 is output. Latch circuits 60 and 61 are connected to the output line 50 of the character generator 5 as launch circuits.

The launch circuit 60 receives the MA output from the CRTCI.
The output display data of the character generator 5 corresponding to the address is output to the UPLCK clock, that is, the second
The launch circuit 61 launches with the clock indicated by ■ in the figure.
The offset value is added by the offset generation circuit 2 to the MA address output from CRTCl, and the character corresponding to the offset address is output 50.
The clock LP shown at J in FIG.
This is a circuit that launches on LCK. The display data placed in the launch circuits 60 and 61, that is, the character corresponding to the MA address and the character corresponding to the offset address, are simultaneously output as serial data from the latch circuit and sent via the selection circuit 62 to the LCD display. It will be sent to the drive circuit and displayed at the same time. The selection circuit 62 determines whether the MA address specifies the upper half or the lower half of the screen.
This is for switching data output. In other words, CR
When the TC address MA specifies the upper side of the screen, the data in the latch 60 is set to data D1 that drives the upper side of the LCD panel, the data in the latch 61 is set to data D2 that drives the lower side of the LCD panel, and MA specifies the upper side of the screen. When the lower side is specified, the output of 60 is set as D2, and the output of 61 is set as Dl.

The present invention uses CRTCl in this way, so that the display does not use the rask scan method like a CRT, and the CD
Screens like this can now be displayed using CRTC 2
It provides a method to display the screen by dividing it into two parts, and CR
An offset is applied to the memory address MA output by the TC, so that while the CRTC itself accesses 1 byte of VRAM, it is forced to access 2 bytes.

Although the character generator 5 is used in the above embodiment, the present invention can also be applied to a bitmap display in which dots on one screen and memory correspond one to one without using a character generator.

When the present invention is applied to a bitmap display, the rask address is also input to the VRAM.

〔Effect of the invention〕

In this way, the present invention uses a CRTC to drive not only a CRT but also a liquid crystal display, that is, an LCD panel display device, which has recently become more practical, without the need for a dedicated LCD controller. , since the LCD can be controlled using a mass-produced CRTC,
This has the effect of greatly improving cost performance compared to CRTC. Furthermore, according to the present invention, CRT
C can be used to control not only CRTs but also LCDs, which improves the cost performance of CRTCs, and even when CRTCs are used in place of LCD controllers, it takes less time (similarly, once per 100 lines of horizontal scanning). Since each pixel will be displayed, each pixel will not be displayed dimly.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram according to a two-screen split screen display method using a CRTC according to the present invention. FIGS. 2+a) to 2(d) are conceptual diagrams of memory access. FIG. 3 is a timing chart of the output waveforms of each circuit in FIG. 1. (a) is a block diagram of the offset generation circuit of the present invention. In the figure (bl is a detailed circuit configuration diagram of the offset generation circuit). Fig. 6 is a block diagram of the video control circuit of the present invention. 1... CRTC. 2... Offset address generation circuit. 3... Selection circuit. 4... VRAM. 5... Character generator. 6... Video control circuit. 7... LCD panel device. 8... - Timing generation circuit. 9... Selection circuit. 10... Horizontal synchronization signal. 11... Vertical synchronization signal. 12... Display period instruction signal. 13... Memory address (MA). 20...・Offset address signal. 21.22... Address conveyor circuit. 23.24... Offset value generation circuit. 25... Judgment circuit that decides whether to add or subtract the offset value. 26... Addition/subtraction device. M32 .M33.M34.M2S... Comparison circuit. M27.M36M37.... Offset value generation circuit and judgment circuit. M38.M39.M2O, M41.M42.M43...
・Adder/subtractor, ' 60.61... Launch circuit. 62...Selection circuit. CF? T's run k #eJ
Q1: J4LCD/Y3tvk&(0)
(b) Fig. 4 (b) Fig. 4

Claims (2)

[Claims] (1) CR that generates a memory address for an image memory that stores display data for at least one screen of a CRT
a T controller, a determination circuit that determines which area the display position corresponding to the memory address corresponds to on a screen divided into at least two areas, and an offset value generation circuit that generates an offset value; The offset value is added to or subtracted from the memory address in response to the output of the discrimination circuit to correspond to a display position in an area other than the area including the display position corresponding to the memory address. an arithmetic circuit that outputs an offset memory address, and while the CRT controller outputs one memory address, reads at least two pieces of data from the image memory using the memory address and the offset memory address; A liquid crystal display display control method using a CRT controller, characterized in that a display corresponding to the data is simultaneously displayed on a liquid crystal display. (2) The screen is divided into upper and lower halves, the discrimination circuit determines whether the display position corresponding to the memory address is included in the upper or lower area of the screen, and the arithmetic circuit determines whether the display position is in the upper area. When the display position is included in the lower screen, the offset value is subtracted from the memory address, and when the display position is included in the lower screen, the memory address and the offset value are added, and the display position is responded to one memory address output from the CRT controller. C according to claim 1, wherein the display is simultaneously performed on the upper and lower screens.
Display control method for liquid crystal display using RT controller.