JP2674145B2 - Display control device - Google Patents

Description

The present invention relates to a display control device, and more particularly to a display control device having a function of performing gradation control of display data and outputting the display data to a display device.

[Conventional technology]

In recent years, display devices as man-machine interfaces have become more and more important, and the market is rapidly expanding. Conventionally, CRTs (CRTs), which have excellent display quality such as color display and high resolution and cost performance, have been mainly used as display devices. However, with the development of IC and LSI technology, including personal computers and word processors
As OA-related equipment, bank terminals, and various industrial equipment such as in-vehicle equipment are becoming smaller and higher in performance, the demand for thinner and lighter displays is rapidly increasing. Liquid crystal displays (LCDs), plasma displays (PDPs), and other various panel displays that meet these demands are being used in conjunction with the development of LSIs while achieving cost reduction, thinning, and weight reduction while improving display quality. The field is expanding. In particular, in OA-related equipment, large-scale full-dot panel displays with a resolution of 640 x 200 dots to 640 x 400 dots, which is comparable to CRTs, are becoming the main focus, and display data of a scale comparable to CRT screens. Can be displayed as is.

In addition, since the colorization of these panel displays is more disadvantageous than CRTs in terms of technology and cost, it is limited to a small size of about 5 inches, and for large panel displays, monochrome display is currently used. However, it is used in the mainstream.

Here, since a monochrome panel display can only express the presence or absence of display pixels, when displaying color data that was conventionally displayed on a CRT or the like on such a panel display, for example, the color data is all "0". If there is no pixel, color data is all "0"
Otherwise, all color data is converted into a binary display pattern, such as with pixels. However, in such a simple monochrome display pattern, it is impossible to identify the display area for each color on the screen, so the display device discriminates this for the color data of the display pixel and corresponds to each color. It has become indispensable to express the distinction of the color of each display pixel by performing gradation processing for converting the information into predetermined agricultural information and displaying it.

Conventionally, as a method for displaying this type of grayscale, a dedicated grayscale control circuit periodically outputs the display pixel data at a timing (hereinafter, referred to as a grayscale pattern) determined corresponding to each color. The method of prohibiting / permitting is generally adopted, but as the display screen becomes more multicolored and diversified, gradation processing by various gradation patterns is performed to cope with this. It is desired to have a display control device capable of performing the above.

FIG. 17 is a block diagram showing an example of a display control device that performs the above gradation control unit, and its operation will be described below.

In the device shown in FIG. 17, the microprocessor 200 controls the operation of the entire system via the system bus 208, stores the program executed by the microprocessor 200 and processing data in the main memory 201, and the peripheral controller 202. Interface to a keyboard 206 or an external storage disk device 207, and the display signal generator 204 causes the display memory 203 to
Various display functions are realized by reading the display data stored in (1) and displaying a desired screen on the panel display 205 such as LCD or PDP.

The gradation display on the panel display 205 is based on the color information of the display data read from the display memory 203 in synchronization with the display timing generated by the display signal generating unit 204, and the color information is displayed by an internal gradation control circuit. It is realized by discriminating and driving the gradation pattern generating circuit corresponding to each color to periodically prohibit / permit the output of the display data according to the display timing.

For example, when the color information of the display data is specified by 2 bits and the combination of the four colors of white, yellow, cyan, and black is displayed in gradation, 4 of A, B, C, and D are displayed. A gradation pattern generation circuit that generates different kinds of gradation patterns is provided, and the A, B, C, and D gradation patterns are assigned to the respective colors. As a result, when the display data is sequentially read from the display memory 203, a signal for selecting one of A to D corresponding to the color information of the display data is output, and the gradation patterns A to D corresponding thereto are output. Selected
On the panel display 205, the originally white color portion is displayed with the gradation A, the yellow portion is displayed with the gradation B, the cyan portion is displayed with the gradation C, and the black portion is displayed with the gradation D. The degree of shading corresponding to each color is determined as a pattern of output prohibition / permission frequency based on the cycle of one screen scan (hereinafter, referred to as a frame) inside the gradation pattern generation circuit. As shown, the part with display pixels is a gradation A that is always displayed, a gradation B that is displayed only during a period of 3 frames out of 4 frame cycles, and a level that is displayed only during a period of 2 frames out of 4 frame cycles. Each pattern of gradation C and gradation D which is not always displayed is determined by hardware.

Here, in an application in which the correspondence between the color information and the gradation pattern is changed according to the type of the panel display 205 to be connected, the contents of the display screen, the property of the display information, etc.
Provided is a code converter capable of generating corresponding gradation pattern selection information based on the color information of display data and changing the combination of the two.
Set the data in the code converter according to the command executed by
For example, the yellow part is changed to gradation C and the cyan part is changed to gradation B.

[Problems to be solved by the invention]

In the conventional display control device having the above-mentioned gradation control circuit, when the type of panel display to be connected is different depending on the application as the device, for example, in LCD, the response speed of the screen is relatively slow. It is sufficient to perform periodic display data output control in units of multiple frames, such as the two-frame period prohibition and the two-frame period permission repetition shown in Fig. 18, but with a panel display with a fast screen response speed like PDP, It is necessary to control the output of display data at a high-speed timing such that the prohibition / permission is repeated for each frame so that the screen does not flicker. Therefore, in order to be able to perform gradation control suitable for various panel displays, there is a disadvantage that it is necessary to provide an independent dedicated hardware for generating gradation patterns for each type of panel display. Was there.

Further, in order to perform gradation display for distinguishing a plurality of colors to be used, it is necessary to prepare hardware for gradation pattern generation for generating each gradation pattern. In the field of color display, the number of color types used by dedicated hardware increases in order to cope with the increasing number of multicolored colors, which is not economically efficient. It was

It is an object of the present invention to improve such problems in the conventional gradation display control, provide a low-cost and highly flexible display device, and improve the performance of the entire display system.

[Means for solving the problem]

A display control device of the present invention includes a display memory for storing display information to be displayed on a display device, a display timing generator for generating a display timing signal and a synchronization signal for the display device, and a process for rewriting the contents of the display memory. In a display control device having a microprocessor for execution and capable of displaying the display information on a display device, a data memory storing a plurality of timing information designating prohibition or permission of output of the display information sent to the display device. A means for selecting and reading the timing information from the data memory by the microprocessor; a register that stores the timing information read by the microprocessor and is rewritable by the microprocessor; and a content of the register. Generated based on By providing a means for inhibiting or permitting the output of the display information to be sent to the display device by the timing signal, and a means for executing the processing of rewriting the contents of the register by the microprocessor in synchronization with the display timing signal, The color information of the display data is converted into grayscale information by the processing executed by the microprocessor and is displayed.

[Embodiment 1] As a first embodiment of the present invention, a display control device for performing gradation display control of a graphic screen by a gradation pattern prepared on a data memory will be described below. FIG. 1 is a block configuration diagram of a display control device according to a first embodiment of the present invention.

The apparatus shown in FIG. 1 controls the operation of the entire system by a microprocessor 1, stores a program executed by the microprocessor 1 in a program memory 2 and processing data of the microprocessor 1 in a data memory 3, and stores the program through a multiplexer 30. The display data of the display memory 4 is operated to realize a desired screen display. Graphic data is stored in the display memory 4 as display information. As shown in FIG. 2, the graphic data is assigned 3 bits C2 to C0 per pixel, and each bit is used as color information of R (red), G (green), B (blue), One color is selected from eight colors for each pixel. The display timing generation circuit 20 synchronizes with the display timing generated by itself, a frame timing signal 21 generated at the end of each frame, a dot timing signal 22 for the gradation control circuit 50, and a synchronization signal for the panel display 5. 23 and a display address 24 for the display memory 4 for reading the display data. The frame timing signal 21 is supplied to the microprocessor 1 and used as an interrupt signal. The parallel graphic data read from the display memory 4 is converted into serial data at the timing of the dot timing signal 22 in the shift register 40 and supplied to the gradation control circuit 50, and converted into grayscale information based on the output of the control register 60. It is then transmitted to the panel display 5 as panel display data. The address decoder 10 generates the write strobe signal 11 and outputs it to the control register 60 when the microprocessor 1 generates the write signal 8 for the control register 60. The multiplexer 30 switches the address to the display memory 4 to the address bus 6 of the microprocessor 1 during the blanking period of the synchronizing signal 23 so that the data in the display memory 4 can be rewritten. If not during the blanking period, the output of the display address 24 from the display timing generation circuit 20 is connected.

FIG. 3 is a detailed block diagram of the shift register 40, the gradation control circuit 50, and the control register 60 shown in FIG.
The control register 60 is an 8-bit latch and latches the write data on the data bus 7 in FIG. 1 at the timing of the write strobe signal 11 generated by the write operation by the microprocessor 1. The decoder 52 is the shift register 40
The 3-bit color information of C2 to C0 read serially in 1 pixel units from is decoded into 8 codes, and C2 to C0 is decoded.
3 bits color information of is decoded into 8 codes, and C2 ~
A decode signal is generated such that Sn becomes active for the value n of 3-bit data, such as S0 when the combination of 3 bits of C0 is "000", S1 when it is "001", and the like. This decode signal is input to the AND gate 53 together with the bit outputs M7 to M0 of the control register 60, and is mask-controlled. The output of the AND gate 53 becomes 1-bit display data by the OR gate 54, and the D flip-flop 55 re-turns it at a dot-by-dot timing based on the dot timing signal 22 and outputs it as the display data output 51 to the panel display 5.

Next, the frame timing signal 21 from the display timing generation circuit 20 is activated at the end of each frame.
Microprocessor 1 stored in program memory 2
FIG. 4 shows a flowchart of the interrupt program process of FIG. 4, and the data transfer process to the control register 60 for gradation display control will be described.

The data memory 3 shows the gradation pattern tables PT0 to PT7 shown in FIG. 5, which are obtained by keyboard input as variables to be processed by the program, the table address TA for designating the addresses, and the storage start address of the table. A start address SA and a terminal counter C that counts the number of transfers are assigned.

In the program, first, one of the data of the gradation pattern tables PT0 to PT7 is read by using the content of the table address TA as an address and transferred to the control register 60 (step 10).
0) Then, the contents of the table address TA are incremented by +1 (step 101), and the terminal counter C
Is decremented by -1 (step 102). If the terminal counter C is not 0, the interrupt program process is terminated (step 103) and the process returns to the main program. If the terminal counter C is 0 in step 103, the contents of the start address SA are set to the table address TA (step 104), the terminal counter C is set to 7 (step 105), the interrupt program processing is terminated, and the main program is terminated. Return to.

By performing the above series of processing each time one frame is completed, each bit output M7 to M0 of the control register 60 in FIG.
As shown in FIG. 6, there are eight types of patterns with eight frame periods, which result in different decoded signal outputs of S7 to S0 based on 3-bit color information of C2 to C0.
Mask control is performed with the M0 pattern. For example, a display pixel in which C2 to C0 is "000" is always prohibited from display, and a "111" display pixel is always displayed. Further, the display pixel of "011" is prohibited to display every other frame, and is displayed with a brightness half that of the display pixel of "111". In this way, the color data of 8 colors is converted into the display data having the meaning of 8 patterns of light and shade corresponding to each other.

As the processing of the microprocessor 1 at this time, it suffices to perform the processing of rewriting the control register 60 each time one frame is completed, and simple data transfer by interruption, comparison,
It is a calculation only, and the processing time is extremely short.

If it is desired to change the correspondence between the color information and the degree of shading, the data at the predetermined bit positions of the gradation pattern tables PT0 to PT7 allocated to the data memory 3 may be replaced. Furthermore, when it is desired to change or finely adjust the degree of gradation, it is only necessary to change the data array of the gradation pattern tables PT0 to PT7.

Second Embodiment Next, as a second embodiment of the present invention, a display control device for performing gradation display control of a text screen will be described. FIG. 7 is a block configuration diagram of a display control device according to a second embodiment of the present invention.

The apparatus of FIG. 7 controls the operation of the entire system by a microprocessor, stores a program to be executed by the microprocessor 1 in a program memory 2 and processing data of the microprocessor 1 in a data memory 3, and stores the data via a multiplexer 30. A desired screen display is realized by operating the display data of the display memory 4.

The display memory 4 stores character codes and color attribute codes as display information. The character code is supplied as address information to the character generator 70. On the other hand, the color attribute code is, as shown in FIG. 8, a color of a dot portion (hereinafter, referred to as foreground) of one character and a dot without dot. CA1 to C for each color of the part (hereinafter called background)
Two bits are assigned to each of A0 and CB1 to CB0, and one color is selected from four colors according to the combination of each bit and displayed. The display timing generation circuit 20 includes a frame timing signal 21 generated at the end of each frame in synchronization with the display timing generated by itself and a gradation control circuit.
A dot timing signal 22 for 50, a sync signal 23 for the panel display 5, a display address 24 for the display memory 4 for reading display data, and a character timing signal 25 for the color register 80 are generated. The frame timing signal 21 is supplied to the microprocessor 1 and used as an interrupt signal. The character pattern data read from the character generator 70 based on the character code read from the display memory 4 is converted into a serial pattern 41 at the timing of the dot timing signal 22 in the shift register 40 and supplied to the gradation control circuit 50. . The color attribute code read from the display memory 4 is stored in the color register 80
Is supplied to the gradation control circuit 50 via the, and converted into grayscale information based on the output of the control register 60 and sent to the panel display 5 as panel display data. The address decoder 10 generates the write strobe signal 11 and outputs it to the control register 60 when the microprocessor 1 generates the write signal 8 for the control register 60. The multiplexer 30 switches the address to the display memory 4 to the address bus 6 of the microprocessor 1 during the blanking period of the synchronizing signal 23 so that the data in the display memory 4 can be rewritten. The output of the display address 24 from the display timing generation circuit 20 is connected except during the blanking period.

FIG. 9 is a detailed block diagram of the shift register 40, the gradation control circuit 50, the control register 60, and the color register 80 shown in FIG. The control register 60 is an 8-bit latch and latches the write data on the data bus 7 in FIG. 7 at the timing of the write strobe signal 11 generated by the write operation by the microprocessor 1. The color attribute codes of CA1 to CA0 and CB1 to CB0 read from the display memory 4 are latched in the color register A81 and the color register B82 respectively at the timing of the character timing signal 25, and the decoder A56 and the decoder B57 each have 2 bits. Decodes color information into 4 codes, 2 of CA1 to CA0
S0 when the bit combination is "00", S1 when "01", "1"
S2 when 0 ", S3 when" 11 ", S4 when the combination of 2 bits CB1 to CB0 is" 0 ", S5 when" 01 ", S6 when" 10 "
When it is "11", a decode signal is generated so that S7 becomes active. This decode signal is input to the AND gate 53 together with the bit outputs M7 to M0 of the control register 60, and is mask-controlled. Each output of the AND gate 53 is generated by OR gates 58 and 59 from 1-bit display data of foreground and background from 4 bits corresponding to S0 to S3 and S4 to S7, respectively. Each display data is input to the AND gates 510 and 511, and the serial pattern 41 from the shift register 40 selects the AND gate 510 as a dot when the value is “1” and the display data in the foreground passes through the OR gate 512. When the output is “0”, AND gate 511 is selected as no dot and the background display data is OR gate 51.
It is output via 2. The output of the OR gate 512 is re-cut by the D flip-flop 55 based on the dot timing signal 22 at the timing of each dot, and the display data output 51 is output to the panel display 5.

Next, the frame timing signal 21 from the display timing generation circuit 20 is activated at the end of each frame.
Microprocessor 1 stored in program memory 2
FIG. 10 shows a flowchart of the interrupt program process of FIG. 10, and the data transfer process to the control register 60 for gradation display control will be described.

In the data memory 3, the gradation pattern table addresses PT0 to PT3 shown in FIG. 11, which are obtained by keyboard input, the table address TA for designating the addresses, and the storage start address of the table are stored as variables to be processed by the program. The start address SA shown and a terminal counter C that counts the number of transfers are assigned.

In the program, first, one of the data of the gradation pattern tables PT0 to PT7 is read by using the content of the table address TA as an address and transferred to the control register 60 (step 10).
0) Then, the contents of the table address TA are incremented by +1 (step 101), and the terminal counter C
Is decremented by -1 (step 102). If the terminal counter C is not 0, the interrupt program process is terminated (step 103) and the process returns to the main program. If the terminal counter C is 0 in step 103, the contents of the start address SA are set in the table address TA (step 104), the terminal counter C is set to 3 (step 106), the interrupt program processing is terminated, and the main program is terminated. Return to.

By performing the above-described series of processes each time one frame is completed, each bit output M7 to M0 of the control register 60 shown in FIG.
Shows four types of patterns of four frame periods as shown in FIG. 12, and as a result, the decode signal output of S7 to S4 and S3 to S0 based on 2-bit color information of CA1 to CA0 and CB1 to CB0 is performed. Are mask-controlled by different M7 to M0 patterns, and in the same manner as in the first embodiment, the color decoding of four colors is converted into display data having the meaning of four shades of light and shade. Further, if the set values of the gradation pattern tables PT0 to PT3 are set to different combinations for the foreground, the background, and the background, it is possible to convert the display data to have 8 patterns of shades and meanings as a whole.

As the processing of the microprocessor 1 at this time, similar to the first embodiment, it suffices to perform the processing of rewriting the control register 60 at each end of one frame, and only the simple data transfer by interruption, comparison, and operation, The processing time is extremely short.

Further, when it is desired to change the correspondence between the color information and the degree of shading, or to change or finely adjust the degree of gradation, the data of the gradation pattern tables PT0 to PT3 assigned to the data memory 3 is also used as in the first embodiment. Just rewrite.

Example 3 Next, as a third example of the present invention, among the display screens,
A display device in which gradation control is performed only on a predetermined area will be described.

FIG. 13 is a diagram showing a display timing generating circuit 300 and a microprocessor 1 corresponding to the display timing generating circuit 20 of the first embodiment of FIG. 1 among the display control apparatus of the third embodiment of the present invention. In the display control device of the third embodiment, except that the interrupt signal supplied from the display timing generation circuit 300 to the microprocessor 1 is different from that of the first embodiment, other block configurations and operations are the same as those of the first embodiment shown in FIG.
The display control device is the same as that shown in FIG.

The display timing generation circuit 300 of FIG. 13 includes a clock generator 302 that generates a dot timing signal 22 indicating the timing of each dot of display data for the gradation control circuit 50 and the shift register 40 of FIG. A dot counter 303 that counts the number of dots in the horizontal direction of the screen based on the dot timing signal 22, and a dot counter 303
Line counter 304 that counts the number of lines in the vertical direction of the screen based on the carry of, the sync signal generation circuit 305 that generates the sync signal 23 based on the carry of the line counter 304 and the carry of the dot counter 303, and the dot counter. First from the count value of 303 and the count value of line counter 304
A display address generation circuit 306 for generating a display address for the display memory 4 in the figure is provided. Here, the carry of the dot counter 303 is a 1H timing signal 301 indicating the end timing of one horizontal scanning, and the carry of the line counter 304 is a frame timing signal 21 indicating the end timing of one frame scanning. It is supplied to the processor 1 and is used as a first interrupt signal and a second interrupt signal, respectively.

Further, regarding the internal configuration and operation of the shift register 40, the gradation control circuit 50, and the control register 60 in the display control device of the third embodiment, the shift register of the first embodiment of FIG.
40, the gradation control circuit 50, and the control register 60, the detailed description thereof will be omitted.

Next, the 1H timing signal 301 from the display timing generating circuit 300 is activated every time one horizontal scanning is completed. A flow chart of the first interrupt program processing of the microprocessor 1 stored in the program memory 2 is shown in FIG. 14, and the data to the control register 60 and the data memory 3 for controlling the gradation display area on the screen. The transfer process will be described.

In the data memory 3, the gradation pattern tables PT0 to PT7, the table address TA, the start address SA, and the terminal counter C shown in FIG. A start address SA, a line end address LEA indicating an end line position for ending the gradation control, and a line counter LC for counting the number of lines for each horizontal scanning are assigned.

In the program, first, the value of the line counter LC is +1
Increment (step 400). Next, the line start address LSA and the value of the line counter LC are compared (step 401). If the line counter LC is smaller than the line start address LSA, the immediate data E (H) is transferred to the control register 60 (step). 404) and after M0 of the control register 60, the first interrupt program processing is terminated and the main program is restored.

On the other hand, if the line counter LC is greater than or equal to the line start address LSA in step 401, the line end address LEA and the value of the line counter LC are compared (step 402), and if the line counter LC is greater than the line end address LEA, E (H) is transferred to the control register 60 (step 404), the first interrupt program process is terminated, and the process returns to the main program. On the other hand, if the line counter LC is smaller than or equal to the line end address LEA, one of the data of the gradation pattern tables PT0 to PT7 is read by using the content of the table address TA as an address and transferred to the control register 60 (step 403). ,
The first interrupt program processing is terminated and the main program is restored.

In addition, the flowchart of the second interrupt program of the microprocessor 1 stored in the program memory 2 which is activated at the end of each frame by the frame timing signal 21 from the display timing generation circuit 300
A control variable generation process for performing gradation control shown in the figure will be described.

In the program, first, the line counter LC is cleared to 0 (step 405), then the content of the table address TA is incremented by +1 (step 101), and the terminal counter C is decremented by -1 (step 102). If the terminal counter C is not 0, the second interrupt program process is terminated (step 103) and the process returns to the main program. On the other hand, if the terminal counter C is 0 in step 103, the contents of the start address SA are set to the table address TA (step 104), the terminal counter C is set to 7 (step 105), and the interrupt program processing is terminated. Return to the main program.

By performing the above-described first interrupt processing and second interrupt processing each time one horizontal scanning ends and one frame end, as shown in FIG. 16, the line start address LSA and line end address of the display screen are displayed. Control data for gradation control is transferred to the control register 60 only for the area designated by LEA, and the display data is mask-controlled in frame cycle units and gradation display is performed. The operation of gradation control by mask control is the same as in the first embodiment.

For example, if a panel display with a total of 200 lines per screen is used, the line start address LS
By setting A and line end address LEA to 19 and 19 respectively, in the area from the 1st line to the 19th line of the screen, M0 of the control register 60 is set to "0", M1 to M7 is set to "1", and the color Display pixels for which the information C2 to C0 is "000" are always prohibited, and display pixels for which the color information C2 to C0 is other than "000" are always displayed. Also, from the 20th line of the screen
In the area up to 192 lines, the color data of 8 colors based on the 3-bit color information is converted into the corresponding display data of 8 patterns of light and shade in the same manner as in the first embodiment.
Further, in the area from the 193rd line to the 200th line, display pixels whose color information C2 to C0 is "000" are always prohibited from being displayed, and display pixels whose color information C2 to C0 are other than "000" are always displayed. In this way, for example, according to the content of the display data, the character display portion of the menu screen is not displayed in gradation, and only the graphic display portion can be displayed in gradation, so that the character display is maintained at a constant brightness. As it is, the graphic display can optimize the correspondence between the color information and the gradation pattern, and a display screen that is easy to see can be obtained.

Further, the gradation display area on the screen can be arbitrarily set only by changing the values of the line start address LSA and the line end address LEA.

As the processing of the microprocessor 1 at this time, there are area discrimination at each end of one horizontal scan and rewriting of the control register 60, and control variable generation processing at every end of one frame. Only transfer, comparison, and calculation are performed, and the processing time is extremely short.

Further, in the present embodiment, an example in which gradation control is performed only in a predetermined area and binary display is not performed, but in the first interrupt processing, the gradation pattern tables PT0 to PT7.
Further, by setting different data in the areas, the correspondence between the color information and the degree of shading can be changed for each area of the screen.

〔The invention's effect〕

In the above-described embodiment, an example of gradation display by pattern control of 8 gradations or 4 gradations is shown, but for gradation display exceeding 8 gradations such as pattern control of 16 gradations by 4-bit color information. Can be easily realized by using the device of the present invention.

As described above, according to the present invention, the degree of shading, that is, the gradation pattern of display data can be easily changed on the data memory, and various patterns can be generated without using dedicated hardware. Therefore, it is possible to make fine adjustments to the optimum gradation level according to the contents of the display screen, the nature of the display information, etc., and easily adapt it to different types of panel displays such as LCD and PDP. The performance of key display can be greatly improved.

In addition, it is possible to change the color information and the degree of shading by diverting a part of the data memory without using a dedicated code converter such as a color palette. The corresponding multi-gradation display can be expanded by adding simple minimum hardware such as latches and AND gates instead of complicated hardware.

As described above, according to the present invention, the existing hardware is shared, and the display control device having the gradation display function which is inexpensive and has high flexibility by the minimum hardware and the simple program processing by the microprocessor is provided. There is an effect that can be provided.

[Brief description of the drawings]

FIG. 1 is a block configuration diagram of a display control device according to a first embodiment of the present invention, FIG. 2 is a configuration diagram of display data according to the first embodiment, and FIG. 3 is a shift register 40 and a gradation control circuit 50 according to the first embodiment. 4, a detailed block diagram of the control register 60, FIG. 4 is a flowchart of the interrupt program processing of the first embodiment, FIG. 5 is a configuration diagram of the gradation pattern tables PT0 to PT7 of the first embodiment, and FIG. 6 is the first embodiment. FIG. 7 is a timing diagram of the gradation patterns M7 to M0 of FIG. 7, FIG. 7 is a block diagram of the display control device in the second embodiment of the present invention,
FIG. 8 is a block diagram of the display data of the first embodiment, FIG. 9 is a detailed block diagram of the shift register 40, the gradation control circuit 50, the control register 60, and the color register 80 of the second embodiment, and FIG. Flowchart of interrupt program processing of Example 2, No.
FIG. 11 is a configuration diagram of the gradation pattern tables PT0 to PT3 of the second embodiment, FIG. 12 is a timing diagram of the gradation patterns M7 to M0 of the second embodiment, and FIG. 13 is a display timing generation of the third embodiment of the present invention. FIG. 14 is a diagram showing a detailed block configuration of a circuit and a configuration of a microprocessor, FIG. 14 is a flowchart of a first interrupt program process of the third embodiment, and FIG. 15 is a flowchart of a second interrupt program process of the third embodiment. Figure 16 shows Example 3
17 is a block diagram of a conventional display control device, and FIG. 18 is a timing diagram showing an example of a gradation display pattern in the conventional display control device. 1... Microprocessor, 2... Program memory,
3 ... data memory, 4 ... display memory, 5 ... panel display, 6 ... address bus, 7 ... data bus, 8 ... write signal, 10 ... address decoder, 11 ...
... write strobe signal, 20,300 ... display timing generation circuit, 21 ... frame timing signal, 22 ... dot timing signal, 23 ... synchronization signal, 24 ... display address, 25 ... character timing signal, 30 ... multiplexer , 40 ... Shift register, 41 ... Serial pattern, 50 ... Gradation control circuit, 51 ... Display data output, 52 ...
… Decode, 53,510,511 …… Andgate, 54,58,59,5
12 …… OR gate, 55 …… D flip-flop, 56 ……
Decoder A, 57 ... Decoder B, 60 ... Control register,
70 …… Character generator, 80 …… Color register, 80 …… Color register A, 82 …… Color register B, 200 …… Microprocessor, 201 …… Main memory, 202 …… Peripheral control unit, 203 …… Display memory , 204 ……
Display signal generator, 205 …… Panel display, 206 ……
Keyboard, 207 ... disk unit, 208 ... system bus, 301 ... 1H timing signal.

Claims (1)

(57) [Claims] 1. A display memory for storing display information, a display timing generator for generating a display timing signal including a frame timing signal and a synchronizing signal for a display device, and a micro-processor for rewriting the contents of the display memory. In a display control device including a processor, a data memory that stores a plurality of timing information that specifies prohibition or permission of output of display information to be sent to the display device and that can change the stored content, a timing information storage register, Means for prohibiting or permitting output of display information to be sent to the display device by a timing signal generated based on the contents of the register, and the microprocessor executes interrupt processing in response to the frame timing signal. , In the interrupt process Reading timing information selected from a plurality of timing information from the data memory,
A display control device, wherein the contents of the timing information storage register are changed according to the read timing information.