JPS60202485A - Display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a display device that displays signals having halftones, such as image signals, using a dot matrix display element such as a fluorescent display tube.

[Prior Art] A dot matrix type display element generally has the configuration shown in FIG. The signal lines consist of two sets, a column electrode group It is done like this.

FIG. 2 shows a typical example of a conventional display device using this display element. In the figure, (1) is a matrix display panel, (2) is a driver that controls the display of pixels arranged at the intersection of electrode groups X and Y of the display panel, and (3) and (4) are column electrodes. A column electrode control circuit and a shift register that obtain drive signals, (5) a row electrode control circuit that also obtains drive signals for the row electrodes, and (6) a column electrode control circuit that also obtains drive signals for the row electrodes, and (6) turn on/off the data of the memory (7) that stores image signals. In the conversion section for converting into a signal, a shift register (4) arranges on/off signals to corresponding column electrodes based on a shift clock signal from a timing generation circuit (8),
The column electrode control circuit (3) is a timing generation circuit (
It is controlled to latch the output of the shift register (4) for a predetermined period based on the latch clock signal from the shift register (4).

(8) is a display controller device equipped with a microprocessor to provide display data;
), an address signal to the selector (1o), and a timing signal for writing data to the read/write control (hereinafter referred to as R/W control) (11).

(12) represents a clock generation circuit, and (13) represents a read address counter.

In the configuration described above, the display panel (1) has a memory (7).
) is read out periodically, converted into on/off signals for each pixel, and displayed. Display control device (8
) The display data sent from R/W Co/Troll (11
), the timing is adjusted so as not to interfere with the read timing of the memory (7) for display, and the data is written to the memory (7). In order to simplify the explanation below, the display panel will be explained using a 4×4 pixel element. There is a one-to-one correspondence between the pixel position of the display element and the memory address, and the relationship is as shown in FIG. 3. That is, (a) is the arrangement of pixels,
(b) is the memory address corresponding to the position of each pixel, (
C) shows data written to each address corresponding to a pixel of the memory, and the addresses can be divided into X addresses and Y addresses as shown in (d). Such a display device performs display by sequentially and periodically driving the electrodes Y and switching the signal applied to the electrodes X in synchronization with the driving.

A control time chart of this display device is shown in FIG. Now, if an address is given to the memory (7) at the timing shown, the corresponding data will be output. What about the conversion section (8) that performs on/off determination? Turn on 1'', '0''
is determined to be off data, and the data is sent to the shift register (4). This data is arranged in a shift register (4) by a shift clock S, latched by a latch clock L and held for a certain period of time, and becomes a signal for driving the X electrode. Craftsmanship lf, Tt (7) mnlH*T+ (1) I
It holds data that is different from fJIrlH, and drives the X electrode according to that data. On the other hand, the Y electrode is driven by Yl, and the display during the period T1 is as shown in FIG. Due to the effect of the afterimage, the data shown in FIG. 3 will be displayed in succession, as shown in FIG. 3 (e). Note that (') indicates the corresponding address of the memory (7).

Such display elements can only express binary values, such as whether a pixel is on or off, but when displaying an image signal with halftones, the data in the memory is read out the required number of times to control the on/off of the corresponding pixel. It is possible to display shades of light and light depending on the length of the cumulative time period in which each pixel is turned on.

The display of data having halftones will be described below.

To simplify the explanation, let's assume that each pixel has 2 bits of data and that it is possible to display four gradations of light and shade. In this case, the memory (7) is read out four times, and each pixel is determined to be on or off according to the data and displayed, and a halftone is displayed based on the accumulated time width of on and off of each pixel.

The converter (6) that performs on/off determination has a concrete configuration shown in FIG. Here, the counter counts the number of times the memory (7) is read, and the display data is read out 4 times and sequentially compared with the counter outputs O to 3 by a comparator. 1 When the display data A is larger than the counter output B, it is turned on and equal. or convert it into an off signal when it is small.

Now, a case will be described in which data as shown in FIG. 7(b) is written to the address of the memory (7) shown in FIG. 7(a) corresponding to each pixel of the display element. According to the driving method shown in Fig. 4, the drive signal for the X electrode is switched at the latch timing, and the signal for the Y electrode is also switched at the same time. The process is repeated successively for the cases where the comparison data B is 0.1 and 2.3 to form a screen of one field, which is shown in FIG. 8 using a time chart. In this case, when the data of each pixel is n pixels, it is possible to display an image with 2"L gradations, but it is necessary to read the memory twice, and even in the above example, the data is Since it is a bit, the memory is read four times,
One field screen is formed by four screens indicated by t1 to t4. FIG. 9 shows each display form (a) to (d) at times t1 to t4 in FIG. 8 and an image (e) visible to the human eye as the cumulative value thereof. an-d3 corresponds to the display at aO to d3 in FIG. 8, and aox
When the counter output B in FIG. 6 is B=0, do is al
~dl is B==1. a2-d2 is B=2, a3-d3
(e) shows the case where B=3, and (e) shows the case where B=4.

However, in dynamic driving in this case,
The Y electrode drive signal is switched at the same time as the electrode drive signal is switched, and the blanking time Tb is
(see FIG. 8), which leads to a reduction in brightness due to the significant sacrifice of the effective light emission period. Furthermore, when displaying high-gradation data, the number of memory reads per 1-field increases, and the number of screens required to make up an 1-field increases, making it impossible for the response speed of the display element to keep up, resulting in disadvantages such as a decrease in contrast. There is.

[Summary of the Invention] The present invention has been made in view of the above-mentioned points, and provides a display device that can reduce the reduction in luminous efficiency due to blanking time.

[Embodiment 1 of the Invention Hereinafter, an embodiment of the present invention will be explained based on Fig. 1θ, in which the same parts as in Fig. 2 are given the same reference numerals.
In FIG. 0, the part corresponding to the address counter (13) that sequentially reads out each pixel signal of the memory (7) in FIG. and a row address counter (15) corresponding to the designation of the planned element group, and a counter (16) corresponding to FIG. 6 is installed between these two address counters, and the memory specified by the row address generator During the driving period of the corresponding row electrode from is being done. Others are the same as before.

Currently, it is possible to display 2Y'' gradations with n-bit display data for each pixel, but the counter (16) is
To simplify the explanation, let's consider the case where each pixel has 2 bits of data. In this case,
The counter (16) is a quaternary counter. Memory (7)
The relationship between the address and the data written to each address is
For comparison with the above description, FIG. 7 is used. The on/off signal of each pixel is compared with the data A of the memory (7) corresponding to each pixel and the output B of the counter (IB), and A>
It is converted into an on signal when H, and an off signal when A≦B.

The Y electrode drive signal is the Y address; it switches as the counter advances eastward, but since a quaternary counter is provided between the X address counter and the Y address counter, the data at the X address corresponding to the Y electrode drive period is repeatedly read out four times. The electrode drive signal switches 4 times. The time chart is as shown in FIG.

The display shown in FIG. 12 is produced by drive control as shown in this time chart.

That is, the composition of the display for the period tl' to t4' (a)
The screen (e) of the l field is formed by (d). In the figure, an-d3 indicates the display of the period aO to d3 in FIG. 11, and is the same as the display at ao-c13 in FIG. Comparing Figures 8 and 9 of the conventional example and Figures 11 and 12 of this embodiment, the screens displayed in the L field are exactly the same, but as can be seen by comparing the time charts, According to the embodiment, the blanking time required when switching drive signals is reduced;
Decrease in brightness can be reduced. Furthermore, the drive signal ao-do,
al~dl, a2~d2, aa~da convert pixel data A into counter 111 and data B values 0, 1, 2, .
3, and is a signal obtained by converting it into a signal that is on when A>H and off when A≦B, where:
A3 to d3 are drive signals when comparison data B=3, but since the memory signal A is 2 bits, A>3 does not hold. Therefore, all pixels of a3 +b3 +03 +d3 are off (see FIGS. 9 and 12). Therefore, by shifting the phase of the drive signal waveform of the Y electrode, a3, b3
, c3, and d3 (Y1' to Y4'), there is no need to insert blanking time into the Y electrode drive signal, and efficient display becomes possible. Further, the display of each pixel is performed by repeatedly reading out the data from the memory and sequentially comparing it with the counter outputs 0, 1, 2.3 to determine whether the pixel is on or off, and is modulated to a time width according to the data.

Using a matrix display element with rows and m columns shown in FIG.
Part of the drive timing when displaying bit data is shown. This FIG. 13 shows the timing of each part when the Y electrode Yj is being driven. Each 1 corresponding to row j
-m column data 81 to am are repeatedly read out twice at timing A. These are compared with the signals indicated by B to determine whether they are on or off, arranged in a shift register at timing S, latched at timing L, and drive the corresponding X electrodes. To explain a specific pixel, if the data A of that pixel is X (O≦X≦21
1) Data (x) is read out 21'L times at the timing of T o "T2"", sequentially compared with θ~27L-1, converted to on/off data, and transferred to the corresponding pixel by a shift register. This display signal becomes a pulse that rises at T1 and falls at Tx+1, and each pixel is driven with a pulse width according to the data.In addition, each row electrode drive signal has a column electrode By inserting a cutting pulse at the switching timing of the drive signal, the brightness of the entire screen can be adjusted.

[Effects of the Invention] As described above, according to the display device of the present invention, the address counter for sequentially reading out each image signal in the memory is replaced by the column address counter corresponding to the designation of the outer pixel group of the display section and the column address counter corresponding to the designation of the planned pixel group. The counter is provided between both address counters, and the image signal of each external 3 2 element is processed by the counter during the drive period of the corresponding row electrode from the memory specified by the row address generator. By repeatedly reading out a set number of times and controlling pixel on/off, each pixel is driven with a time width that corresponds to the image signal, reducing the blanking time required when switching drive signals and reducing brightness. This has the effect of significantly reducing the

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a general dot matrix display element.
Figure 2 is a configuration diagram showing a conventional display device, Figure 3 (a)
~(d) is a table, the front page shows the pixel position of the display element, the corresponding memory address, and data; FIG. 4 is the operation time chart of FIG. 2; FIG. 5 is an explanatory diagram showing a display example; Figure 6 is a detailed view of a portion of Figure 2, and Figures 7 (a) and (b) are diagrams showing the relationship between memory addresses and data when each address has 2-bit data (4-level gray scale display). Figure 3(b). (c) Correspondence diagram, Fig. 8 is a time chart when displaying 4-gradation shading, Fig. 9 is a display form diagram corresponding to Fig. 8, Fig. 10
Figures 1 to 13 illustrate one embodiment of the present invention.
Figure 0 is a configuration diagram corresponding to Figure 2, Figure 114 is a time chart I, Figure 12 is a slope diagram of Figure 9, and Figure 1 is a diagram corresponding to Figure 2.
FIG. 3 is a drive team chart when an upright m-column matrix display element is used. (1)... Matrix display panel, (3)... Column electrode control circuit, (4)... Shift register, (5)... Row electrode control circuit. (6)...On/off signal 1) converter, (7)...memory, (14)...column address counter, (15)...row address counter. (18)...Counter. Agent Masuo Oiwa 5 Figure 1 Figure 5 Figure 6 Figure 7 Figure 9 (C') (42Z) Cb2) ((J) (d-3) Procedural amendment (voluntary) 59529 Showa year/month Day 2, Invention title display device 3, relationship with the person making the amendment Patent applicant address Chiyo, Tokyo [■2-2-3 Marunouchi, Ward Name (601) Jinhachi Katayama, representative of Mitsubishi Electric Corporation Part 4, Agent address: Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo 5, Detailed description of the invention in the specification subject to amendment, and drawings. 6. Contents of the amendment (1) ) The description "counter" on page 7, line 3 of the specification is corrected to "count". (2) Same book, page 8, line 1θ (7) rB=3, (e) is B
The statement "When B = 4" is corrected to "When B = 3." (3) The statement “said indication” on page 8, line 15 of the same book has been changed to “
"Incorrect display" and compensated for the pressure. (4) The statement "due to an increase in the number of screens" in the first line of page 9 of the same book has been corrected to "due to an increase in the number of screens and high-speed scanning." (5) On page 9, lines 5 and 6 of the same book, the statement ``It was made in view of the situation'' was amended to ``It was made in view of it.'' (6) The statement ``driven.'' on page 13, line 9 of the same book is amended as follows. In addition, the pixel is always off during the period indicated by TO in the figure. Therefore, by switching the row electrode signal during this period, there is no need to provide a blanking time and reduce the row electrode signal, which increases efficiency. (7) In the same book, page 14, lines 4 to 6, the statement ``plays when the drive signal is switched'' has been changed as follows. to correct. "The number of screens that make up one field is one regardless of the gradation of the data, and the scanning speed is constant, which greatly reduces the brightness drop caused by insufficient response speed of the display element or the brightness drop due to blanking time. (8) Correct the figure 4 of the drawing medium temperature as shown in the attached sheet. 7. Inventory drawing of attached documents 16.

Claims (2)

[Claims] (1) A matrix display panel that has a row electrode group and a column electrode group and controls the display of pixels arranged at the intersection of both electrode groups by a combination of driving of both electrode groups, and a memory that stores image signals; A conversion unit that converts memory data into pixel on/off signals, a shift register that arranges the on/off signals to the corresponding column electrodes, a shift register output that is held and latched for the required period, and the latch output is sent to the column electrodes. The drive means for periodically and sequentially driving the row electrodes in synchronization with the driving of the column electrodes is provided, and the image signal of each pixel is read out from the memory a required number of times at a required interval, and the corresponding pixel is turned on and off. In a display device that displays an image with halftones by controlling the off-time of each pixel and making the cumulative on-time width of each pixel proportional to the amplitude of the image signal of the corresponding pixel, each image signal in the memory The address counter is divided into a column address counter corresponding to the column pixel group designation of the display section and a row address counter corresponding to the planned pixel group designation, and a counter is provided between the two address counters to generate the row address. During the driving period of the corresponding row electrode from the memory specified by the memory, the image signal of each column pixel is repeatedly read out the number of times set by the above counter, and each pixel corresponds to the image signal by controlling the on/off state of the pixel. A display device characterized in that it is driven with a time width of (2) The display device according to claim 1, wherein when the counter advances, a cutting pulse is inserted into the row electrode drive signal to adjust the brightness of the entire screen.