JP2776090B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, and
LCDs with slow response speed due to cumulative response
To an image display device.

[0002]

2. Description of the Related Art In recent years, liquid crystal projectors, liquid crystal televisions, etc.
Has adopted a liquid crystal display device. This kind of liquid crystal table
The display device performs gradation display based on gradation data.
You. As a prior art for gradation display, Japanese Utility Model Application
JP-A-113476, JP-A-1-260488, JP-A-Showa
No. 54-53922 are known.

[0003]

SUMMARY OF THE INVENTION A liquid crystal display device
Because the position has a cumulative response,
Therefore, there is a problem that the change of the gradation display is delayed.
In the above-mentioned Japanese Utility Model Application No. 2-1476, the solution is to some extent.
In this prior art, the gradation of a certain pixel is
If the data is larger than the previous gradation data, the gradation data
If the maximum value of the data is smaller than the previous gradation data,
Is to apply the minimum value of the gradation data.
The response speed is faster, but there is
It is still not enough, for example, it cannot be corrected. This invention is
Liquid crystal with low response speed, made in consideration of such circumstances
Even if a display device is used, a gradation table for changes in gradation data
Image display with good follow-up of changes in display and fine correction
It is intended to provide a device.

[0004]

In order to achieve the above object, according to the present invention, there is provided a liquid crystal display device which is scanned N times (N> 2) during one field period of a video signal. In an image display device, a table memory storing a plurality of sets of a plurality of continuous gradation data as N gradation data strings arranged so as to emphasize a change in gradation, and a display data of a previous frame. And now frame display data
According to the comparison result of the comparison means,
Within one frame period.
Specify one set of gradation data strings
Output in the order that emphasizes the change in gray level
Data output means and output by the gradation data output means
The grayscale data string by sequentially supplied to the liquid crystal display device of N gradation data constituting the gradation data sequence in one field period, the response speed of the liquid crystal display device is fast And a driving unit for driving the image display device.

[0005]

[0006]

An embodiment will be described below with reference to FIGS. FIGS. 1 to 14 are diagrams showing an embodiment of an image display device. In this embodiment, light from one light source is converted into an R (red) component, a G (green) component, and a B (blue). The light is decomposed into three light components and irradiates the corresponding three liquid crystal display modules, and each liquid crystal display module synthesizes an image decomposed into three colors of R, G, and B by reflection and transmission. This is an example in which the present invention is applied to a liquid crystal projector that performs enlarged projection on a screen with one projection lens.

FIG. 1 is an overall configuration diagram of the liquid crystal projector 1. In FIG. 1, a liquid crystal projector 1 includes R, G,
The video signals which are separated into three colors of B and input are R, G, B
Image display device 2 for displaying on three liquid crystal panels for
An optical system 4 is provided that combines images displayed on the R, G, and B liquid crystal panels by reflection and transmission based on light from a light source, and enlarges and projects the images on a screen 3 with one projection lens.

The image display device 2 generates a variety of timing signals and supplies these timing signals to the respective circuits. The image display device 2 converts a video signal from a video signal source into a predetermined bit (for example,
A / D converter 1 for converting a digital signal of 5 bits)
2, an R display control unit 13, a G display control unit 14, a B display control unit 15, which performs display control for each of R, G, and B display signals according to a control signal from the timing control circuit 11.
Display control unit 13, G display control unit 14, B display control unit 15
Liquid crystal display device 16, G liquid crystal display device 17, and B liquid crystal display device 1 for driving R, G, B liquid crystal panels by the output of
8 is provided. The detailed description of the image display device 2 will be described later with reference to FIG.

FIG. 2 is a block diagram of the liquid crystal display devices 16, 17, and 18. Since the R, G, and B circuits are composed of the same circuit, the R liquid crystal display device 16 is shown as a representative. As shown in FIG. 2, the R liquid crystal display device 16 includes a vertically divided liquid crystal panel 20, a scanning side driving circuit 21 for driving the upper liquid crystal panel 20A, and a scanning side driving circuit 22 for driving the lower liquid crystal panel 20B. , R signal control circuits 23 and 24 for driving gradation display by the output of the R display control unit 13.

The R liquid crystal driving device 16 applies scanning signals from the upper limit scanning side driving circuits 21 and 22 to the upper and lower scanning line electrodes of the liquid crystal panel 20, and from the signal side driving circuits 23 and 24 to the signal line electrodes of the liquid crystal panel 20. A video signal is applied to control the driving of the liquid crystal pixels where both signal line electrodes intersect. The gray scale signal data output from the R display control unit 13 is supplied to the liquid crystal for 1H, but is first converted to a pulse width (PWM) by the signal side drive circuits 23 and 24. Any one of the signals having the 16 pulse widths is generated in the signal drive circuits 23 and 24, thereby determining the density of each pixel in the selected scanning line electrode. The above operation is repeated every time the selection of the scanning line electrode is switched.

In the following description of the present embodiment, first, technical features will be briefly described for convenience of description. Increase the frame frequency. In the image display device, a period during which one entire screen is scanned is referred to as one frame, and one screen is displayed in one field of a video signal, so that the cycle (frame frequency) is 1 / 60S. The image display device 2 is configured such that the liquid crystal panel 20 is
One screen is displayed four times by scanning four times during S, and the frequency is set to 240 Hz. In order to realize this, in the present embodiment, four frame memories (RAM-A, RAM-B, RAMC, RAMC) are stored in the display control units 13, 14, and 15.
-D) so that the data once stored in the memory is read four times at a predetermined timing. It should be noted that the two fields of the video signal are also referred to as a frame, and in this specification, the term "frame" is used for both the meaning of one scan of the liquid crystal panel and the meaning of the two fields of the video signal.

A vertically divided panel is used. As shown in FIG. 2, the scanning-side driving circuit of the liquid crystal driving device 16 for driving the upper and lower divided liquid crystal panel 20 is divided into a scanning-side driving circuit 21 and a scanning-side driving circuit 22. The electrode and the scanning line electrode of the lower liquid crystal panel 20B are selected. That is, under the condition that the margin becomes higher as the duty of the liquid crystal becomes larger, the margin becomes insufficient when the number of scanning line electrodes is increased, but the duty can be reduced by half by performing such an operation. , The selection time for one scan is doubled. However, in order to simultaneously display data as described above, for example, X1 data and X241 data must be obtained at the same time, and therefore at least one of the data must be read from the memory. In this embodiment, this memory is referred to as the RAM-A, RAM-B, RAM-C,
This is realized by using the RAM-D.

The conversion of the gradation signal is performed using the ROM table. As shown in FIG. 3, when the gradation signal of a certain pixel on the liquid crystal panel 20 is “2” in a certain frame, the response speed of the liquid crystal is small even if the gradation signal becomes “10” in the next frame. It will slowly follow from "2" to "10". Considering this as luminance, as shown by the solid line in FIG. 4, even if the gradation signal “10” continues four times, a response delay occurs when the luminance of “2” becomes the luminance of “10”.

Therefore, in the present application, in such a case as shown by the broken line in FIG. 3, the response speed is greatly increased as shown by the broken line in FIG. ing. Similarly, when it becomes "3" in the next frame, this "3" is converted to "0" to improve the fall response speed.

In order to convert the gradation signal, a ROM table is provided in the ROM, in which values of the previous frame and the current frame are tabulated, and the gradation signal is converted with reference to the ROM table to increase the speed. To do. For example, if the previous frame is “0”, the current frame is “0”, the table data is “0”, the previous frame is “2”,
If the frame is “10” this time, the table data “1”
5 ". Thus, the display data (gradation signal) of the video signal is not directly supplied to the liquid crystal panel,
The table is transformed using a table.

When the current frame is "10", RO
If “15” is given by the M table, if the next frame is “10”, the previous frame is “10”,
Since the frame is “10” this time, for example, “10” is read from the ROM table. In this case, as long as "10" continues in the next frame, "10" is read from the ROM table, and the data converges on "10".

If it is sufficient to simply increase the response speed, the maximum value is given if the response value is larger than the previous value, and the minimum value is given if the response value is smaller than the previous value. Shoot).
Therefore, in practice, an optimum value is obtained in advance by simulation or the like, and this is stored in the ROM table. Further, since the optimum value differs depending on the temperature, a plurality of ROM tables corresponding to the temperature may be prepared.

The gray scale signal is decomposed to realize the gray scale in four steps. This makes it possible to reduce the number of transmission bits of the drive system (which will be described in detail below). First, the advantage of reducing the number of transmission bits will be described. For example, if the gradation signal obtained by the A / D converter 12 is 5 bits, 000
There are 32 tones from 00 to 11111. In this case, shift registers (described later) in the display control units 13, 14, and 15 shown in FIG. 1 must be operated with 5 bits, and memory access must be performed with 5 bits per pixel. However, there is a demand to operate the liquid crystal driving devices 16, 17, and 18 with 3 bits in order to reduce the number of wirings. Therefore, the number of bits in the liquid crystal driving device is reduced from, for example, 5 bits to 3 bits by realizing the gradation in four times as described below.

That is, as described above, one pixel is displayed four times and the frequency is set to 240 Hz. This means that the same data is displayed four times. For example, in the conventional case, one screen is 1/60 and data is “5” as shown in FIGS. 5A and 5B, but one screen is four times as shown in FIG. 5C. Is displayed in each of the four divided areas. That is, 00000-1111 in 5 bits
Instead of representing one 32 gradations, the present application divides one screen into four times, each of which is represented by 3 bits (see FIG. 5D). For example, when the original 5-bit data is “0”, FIG.
As shown in (e), each of the 3-bit data divided into four times may be represented by "0", "0", "0", and "0".
When the bit data is "31", as shown in FIG.
It divided the data of it into 4 times, "7""7""7"
What is necessary is just to display "7". As described above, since the liquid crystal operates depending on the effective value of the applied voltage, the same result can be obtained by averaging even if the liquid crystal is divided into four times. That is, 3bit
Can obtain only eight gradations from 0 to 7, but by dividing this into four times, eight gradations can be expressed by four combinations, and 28 gradations can be realized by 3 bits × 4.

The above is specifically described with reference to the waveform diagram shown in FIG. In FIG. 6, the solid line in FIG.
The waveform of the gray scale signal at the time is shown.
The signal waveform at the time of z is shown.

If the gradation signal waveform is "1" as shown in FIG.
(See FIG. 6B), and when the gradation signal waveform is “20” as shown in FIG. 6C, this is divided into four times to “5”.
If “5”, “5”, and “5” are used, 5 × 4 = 20 and the width (that is, gradation) is the same as “20” in the case of 5 bits (see FIG. 6D). Similarly, when the gradation signal waveform is “21” as shown in FIG.
If it is divided into "5", "5" and "5" four times, it becomes "21" (see FIG. 6 (f)). Further, when the gradation signal waveform is “31 (f
"ull)", "7" as shown in FIG.
If “7”, “7”, and “7” are used, 7 × 4 becomes “28”.
Therefore, in the conventional example, 5 bits are required to express 32 gradations, but in the present application, the waveform is divided into 3 bits.
28 gray levels can be expressed by t × 4. In addition, 5bit
In the case of, the gradation expression of 0 to 31 can be performed, but in the case of 3 bits, only the gradation of 0 to 28 can be expressed.
8, 29, 30, and 31 are all full (FIG. 6)
(G)).

The scanning electrodes are driven two by two. As shown in FIG. 7, if there are 480 scanning lines, one field has 240 scanning lines. In the case of a CRT, interlaced scanning is performed to display odd lines 1, 3, 5, 7,... First, and then display even lines 2, 4, 6,. If the duty is high, the operation margin (voltage drive ratio) decreases, so it is desirable to avoid skipping of the scanning lines. Therefore, as shown in FIG. 7A, when the fields are originally displayed as 1, 3, 5, and 7, as shown in FIG. 7A, the line 1 is the line 2, the line 3 is the line 4, and the line 5 is the line 6. Simultaneously, the combination is changed for the next field, and as shown in FIG.
And This is operated by the liquid crystal driving side irrespective of the signal side. For example, as shown in FIG. 2, the line 2 (X2) which is not originally scanned is turned on together with the line 1 (X1). 3 (X3) and line 4 (X4) are turned on together.

FIGS. 8 to 14 show an embodiment of an image display device based on the above basic concept. First, the configuration will be described. FIG. 8 is a block diagram of the image display device 2. The image display device 2 is composed of three identical circuits of R (red), G (green), and B (blue). , R) (that is, the timing control circuit 11, the A / D converter 12, the R display control unit 13, and the R liquid crystal display device 16) are shown as representatives. In FIG. 1, an image display device 2 includes a timing control circuit 11 that generates various timing signals and generates a control signal based on the timing signals, and display control circuits 51 and 5 that perform display control by a control signal from the timing control circuit 11.
2. signal-side drive circuits 51 and 52 for driving gradation display by the output of the display control circuit 51; scanning-side drive circuit 21 for driving the liquid crystal panel 20 based on a predetermined timing signal;
22. Here, the timing control circuit 11 and the display control circuit 51, which are control systems, operate in 5 bits, and the signal side drive circuits 23, 24 and the scan side drive circuits 21, 22 in the drive system operate in 3 bits.

The timing control circuit 11 includes a V counter 62 for counting the vertical synchronizing signal Φv, and a timing generation circuit 63 for generating various vertical timing clocks while taking timing based on the output of the V counter 62 (the operation timing is shown in FIG. Reference), voltage controlled oscillator (OSC) 6
4. A PLL circuit 67 comprising a phase comparator 65 and an H counter 66 for comparing and locking the phase of a signal obtained by dividing the output of the horizontal synchronizing signal Φ _H and the output of the OSC 64, and timing based on the output of the H counter 66 of the PLL circuit 67. A timing generation circuit 68 for generating various horizontal timing clocks, and a control circuit 69 for generating various control signals based on the outputs of the timing generation circuits 63 and 68.

The output of the A / D converter 12 is a liquid crystal panel 20
The D / D control signal input to the display control circuit 51 for controlling the upper side and the display control circuit 52 for controlling the lower side, respectively, and generated by the control circuit 69 is also the same as the display control circuit 51,
52. Although the hardware configuration of the display control circuit 51 is the same as that of the display control circuit 52, the operation timing of each internal circuit is different.

The display control circuit 51 decodes the D / D control signal from the timing control circuit 11 and decodes the RAM-A 73, RAM-B 74, and SOM (Se
rialOut Memory) —Op decoder (operation decoder) 71 that outputs write enable signals WEA and WEB and read pulse RS (see FIG. 11) that enable writing operations of A75 and SOM-B76, and converts the signals into 5-bit digital signals. A shift register (SIM (Serial In Memory) -A) 72 for storing the obtained video data (for example, R (red) data RD) for one scanning line (1H) and a shift register (SIM-A) 72 1H data R
D is sequentially written at the timing of the write enable WEA shown in FIG. 11, and the 1H data RD stored in the shift register (SIM-A) 72 is stored in the write enable WEB shown in FIG. Frame memory (RAM-B) 74 which is sequentially written at timing
And a shift register (SOM-A) 75 for performing a parallel-serial conversion operation of reading out the video data written in the RAM-A 73 at once and storing the same row at the timing of the pulse RS, and a video written in the RAM-B 74. A shift register (SOM-B) 76 for performing a parallel-serial conversion operation for reading and storing the same row at a time at the timing of a read pulse RS and storing a ROM table 100 shown in FIG.
And a ROM 77 for sequentially comparing the data of the previous frame and the data of the current frame with the data stored in the SOM-B 76 as the ROM address and outputting a data conversion value based on the ROM table 100 to the signal side driving circuit 55. I have.

Similarly, the display control circuit 52 decodes the D / D control signal from the timing control circuit 11 and decodes the RAM-C83, RAM-D84, S
Write enable signals WEC, WED and read pulse R for enabling the write operation of OM-C85 and SOM-D86
OP decoder 81 that outputs S (see FIG. 11) and 5 bits
Video data (for example,
FIG. 11 shows a shift register (SIM-C) 82 for storing R (red) data RD) for one scanning line (1H) and a 1H data RD stored in the shift register (SIM-B) 82. A frame memory (RAM-C) 83 to which data is sequentially written at the timing of the enable WEC, and 1H data R stored in a shift register (SIM-B) 82
D are sequentially written at the write enable WED timing shown in FIG.
A shift register (SOM) for performing a parallel-serial conversion operation of reading out video data written in the M-C83 at once and reading and storing the same row at the timing of a pulse RS.
-C) 85, a shift register (SOM-A) 86 for performing a parallel-serial conversion operation for reading and storing the same row at a time at the timing of a read pulse RS and reading and storing video data written in the RAM-D84, and the ROM table 100. And the SOM-C85 and the SOM
And a ROM 87 which sequentially compares the data of the previous frame and the data of the current frame with the data stored in -D86 as a ROM address and outputs a data conversion value based on the ROM table 100 to the signal side drive circuit 56.

In this embodiment, assuming that the number of pixels of the liquid crystal panel 20 is 736 dots per line, the shift registers (SIM-A) 72 and (SIM-B) 82
Is a 736-stage shift register. This SIM-A
72, data stored in the SIM-B 82 are stored in the frame memories RAM-A 73, RAM-B 74, RAM-C 8
(3) Input to RAM-D84. The operation in this case will be described later (see FIGS. 10 and 11).

The data processed by the contents of the ROM 77 of the display control circuit 51 is output to the signal side drive circuit 23, and the data processed by the contents of the ROM 87 of the display control circuit 52 is output to the signal side drive circuit 24. You. The signal side drive circuits 23 and 24 perform gradation expression with 3 bits based on the data output from the display control circuits 51 and 52 (the number of bits for gradation expression is 5 bits inside the display control circuits 51 and 52). (32 gradations).

Further, the scanning side drive circuit 21 is shown in FIG.
The liquid crystal panel 20 is driven at the timing shown in FIG.

Further, as shown in FIG. 2, the liquid crystal panel 20 has 736 pixels and the number of scanning line electrodes is x1-2.
40, × 241 to × 480 are used for R, G, and B. In this case, the number of pixels for projection display is (number of pixels for display) = 480 × 736 × 3, and the amount of data is data amount = (number of pixels for display) × 5 bits. Further, the duty is as follows: Duty = 1/480 × 2 (because it is vertically divided) × 2 (to select two lines of scanning electrodes) = 1/120.

FIG. 9 shows the RO stored in the ROMs 77 and 82.
FIG. 3 is a diagram showing a configuration of an M table 100. In FIG. 9, the ROM table 100 is created in accordance with both the concept of the conversion of the gradation signal described in FIGS. 3 and 4 and the concept of the decomposition of the gradation signal described in FIGS. 5 and 6. It is a table and has the following features.

That is, from the viewpoint of performing the conversion of the gradation signal, as shown in FIG.
To 31 and 5 bits in the current frame in the horizontal direction.
From the previous frame 0 to 3
For each table value tabulated by 1 and current frames 0 to 31, 3 bits are divided into four times and the data conversion values 0 to 7 are divided.
(7 is the maximum value because it is 3 bits). This data conversion value is gradation signal data set so that the response speed is as high as possible based on the movement between the previous frame and the current frame, and the optimum value is calculated and stored in advance by simulation or the like. In this embodiment, the data conversion value is 3 bits for the following reason.
Is stored as data. For example, the previous frame is “2” and the current frame is “15” (all 5 bits information)
In this case, the 3-bit maximum value "7" is read from the ROM table 100, and the response speed can be improved by using the data conversion value "7" read from the ROM table 100.

On the other hand, from the viewpoint of decomposing the gradation signal, as shown in FIG. 9, the data conversion values 0 to 7 are provided for each of the three times represented by dividing one screen into four times. To do. Therefore, data of 3 bits × 4 is read from the ROM table 100 accessed by 5 bits, and the driving system at the subsequent stage can be operated by 3 bits.

For example, as shown in FIG. 9, when the previous frame is "2" and the current frame is "15", the table value is "7777", so the first time the 3-bit data conversion value "7" is 2 "7" is read out the third time, "7" is read out the third time, and "7" is read out the fourth time. If the previous frame is “15” and the current frame is also “15”, “444”
3 ", the first time is a 3-bit data conversion value" 4 ",
"4" is read for the second time, "4" is read for the third time, and "3" is read for the fourth time.

As described above, by using the ROM table 100, the conversion and resolution of the gradation signal can be realized at the same time, so that the response speed can be improved by the conversion of the gradation signal and the driving system can be improved by the decomposition of the gradation signal. Contradictory objectives of reducing the number of transmission bits of the data can be achieved at the same time.

Next, the operation of this embodiment will be described. Overall Operation First, in the timing control circuit 11, the PLL circuit 67 locks the phase and frequency of the horizontal synchronizing signal Φ _H created from the video signal and the signal divided by the OSC 64 and the H counter 66. The output of the H counter 66 constituting the frequency dividing circuit is input to the timing generating circuit 68,
The timing generation circuit 68 creates various timing clocks for H (horizontal). The vertical synchronizing signal Φv is input to the V counter 62, and the V counter 62 counts the number of Hs while synchronizing with Φv from the video signal based on the count output of the H counter 66. Create various timing clocks in (vertical).

On the other hand, the R, G, and B video signals are converted into 5-bit digital signals by the A / D converter 12, and the SIM-A72 and SIM-B8 of the display control circuits 51 and 52 are used.
2 is output. In the display control circuits 51 and 52, A / D
The data RD of the video signal R (red) for 1H by SIM
-A72, and the data stored in the SIM-A72 are write enable WE as data of the A and B fields.
The data is sequentially written to the RAM-A 73 at the timing of A (FIG. 11). Similarly, the data in the CD field is stored in the RAM-B at the timing of the write enable WEB (FIG. 11).
74 are sequentially written. RAM-A73, RAM-B
The video data written in 74 is a read pulse RS
(FIG. 11) shows that the same rows are each SOM-A75,
Read to SOM-B76, SOM-A75, SOM
The data of B76 as the address of ROM,
7, the data of the previous frame and the data of the current frame are sequentially compared. Then, the data to be displayed on the same pixel is compared, and the ROM table 100 stored in the ROM 77 is compared.
Is sent to the signal side drive circuit 23 in accordance with the contents of the above. Here, since the image display device 2 has a frame frequency of 240 Hz / vertical division,
One line of data is read out during the H period and displayed on the liquid crystal panel 54 through the signal side drive circuit 23. The lower screen is also displayed in the same procedure, and display control is performed for G and B in the same manner as for R.

Operation in the display control circuits 51 and 52 1H of the data of the video signal R after the A / D conversion is SI.
M-A72 and SIM-B82, and this 1H data is stored in frame memories RAM-A73 and RAM-B7.
4, RAM-C83 and RAM-D84. The operation in this case will be described with reference to FIGS.

FIG. 10 shows f ₅ out of the fields f _{1 to} f _8.
The is a diagram for explaining the write operation of RAM-A~RAM-D when taken as an example, FIG. 11 is a field f ₅
Is a timing chart showing the detailed operation timings of respective parts in ~f _8.

As shown in FIG. 11, first, the field f
_{In 5} , the upper half data (H1 to H120) is written to the RAM-A 73 by the write enable WEA,
The lower half of the data of the field f ₅ (H121~H24
0) is RAM-C83 by the write enable WEC.
Is written to. Thereafter, RAM becomes a field f ₆ Mataue half of data by the write enable WEA
-A73, and the lower half of the data is written to the RAM-C83 by the write enable WEC. The upper half of the data becomes a field f ₇ is written to RAM-B74 by write enable WEB, RAM lower half of the data is the write enable WED
-Is written to D84. Thereafter, when the field f ₈ Mataue half of the data is written to the RAM-B74 by write enable WEB, the lower half of the data is written to the RAM-C84 by write enable WEC. Therefore, the display control device 52 uses the SIC shown in FIG.
Data field f ₅ H1 by A is SIM-A7
2 and the field f ₅ H12 by SICB
1 is taken into the SIM-B 82. As described above, the SIC-A72 and the SIC-B82 take 1 H to individually take in data, but the frame memories (here, the RAM-A73 and the RAM-C83) are written by the latch clock line by line. It is. Similarly, in the next frame, the frame memory (RAM-B74, RAM-D84)
Is written for each line.

[0042] Thus, the data of f ₂ at the timing of the field f ₂ as shown in FIG. 10 is written into the frame memory (f ₂ W), at the timing of f ₃ to write the data of f ₃ in the frame memory ( f ₃ W). Hereinafter, likewise at the timing of f ₈ writes data of f ₈ (f
₈ W).

[0043] performed in this case, will be described by focusing on the timing of the field f _5, it is the timing of f ₅ data f ₂ lead (f ₂ R) 4 times. relationship between the frame memory for one f ₂ R is shown in the enlarged portion of FIG. 10, in one f ₂ R fields f ₅ as shown in FIG, f ₂ the upper data from the RAM-A73 ( H1R H2
R H3R~H120R) is, f ₄ from the RAM-B74
Upper data (H1R H2R H3R to H120R)
But, f ₂ lower data from the RAM-C83 (H240R
H239R to H121R) are converted from RAM-D84 to f ₄
The lower data (H240R H239R to H121R) is read out (here, H represents each horizontal number). Further, in the other times and other fields of f ₂ R, similarly, from the frame memory, the upper half for the previous screen,
The upper half data for the current screen, the upper half for the previous screen, and the lower half for the current screen are read. Here, RAM-C83, R
When reading the lower data from AM-D84, H240
The reason for reading in the reverse direction from to H121 will be described later.

As described above, the shift register (SIM)
−A) 72 receives 736 dots of data for 1H, and RA of the 736 data stored in the SIM-A 72.
The M-A 73 and the RAM-B 74 are accessed. RAM
736.times.5 bits of data are read out from the RAM 73-A73 and these data are read out from the SOM-A85,
Output to MB86. SOM-A85, SOM-B
Reference numeral 86 denotes the data read from the RAM-A 73 and the RAM-B 74 7
36.times.5 bit data is read out by a read pulse RS (FIG. 11) as in a parallel-serial conversion in which the same row is arranged at a time, and R.times.
Access OM77. Here, 5 bits are accessed 736 times, which is performed during 1 / 2H. That is, one screen is divided into four to increase the frame frequency.
Since the frequency is displayed twice and set to 240 Hz, 1 /
Although the access must be made by 4H, in the present embodiment, since the upper display control circuit 51 and the lower display control circuit 52 share (divide into two), the access is made 736 times at 1 / 2H. The same applies to SOM-B86.

Here, the contents of RAM-A 73 and RAM-
Since the displacement of one frame of the contents of B74, for example, the contents of the field f ₅ and the field f ₇ in the case of the aforementioned 2
The ROM 77 is accessed as an input. From the ROM 77 accessed with 5 bit data, the converted 3bi
Since the data of t is read and output to the signal side drive circuit 23, the drive system of the liquid crystal panel 54 can be operated with 3 bits (see FIG. 12). Therefore, FIG.
Put the frame memory data f ₂ (a), the frame memory data f ₄ because data is needed at the same position in the next frame is to compare the data of the f ₂ placed so that to compare data of f ₂ and f ₄ at f ₅ in. This causes the display to be delayed by a frame. In order to realize the above, the image display device 2 of the present embodiment has a frame memory of four blocks, that is, RA.
M-A73, RAM-B74, RAM-C83, RAM
-D84.

As described with reference to FIG. 12, the liquid crystal drive system for driving the liquid crystal panel 20 can be operated with all three bits, so that the circuit scale can be greatly reduced. In this case, each of the R, G, and B systems has 3 bits.
It can be operated, and the information amount for 5 bits can be obtained while operating at 3 bits.

Operation in Liquid Crystal Drive System FIG. 13 is a waveform diagram showing drive waveforms of the scan side drive circuits 21 and 22. In this embodiment, since the scanning electrodes are driven two by two (see FIG. 7), as shown in FIG. 13, in one field (f ₁ ), line 2 (X2) and line 3 (X
3), line 4 (X4) and line 5 (X5), and the next two fields (f ₂ ), line 3 (X3) and line 4
The combination is shifted such as (X4).
As a result, the driving margin of the liquid crystal is increased.

Further, in this embodiment, in order to drive the liquid crystal panel 20 by AC, a method of inverting the driving waveform every one selection period of the scanning line electrode is adopted. Further, in this embodiment, when scanning the vertically divided liquid crystal panel 20, both the upper liquid crystal panel 20A and the lower liquid crystal panel 20B do not scan in the quasi-direction as shown in FIG. As shown in FIG. 2B, the lower liquid crystal panel 20B scans in the reverse direction. By driving in this manner, the connection line between the upper liquid crystal panel 20A and the lower liquid crystal panel 20B can be made inconspicuous. For this purpose, the RAM-C83, RAM-
When data is read from D84, the data is read in the opposite direction from H240 to H121 as shown in FIG.

As described above, the display control circuit 51 of the image display device 2 of this embodiment includes the SIM-A 72 for storing 5 bit video data for one scanning line (1H),
RAM-A73 which sequentially writes at the timing of 1H data WEA stored in A-72 and a shift register (SI
(M-A) RAM-B 74 that sequentially writes at the timing of 1H data WEB stored in 72, and SOM-A 75 that reads the data written to RAM-A 73 and reads and stores the same row at a time at the timing of pulse RS. And R
Read data written to AM-B74 and read pulse RS
SOM that reads out and stores the same row at the same time
-B76 and the ROM table 100. The data stored in the SOM-A75 and the SOM-B76 are used as ROM addresses, and the data of the previous frame and the data of the current frame are sequentially compared.
And a ROM 77 that outputs a data conversion value based on the signal to the signal-side driving circuit 55. The ROM 77 decomposes the gradation signal and divides the gradation signal into four times.
Since the gradation signal is converted by comparing the motion between the previous frame and the current frame using the M table 100,
One ROM table 100 can simultaneously achieve the contradictory objectives of improving the response speed by converting the gradation signal and reducing the number of transmission bits of the drive system by decomposing the gradation signal. That is, in this embodiment, the driving system is 3 bits.
Even in this case, 28 gradations close to 32 gradations (5 bits) of the control system can be realized, and all the driving systems can be operated with 3 bits.
The image quality of 5 bits can be realized while operating at t.

In this embodiment, the image display device is applied to a liquid crystal projector using, for example, an STN. However, the present invention is not limited to this, and can be applied to all devices using a table. Needless to say,

In this embodiment, the gradation signal is divided into four times. However, it goes without saying that any signal may be used as long as the gradation signal is decomposed.

Further, the number of control bits and R
The number of bits of the OM table is not limited to the embodiment described above, and any number can be used.

Further, it goes without saying that the circuits, the number of pixels, the types, etc., constituting the image display device, the liquid crystal panel and the like are not limited to the above-described embodiments.

[0054]

According to the present invention, a liquid crystal display having a low response speed is provided.
Even if a display device is used, gradation display for changes in gradation data
Image display device with good follow-up of
Can be obtained.

[0055]

[0056]

[0057]

[0058]

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a liquid crystal projector.

FIG. 2 is a block diagram of a liquid crystal display device of the image display device.

FIG. 3 is a waveform chart for explaining conversion of a gradation signal of the image display device.

FIG. 4 is a waveform chart for explaining a response speed of a gradation signal of the image display device.

FIG. 5 is a diagram for explaining decomposition of a gradation signal of the image display device.

FIG. 6 is a waveform chart for explaining the decomposition of a gradation signal of the image display device.

FIG. 7 is a diagram for explaining driving two scanning electrodes of the image display device at a time.

FIG. 8 is a block diagram of the image display device.

FIG. 9 is a diagram showing a structure of a ROM table of the image display device.

FIG. 10 is a waveform chart for explaining the operation of the image display device.

FIG. 11 is a waveform chart for explaining the operation of the image display device.

FIG. 12 is a diagram illustrating that the number of transmission bits of a drive system of an image display device is reduced.

FIG. 13 is a waveform chart for explaining the operation of the liquid crystal drive circuit of the image display device.

FIG. 14 is a diagram for explaining a method of driving the scanning electrodes of the image display device.

[Explanation of symbols]

Reference Signs List 1 liquid crystal projector 2 image display device 11 timing control circuit 12 A / D converter 13, 14, 15 display control unit 16, 17, 18 liquid crystal display device 20 liquid crystal panel 20A upper liquid crystal panel 20B lower liquid crystal panel 21, 22 Scan-side drive circuit 23, 24 Signal-side drive circuit 51, 52 Display control circuit 71 OP decoder 72, 82 Shift register (SIM-A, SIM-
B) 73, 74, 83, 84 frame memory (RAM-
A, RAM-B, RAM-C, RAM-D) 75, 76, 85, 86 shift register (SOM-
A, SOM-B, SOM-C, SOM-D) 77, 78 ROM 100 ROM table

Continued on the front page (72) Inventor Hideki Mori 2-229 Sakuragaoka, Higashiyamato-shi, Tokyo Casio Computer Co., Ltd. Tokyo office (56) References JP-A-1-260488 (JP, A) JP-A-2- 1812 (JP, A) JP-A-3-174186 (JP, A) JP-A-2-113476 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) G09G 3/36 G02F 1 / 133 545

Claims (1)

(57) [Claims] 1. An image processing apparatus comprising: N times (N times) during one field period of a video signal;
> 2) In an image display device having a liquid crystal display device to be scanned, a plurality of continuous sets of a plurality of gradation data are stored as N gradation data strings arranged so as to emphasize a change in gradation. Table memory, and compare the display data of the previous frame with the display data of the current frame.
In one frame period according to the comparison means to be compared and the comparison result of the comparison means.
The tone data string stored in the table memory
Is specified, and the gradation data
The grayscale data output means for outputting the grayscale data in the order in which the grayscale data is output, and the grayscale data output from the grayscale data output means. A driving unit for sequentially supplying tone data to the liquid crystal display device to drive the liquid crystal display device so that the response speed of the liquid crystal display device is increased.