JP2954329B2 - Multi-tone image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention controls the electro-optical characteristics of a signal voltage written in a certain selection period and controls the electro-optical characteristics of the signal voltage during a period other than the selection period to maintain a display state. The present invention relates to an image display device in which a display element such as an active matrix type liquid crystal is configured as a pixel, and more particularly to a multi-tone display of an image by controlling a signal voltage holding period according to a level of a video signal to be displayed. The present invention relates to a multi-tone image display device that performs the following.

[Conventional technology]

FIG. 18 is a schematic diagram showing a conventional example of a configuration of an active matrix liquid crystal display device.

In the figure, DR is a data driver circuit, SC is a scanning circuit, GB is a gate bus, DB is a data bus (drain bus), Tr is a transistor (FET), Cr is a liquid crystal cell, and CE is a common electrode.

In FIG. 18, an active matrix liquid crystal panel is configured by arranging a pixel including an active circuit element such as a transistor Tr and a liquid crystal cell Cr at each intersection of a gate bus GB and a data bus DB. The transistor Tr is selected by the gate bus GB, and a voltage signal is written from the data bus (drain bus) DB to the liquid crystal cell Cr via the transistor Tr. The liquid crystal cell Cr functions as a capacitor for storing the written voltage, and at the same time, performs display by controlling the electro-optical characteristics by the held voltage. By varying the level of the voltage signal to be written to the liquid crystal cell Cr, multi-tone display is performed.

Such an active matrix liquid crystal display device is, for example, a “flat panel display '90” (Nikkei BP 1
Although described on pages 113 to 115 (November 1, 990), intermediate display is performed by a method of appropriately applying an analog voltage according to display luminance to a plurality of data buses of an active matrix liquid crystal panel.

On the other hand, using a binary display panel, such as a plasma display, which emits light when a sustaining pulse sufficient to maintain light emission is applied, and emits no light when not applied,
An example of an image display device that realizes 2 ⁿ gray scale display by pulse width modulation by selecting each pixel (n + 1) times in one field and controlling the number of sustain pulses to be applied is disclosed in No. 16379 and Japanese Patent Application Laid-Open No. 1-163795.

[Problems to be solved by the invention]

In the first prior art, a data driver circuit (horizontal scanning optical path) for driving a data bus DB in FIG.
The DR samples an analog video signal for one scanning line sent in time series through a signal path (not shown), holds the sampling, and synchronizes with the timing of the scanning signal of the gate bus GB, It is necessary to have as many circuits for outputting the held analog sampling signals as the number of data buses DB.

If the output voltages of a large number of analog sampling circuits required in this way vary, the brightness will vary in halftone display, causing display unevenness. Therefore, the output voltage accuracy of the sampling circuit is required. An analog horizontal scanning circuit (data driver circuit) that satisfies such a requirement has a problem that it is difficult to reduce the size, cost, and power consumption because the circuit scale is large.

Further, for example, S.I.D., '90, Digest (1990), pp. 220 to 223 (SID'99DIGEST (19
90) NCAP (Nemati) described in PP220-223)
c Curvilinear Aligned Phase) Even if you try to drive a display device with a high driving voltage of several tens of volts, such as a liquid crystal,
In general, the expansion of the dynamic range (that is, the adoption of a process with a large maximum rated voltage) leads to a decrease in analog sampling speed, and there is a problem that a video signal cannot be sampled with high resolution. That is, high definition of the display panel is hindered.

In the second prior art, the voltage output by the horizontal scanning circuit is binary even when displaying a halftone, and the signal to be handled is digital data. Therefore, there is an advantage that a horizontal scanning circuit having a small circuit scale, a small variation in output voltage, a high speed and a high withstand voltage is easily obtained.

However, a display device such as an active matrix type liquid crystal cannot perform halftone display by pulse number modulation because there is no signal corresponding to a sustain pulse of a plasma display, and furthermore, A / D described in the second prior art. The contrast / brightness cannot be adjusted over a wide range beyond the adjustment range limited by the input dynamic range of the D converter. Also, there is no mention of an AC drive technique that is commonly employed as an effective technique for improving the reliability of a liquid crystal cell, since the subject is a plasma display.

Further, in the second prior art, when an attempt is made to increase the number of display gradations, the number of times of selecting each row in one field increases, so that the time required for selecting one row is shortened. In some cases, scanning cannot be performed with a liquid crystal panel.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to use a digital horizontal scanning circuit having a small circuit size and high withstand voltage easily, and to realize a multi-tone image with a highly reliable active matrix liquid crystal panel. A display device is provided.

[Means for solving the problem]

To achieve the above object, in the present invention, in order to perform halftone display using a digital data driver, a period during which the voltage written to the display cell of each pixel is held during the selection period is used instead of the sustain pulse number modulation. Along with the adoption of the pulse width modulation method for modulation, the display effective voltage is increased by driving using almost all of the field period, and the number of times of selecting each row in one field of the video signal to be displayed is reduced, and many gradation displays are performed. In order to make it possible to perform the above, a thinning drive by analog processing is also used.

[Action]

For example, an analog video signal to be displayed is 8-bit A / D
When performing pulse width modulation by 8-bit output obtained by digitizing the converter, the A / D converter output of the least significant bit (LSB, which is referred to as b _0), for example,
Assign a signal holding period of a ₀ , and assign the next upper bit (b ₁ )
assigns a signal holding period for a _1, the Likewise most significant bit (MSB, which is referred to as b ₇₎ allocating a signal hold period of a _7.

Then, the output voltages V _N , V _{S of the} horizontal scanning circuit are determined according to the state of each bit 0, 1 of the output data b _{0 to} b ₇ of the A / D converter.
Will be assigned.

At this time, assuming that the response time of the display element is sufficiently shorter than the signal holding period, the luminance of the display element is given by the following equation.

Here, f (V _N ) and f (V _S ) indicate the luminance when the voltages V _N and V _S are applied to the display element, respectively, and A is equal to the period of one field. It is.

If the signal hold period a _i are set to ^{_{a i ≒ 2 i · a o}} ...... (3), in combination with A / D converter output b _i, enables luminance control by pulse width modulation, multi A gradation display can be realized.

From the above equation (1), the maximum luminance lmax and the minimum luminance lmin are obtained as follows.

lmax ≒ f (V _S ) (4) lmin ≒ f (V _N ) (5) _{Let the} contrast ratio be CR and define it as lmax / lmin.

_{C R ≡lmax / lmin ≒ f (} V S) / f (V N) ...... (6) Thus, by adjusting the output voltage V _S, V _N of the horizontal scanning circuit, respectively the contrast C _R and the lowest Brightness lmin
Can be adjusted.

Further, assuming that the response time of the display element is longer than the signal holding period and the luminance of the display element depends on the average applied voltage, the luminance of the display element is given by the following equation.

When the maximum luminance lmax and the minimum luminance lmin are obtained from the above equation (7), the above equations (4) and (5) are established similarly to the case obtained from the above equation (1). Therefore, similarly, when the response time of the display element is long, the output voltage V _S of the horizontal scanning circuit is
By adjusting V _N , the contrast and the minimum luminance can be adjusted.

Furthermore, the retention period a ₇ assigned to the most significant bit b ₇ to 2 minutes, by 2 rounds of selection drive, the maximum signal holding period is halved, the a _7/2. Thus, even if signal leakage as a capacitor occurs in each display element, the maximum period to be held can be halved, so that signal attenuation due to leakage is reduced by half or less, and the reliability of gradation display is improved.

In addition, when a liquid crystal element that requires AC driving to ensure reliability is used as a display element, each display element is usually driven by a signal whose polarity is inverted for each field, and AC driving is realized in a two-field cycle. . However, if the signal changes between fields as in the case of displaying a moving image, etc., it is not possible to perform full AC conversion. Field in these circumstances, when driving the same polarity display device, when the change to all the A / D conversion data b _i are all "1""0", the maximum DC component represented by the following formula
V _DC will be applied.

(Is used herein in the above (2) relationship.) In contrast, the retention period assigned to the uppermost bit b ₇
and a a ₇ to 2 minutes, if the giving of opposite polarity signals, respectively, do not have to consider the DC component even if signal changes between fields regarding the most significant bit b _7. At this time, the maximum DC component V _DC is represented by the following equation.

(Here, from the above equations (2) and (3), Was used. ) Thus, the retention period assigned to the most significant bit b ₂
By dividing _a7 into two and giving signals of opposite polarities, the maximum DC component _VDC at the time of a signal change between fields can be halved, so that the reliability of the display element can be improved.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Before that, a reference example that is useful for understanding the present invention will be described.

FIG. 1 is a block diagram showing a reference example of the present invention.
The reference example is a reference example directed to a multi-tone display device using pulse width modulation in field time division scanning as a typical example.

In FIG. 1, the multi-gradation display device includes a video signal input terminal 1, a video signal processing circuit 2, an A / D converter 3, a memory 4,
A vertical scanning pulse generating circuit 5, a horizontal scanning pulse generating circuit 6, an AC control circuit 7, a vertical driver 8, a horizontal driver 9, an active matrix display panel 11, and a synchronizing signal are separated from an input video signal, and based on the synchronizing signal. It comprises a control circuit 12 for controlling the operation of each circuit, a contrast adjustment circuit 14, and a brightness adjustment circuit 15.

Also, a horizontal driver 9, a vertical driver 8, a display panel
11 is collectively defined as a display unit 13. Hereinafter, the operation of the first block diagram will be described.

The video signal processing circuit 2 forms image signals such as R, G, and B primary color signals based on the video signal input to the terminal 1. The formed image signal is PCM with the required number of bits in the A / D converter 3.
(Pulse Code Modulation) signal and stored in the memory 4 for each bit.

In the control circuit 12, various control signals synchronized with the input video signal are formed and supplied to each circuit.

The vertical scanning pulse generation circuit 5 generates a vertical scanning pulse for the display panel 11 based on the control signal from the control circuit 12, and scans the display panel 11 via the vertical driver 8. The horizontal scanning pulse generation circuit 6 fetches an image signal for each bit of the memory 4 in synchronization with a control signal from the control circuit 12, and forms a writing pulse to display pixels arranged in the horizontal direction. This write pulse passes through the horizontal driver 9 and is synchronized with the vertical scanning in the display panel.
11 is applied.

The AC control circuit 7 controls the polarity of the output voltage of the horizontal driver 9 on the basis of the control signal from the control circuit 12 so that the voltage applied to each pixel of the display panel 11 becomes AC (the display constituting each pixel). When the element is a liquid crystal cell, AC driving is performed to prevent the liquid crystal from deteriorating.)

In the display unit 13, the horizontal driver 9 selects and outputs a predetermined voltage corresponding to each bit of the digital data obtained by the A / D conversion to the pixels in the row selected by the vertical driver 8, and outputs each voltage. The data is written into a pixel (for example, a liquid crystal cell) to perform a gradation display according to the value of the digital data.

In this embodiment, the contrast adjustment circuit 14 and the brightness adjustment circuit 15 are provided, and the voltage applied to the horizontal driver 9 is adjusted to a predetermined voltage in a normal state. Further, when it is necessary to finely adjust the contrast or reduce the black level specially, the video signal processing circuit 2 reduces the amplitude of the video signal input to the A / D converter 3 or lowers the DC level. Act on. Of course, there are other methods for equivalently changing the amplitude and the DC level of the video signal, but the method shown in FIG. 1 shows a typical example.

FIG. 2 shows a relationship between a scanning line and a scanning time in a field period for specifically explaining a field time-division scanning as an operation principle for performing multi-gradation display on the display panel 11 of FIG. It is a schematic diagram.

In FIG. 2, the vertical axis indicates the scanning line number, and the horizontal axis indicates the scanning time. A normal television signal is represented by a solid line L ₀ shown in FIG.
Are scanned along. That is, in the solid line L _0, the scanning of the scanning line number 1 is performed at the left end indicating the first one field (upper end in terms of the 1 field screen), or less, although at the right end (1 field screen indicating the end of one field (Lower end) indicates that scanning of the scanning line number n is performed.

In the solid line L ₂ contrast, scanning of the scanning line number 1 is performed at the center (in terms of the one-field screen top and center of the lower end) indicating the middle of one field, hereinafter, not scanning is sequentially performed, Compared to scanning by solid line L ₀ , just 1
This indicates that screen scanning is started and performed with a phase shifted by half from the top of the field screen. For even solid L _1, only the start phase of the picture scanning is different, the same is left.

For simplicity, an image signal to be displayed is represented by a PC of n = 3 bits.
A / D conversion is performed for M signals. That is, the image signal is A / D-converted with 3 bits, and LSB to MSB are respectively b ₀ ,
It is represented by b ₁ , b ₂ bits, and scanning is started in a form shifted in phase along the solid lines L ₀ , L ₁ , L ₂ corresponding to each bit of b ₀ , b ₁ , b ₂ , Scan in parts.

As can be seen from FIG. 2, in a normal television receiver, L ₀
In the image display according to the present embodiment, one field is divided into three parts and the field is divided by L ₀ , L ₁ , and L ₂ , whereas the field display is performed in one time. An image is displayed by scanning. In FIG. 2, the dotted line represents the scanning accompanying the image display in the previous field.

FIG. 3 is a circuit diagram showing a specific configuration example of the display unit 13, the contrast adjustment circuit 14, and the luminance adjustment circuit 15 in the reference example of FIG.

Each of the vertical driver 8 and the horizontal driver 9 includes a shift register 81, 91, a latch 82, 92, an analog multiplexer.
83,93, for example, "Hitachi LCD Driver LSI Data Book (5th Edition)" issued by Hitachi, Ltd.
A liquid crystal driver HD66107T described on pages 274 to 292 (issued in March 1990) may be used.

The display panel 11 includes gate buses G _a1 , G _a2,.
, D _r1 , D _r2 ,..., A pixel transistor 111 formed at the intersection thereof, a pixel electrode S _o1 , S _o2,. Such an electro-optical display element 112 includes a common electrode 113.

A PLL (Phase Locked Loop) 121 is a part of the control circuit 12, and includes a phase comparator 122 based on a horizontal synchronization signal supplied from a terminal 126, and a low-frequency filter (LPY; Low Pass Filtration).
er) 123, Voltage Controlled Oscillator (VCO)
cillator) 124, frequency divider 125, display panel 11
A dot clock corresponding to the number of horizontal pixels is formed.

The AC control circuit 7 generates a frequency divider 72 that divides the vertical synchronization signal input to the terminal 71 by two, and a clock that is synchronized with a dot clock formed by the PLL 121, for example, three times the horizontal synchronization frequency. It comprises a counter 72 to be input, a decode circuit 74, and an exclusive OR circuit 75.

The contrast adjustment circuit 14 and the brightness adjustment circuit 15 include an operational amplifier 141, 142, 151, 152, a current source 144, resistors 145, 146, 154,
155, variable resistors 143 and 153. 88 and 89 are voltage sources.

FIG. 4 shows an example of operation waveforms when the configuration example of FIG. 3 is driven in accordance with the field time-division scanning method shown in FIG. 2, and the operation will be described below.

Gate bus G _a1 for example, time 0 by the vertical driver 8 to, (1 + 1/3) H, (3 + 2/3) a pulse is applied to H (where, 1H denotes one horizontal scanning period), g ₀ respectively, g ₁ ,
g represented by ₂ symbols. Although the gate bus G _a2, G _a3 are the same G _a1 and waveform applied to g _0, g _1, g ₂ of pulses each 1H, 2H delayed G _a1.

When the gate pulses g ₁ , g ₂ , g ₃ are selected, the voltage source 88
The voltage V _8, at the time of non-selection is obtained the voltage V ₉ of the voltage source 89 is switched by an analog multiplexer 83.

The data bus D _r1, 3-bit data in accordance with the g _0, g _1, g ₂ of the pulse applied by the horizontal driver 9 to the gate bus _{G a1, G a2, G a3} , an image signal by A / D-converting b ₀ , b ₁ , b ₂
Is selected from the previously given four voltage levels V ₁ , V ₂ , V ₃ and V ₄ .

At this time the analog multiplexer 93, the level of the output M of the alternating control circuit 7, by the combination of the output D _i of the A / D conversion data b _0, b _1, b ₂ a latch 92 for sequentially outputting a signal corresponding to, Since the voltage level is selected as shown in FIG.
Is "1" level, V ₁ when b _i = 1, V ₃ when b ₁ = 0, M
There the "0" level, it is assumed to select a V ₄ when _{b i = V 2, b i} = 0 when 1.

In the waveform example of FIG. 4, the gate pulse g of the gate bus _Ga1
0 , g ₁ , g ₂ The voltage of the drain bus _Dr1 given in synchronization with
V ₁ (the field of M = 1) and the voltage V ₂ (the field of M = 0) are written to the pixel electrode _Sol, and are held until the next data is written.

Therefore, the pixel electrode S _o1, the amplitude voltage _{V s (= V 1 -V 2} )
Is applied. In addition, the pixel electrode S
_o2 likewise given in synchronization with the gate pulse g _0, g _1, g ₂ of the gate bus G _a2, the voltage V ₃ of the drain bus D _r2 (M =
1 field) and the voltage V ₄ (M = 0 field) are written to the pixel electrode _So2, and are held until the next data is written. Therefore, the amplitude voltage V _N is applied to the pixel electrode _So2.
(= V ₃ −V ₄ ) AC waveform is applied.

Thus, the effective voltage V _N depends on the content of the A / D conversion data.
So that the voltage of ~V _S is applied to each pixel electrode. It is clear that the display luminance at this time is expressed by the above-mentioned equation (1) when the response of the display element is fast, and is expressed by the above-mentioned equation (7) when the response is slow. Halftone display according to the converted data can be performed.

At this time, assuming that the luminance characteristic of the display element is approximated by f (V) = kV (10), the minimum luminance lmin is given by the above-mentioned equation (5) as follows: lmin = kV _N = k (V ₃ −V ₄ ) …… (11) On the other hand, it is given by the above-mentioned (6) = contrast ratio C _R is C _R = V _S / V _N from the equation _{(V 1 -V 2) / (} V 3 -V 4) ...... (12).

Here, assuming that the display element is driven by AC, the waveform given to the pixel electrodes S _o1 and S _o2 requires a voltage waveform that is symmetrical for each field with respect to the potential V _COM of the common electrode 113. Therefore, the following condition is satisfied.

V _COM = (V ₁ + V ₂ ) / 2 = (V ₃ + V ₄ ) / 2 (13) By substituting the above equation (13) into the above equations (11) and (12), the following equation is obtained.

lmin = 2k (V _COM −V ₄ )… (14) C _R = (V _COM −V ₂ ) / (V _COM −V ₄ ) = 1 + (V ₄ −V ₂ ) / (V _COM −V ₄ ) ... (15) Therefore, in the brightness adjustment circuit 15, through the differential amplifier 152 to the common electrode potential V _COM is applied to the terminal 156, acting a voltage V ₄ obtained by dividing the luminance adjusting variable resistor 153 as a buffer, It can be seen from the above equation (14) that the minimum luminance lmin can be adjusted by inputting the signal to the anilog multiplexer 93 in the horizontal driver 9.

In the contrast adjustment circuit 15, the constant current circuit 14
4 and a variable resistor voltage level shift circuit consisting of 143 by forming a set voltage lower by the voltage V ₂ with the power voltage V ₄ of the brightness adjustment circuit 14, a differential amplifier 14 which acts as a buffer
Through 2, by inputting the analog multiplexer 93 in the horizontal driver 9, the above equation (15), it can be seen that adjusting the contrast ratio C _R.

Other and voltages V ₁ to be input to the analog multiplexer 93
V ₃ is based on the common electrode potential V _COM , in order to satisfy the above-mentioned conditional expression (13) of the display element AC conversion.
The circuit for inverting the potential of the voltage V ₂ and V _4, the differential amplifier 141,
151 and resistors 145, 146, 154, 155 are used.

In FIG. 4, there is a period (1 / 3H to 1H, 1 (2/3) H to 2H) during which the M signal is inverted in the field.
This is because a period in which a video signal of the opposite polarity of the previous field (corresponding to the broken lines (L ₁ ) and (L ₂ ) in FIG. ₂ ) is added.

FIG. 6 shows the vertical scanning pulse generation circuit 5 in FIG.
FIG. 3 is a block diagram showing an example of the configuration of FIG.

In FIG. 6, a clock is input to the input terminal 53 from the control circuit 12 shown in FIG. 1, an address is formed by the counter 51, and an address is formed by a decoder circuit 52 composed of, for example, a read-only memory (ROM). Pulse at terminals 54 and 5
5 is input to the vertical driver 8.

The vertical driver 8 is composed of a shift register 81, a latch 82 and an analog multiplexer 83 as shown in FIG. 3, and obtains gate bus waveforms _Ga1 , _Ga2 ,... Shown in FIG.

FIG. 7 shows another reference example of the present invention. The same components as those shown in the configuration diagram of FIG. 3 are denoted by the same reference numerals.
The difference between the reference example of FIG. 3, the selected output voltage of the horizontal driver 9 the two values V ₁ and V _3, a point obtained by alternating a common electrode potential V _COM. 73 is an exclusive-OR inverter (Ex-NOR), 84,
Reference numerals 94 and 154 denote analog multiplexers for selectively outputting binary voltages. Hereinafter, the operation of the circuit shown in FIG. 7 will be described with reference to an example of operation waveforms of each part shown in FIG.

As can be seen from the operation waveform example of FIG. 4 already described, in the reference example of FIG.
The V ₁ and V _3, whereas have selected voltage V ₂ and V ₄ in the field of M = 0, in the reference example of FIG. 7, in the field of M = 0, the input data to the horizontal driver 9 D is inverted by an exclusive OR inverter 73 in advance, and the voltage V ₃
We have selected the V ₁ and.

Also, the output M of the alternating control circuit 7, and AC switch the common electrode potential V _COM voltage V ₇ and the voltage V _S. The waveforms of the gate buses G _a1 , G _a2 , G _a3 are the same as those in FIG.

The pixel electrode _So1 is _supplied with V ₁ in the field of M = 1 and V _{3 in} the field of M = 0, and the common electrode 113 is supplied with V ₈ in the field of M = 1 and V _{7 in} the field of M = 0. Applied.

At this time, the voltage felt by the display display 112 sandwiched between the pixel electrode _So1 and the common electrode 113 is V _S1 = V ₁ −V ₈ (16) in the field of M = 0 in the field of M = 1. V _S2 = V ₃ −V ₇ (17), and the amplitude voltage V applied to the display element 112 after all
_S is V _S = V _S1 −V _S2 = (V ₁ −V ₃ ) + (V ₇ −V ₈ ) (18)

Similarly, the pixel electrode _{S o2, V N1 = V 3} -V 8 ...... (19) V N2 = V 1 -V 7 ...... (20) V N = V N1 -V N2 = (V 3 -V 1) + (V ₇ −V ₈ )... (21)

Thus, the effective voltage V _N depends on the content of the A / D conversion data.
Voltage ~V _S is, by being applied to the display elements 112, as in the reference example of FIG. 3, it is possible halftone display.

Here, the condition for AC driving is V _S1 + V _S2 = 0, so that V ₁ + V ₃ = V ₇ + V ₈ (22) is obtained from the above equations (16) and (17).

Vcen≡ (V ₁ + V ₃ ) / 2 = (V ₇ + V ₈ ) / 2 (22 A) From the above equations (18) and (21), V _S = 2 (2Vcen−V ₃ −V ₈₎ ) (23) V _N = 2 (V ₃ −V ₈ ) (24) When the luminance characteristics of the display element 112 are approximated as in the aforementioned equation (10), the average luminance _BR and the contrast ratio _CR are Above (2
3) and (24) are calculated as follows.

B _R ≡ (1/2) ｛f (V _N ) + f (V _S )｝ = 2k (Vcen−V ₈ )… (25) C _R ≡f (V _S ) / f (V _N ) = (2Vcen −V ₃ −V ₈ ) / (V ₃ −V ₈ ) = 1 + 2 (Vcen−V ₃ ) / (V ₃ −V ₈ ) (26) Therefore, by adjusting the voltage of V ₈ , the average luminance is obtained. B _R
Can be adjusted by adjusting the voltage of V _3, it can be seen that adjusting the contrast ratio C _R.

The brightness adjustment circuit 15 in FIG. 7 forms the binary voltages V ₇ and V ₈ satisfying the above equation (22), and is controlled by the analog multiplexer 157 controlled by the output M of the AC control circuit 7. by switching the voltage V ₇ and V ₈ binary, giving the common electrode 113.

Voltage V ₈ may divide the reference potential Vcen applied to the terminal 158 of the variable resistor 153, through a differential amplifier which acts as a buffer, and applied to an analog multiplexer 157. Voltage V ₇ is the inverted amplifier constituted by the differential amplifier 151, resistors 154 and 155, inverts the voltage V ₈ with respect to the reference potential VCEN, and applied to an analog multiplexer 157,
Obviously, the above expression (22) is satisfied. Thus by adjusting the voltage V ₇ by adjusting the variable resistor 153, as shown in the above (25), it can be seen that adjusting the average luminance B _R.

The contrast adjustment circuit 14 in FIG. 7 also includes differential amplifiers 141 and 142, a variable resistor 143,
The output voltages V ₁ and V _{3 which} are constituted by the resistors 145 and 146 and are adjusted by the variable resistor 143 are obtained. That is, (2)
6) it can be seen that adjusting the contrast C _R as shown by the formula.

The multi-tone display device described above is, for example, 3b
By using the A / D converter of it to sequentially select each pixel three times in one field, 8 (= 2 ³ ) gray scale display is realized. To increase the number of gradations, it is necessary to increase the number of times of selecting each pixel in one field. For example, in terms of the operation speed of the transistor formed in each pixel,
Sometimes you can't increase it as you want. Accordingly, FIG. 9 shows an example of an accessory circuit necessary for realizing a display with more gradations without increasing the number of selections of pixels in one field, as a reference example.

The portion of the broken line frame 31 in FIG. 9 is an attached thinning circuit, which is used by inserting it into the A / D converter 3 and the memory 4 of the reference example shown in FIG.

In FIG. 9, a video signal is applied to terminal 31 and A /
The D converter 3 outputs, for example, a 4-bit PCM signal b ₀ ^* , b ₁ ^* ,
Converted to b ₂ ^* , b ₃ ^* . The terminal 73 receives, for example, an output signal M of the AC conversion control circuit 7 shown in FIG. 3, which is inverted for each field, and uses the output signal M as a thinning signal MB.

32, 33, 34 and 35 are constituted by, for example, 1-bit adders. Each carry signal is inputted to the next stage, and the output of the adders 33, 34 and 35 is supplied to the input signal b of the memory 4. _0, b _1, is used as b _2. The OR circuit 36 is used as an overflow countermeasure.
The logical sum of the carry signal and the addition output is formed.

With this connection, when the least significant bit b ₀ ^* of the A / D conversion output is 0, b ₀ = b ₁ ^* , b ₁ = b ₂ ^* , b ₂ = b ₃ ^*
Next, displays a ^{_{b 1 * +2 (b 2 *}} + 2b 3 *) gradations in eight gradations. That is, the least significant bit of the A / D conversion output is truncated and displayed using the upper 3 bits.

Next, when the least significant bit b ₀ ^* of the A / D conversion output is 1,
M b ₀ = b ₁ ^* In = 0 ^{_{field, b 1 = b 2 *,}} b 2 = b 3 * , and the second b ₁ of 8 gradations ^{_{* +2 (b 2 * + 2b}} 3 *) tone (A / D
The upper 3 bits of the converted output are displayed. In the field of M = 1, the attached thinning circuit 31 adds 1
^{_{b 1 * +2 (b 2 *}} + 2b 3 *) +1 gradation (A / D conversion the 3 bits obtained by rounding the least significant bits of the output) for displaying, the b as the average gray level of the two fields ₁ ^* + 2
^{_{(B 2 * + 2b 3 *}} ) +0.5 will display gradation.

_{^{However, b 0 * = b 1 *}} = b 2 * = b 3 * = 1 case of, M = 1
When 1 is added in the field of (1), a carry occurs, so that gradation display with 1 cannot be performed. Therefore, the 7th gradation display is used by the OR circuit 36.

That, b ₁ ^* = at ^{_{b 2 * = b 3 * =}} 1, regardless of the value of b ₀ ^*, 8 in the tone in every field,
Display is performed at the seventh gradation. As a result, in 0.5 gradation steps,
15 gradations from 0 to 7 can be displayed. in this way,
The number of display gray scales can be almost doubled without increasing the number of sequential selection circuits for each number of pictures in one field.

At this time, when b ₀ ^* = 1, the field of M = 0 and M
= 1, the gray scale to be displayed is shifted by one. Therefore, when a negative electrode is provided in the field of M = 0 and a positive electrode is provided in the field of M = 1, and the display element is AC-driven, Will be applied to the DC component.

However, since the difference in voltage between the fields is one gradation of 8 gradations _{{(V S / 2) -} (V N -2)} / 7 a is, DC component V applied to the display element _DC is half that.

V _DC = (1/28) · (V _S −V _N ) (27) For example, if V _S = 13 V _PP and V _N = 4 V _PP , V _DC = 0.3 V. Of course, in the display of b ₀ ^* = 0, it is assumed that V _DC = 0 V.

Here a common electrode potential V _COM to DC, for example 0.15V if raised in advance, the maximum DC voltage can be a within ± 0.15, substantially acceptable level.

In the above example, the data to be handled after the memory 4 is 3 bits. However, when the number of bits is increased to increase the number of gradations, the DC component of the above equation (27) is further reduced. Is clear.

In the above description, the signal given to the terminal 73 is
This is a field-by-field inversion signal, which provides a signal obtained by dividing the dot clock by 2 or a signal obtained by dividing the horizontal synchronization signal by 2, and controls the truncation and rounding of the least significant bit between adjacent pixels. Thereby, the number of gray scales that can be displayed as the average luminance can be increased.

FIG. 10 shows a main part of another reference example of the present invention. Like the thinning circuit in FIG. 9, multi-gradation display by thinning is intended. A feature is that a look-up table (LUT) 36 constituted by, for example, a read-only memory (ROM) is used instead of the thinning circuit 31.

In FIG. 10, the output signal b of the 8-bit A / D converter 3
₀ ^* ~b ₇ ^* with, is input from the terminal 74, 75, for example,
The thinning signal that switches for each field and for each pixel is
6-bit P
Supplied to the memory 4 as C signal b ₀ ~b _5.

As described above, by using the LUT 36, when the voltage-luminance characteristics of the display pixel are different from those assumed by the input video signal, there is an advantage that the function of so-called gamma correction for correcting the signal is also provided. .

9 and 10 show that the A / D converter of the number of bits corresponding to the number of gray scales to be displayed is required irrespective of the number of bits of the PCM signal handled by the memory. Become. In general, if the number of bits handled by the A / D converter increases, the price, power, etc. increase, so it is desirable to use an A / D converter with a small number of bits.

In order to meet this demand, a circuit that realizes multi-gradation display by thinning-out display using an A / D converter having the same number of bits as the number of PCM signals handled by the memory is an embodiment of the present invention. That is.

Based on the above, the main parts of the embodiment of the present invention are shown in FIGS. 11 and 12.

In the main part of the embodiment shown in FIG. 11, a portion surrounded by a broken line 21 is an attached thinning circuit. For example, given to terminal 73,
The analog multiplexer 24 is controlled by an MB signal such as an inversion signal for each field, and a voltage of half (1/2 LSB) of the minimum gradation voltage of the A / D converter 3 output from the voltage source 25 and 0 V are switched. The signal is supplied to the adder 23, added to the video signal input to the terminal 22, and supplied to the A / D converter 3. This is just
This means that the attached thinning circuit 31 in the main part of the reference example of FIG. 9 is realized in an analog manner. The operation after the memory 4 is the same as in the case of FIG.

In the main part of the embodiment of FIG. 12, for example, a random number voltage source 26 having a maximum amplitude substantially equal to the minimum gradation voltage (1 LSB) of the A / D converter 3 is used instead of the analog multiplexer 24 of FIG. Used.

This random number voltage source 26 has a voltage amplitude of a random number, and uses the same frequency of occurrence of each voltage over the voltage range of 1 LSB, thereby using a thinning PCM without using a thinning control signal. A signal can be obtained. Examples of the random voltage generator 26 include thermal noise of a resistor and avalanche breakdown noise of a transistor.

There is an advantage that the circuit configuration is simplified by performing the analog processing.

Another method of field time division scanning for use in another embodiment of the present invention is shown in FIG.

It differs from that shown in FIG. 2, corresponding to the most significant bit b ₂ of the A / D converted data, the signal holding period of each pixel 2
That is, the selection is sequentially performed a total of four times, including one time which is increased by dividing each pixel into two in one field. One of the solid line L ₂ shown in FIG. 2, in the Fig. 13 L
What is indicated by two lines ₂₁ and L ₂₂ represents this. FIG. 14 shows an example of operation waveforms of each part when this scanning method is applied to the reference example of FIG. 3 and driven.

The main difference between the operation waveform examples of FIG. 4 and FIG.
In addition, since each pixel is sequentially selected four times in one field, the time required for selecting one row is (1/3) H →
(1/4) H. _Second , the holding period corresponding to the most significant bit b ₂ is divided into two, and a ₂₁ , a ₂₂ (a ₂₁ = a ₂₂ ≒ a ₂ /
2) and the order, the field maximum retention period is halved, the third, in the period of a ₂₁ and a _22, a point that reverses the polarity of the video signal.

The first point is that the time required for selecting one row is shortened and the scanning speed required for the display panel is increased. However, it is considered that the problem can be solved by using the above-described thinning scanning together.

The second point is that, for example, when an active matrix liquid crystal panel using a display element composed of a transistor and a liquid crystal cell for each pixel is considered as a display panel, it is necessary to effectively hold the written voltage during periods other than the selection period. It is desirable to add a storage capacitor in parallel with the liquid crystal cell capacity, but halving the longest storage period means that the storage capacity to be added can be reduced. This leads to a reduction in the area for forming the storage capacitor, and thus an improvement in the aperture ratio leads to an improvement in luminance.

The third point is that the DC component that is transiently applied can be suppressed even when the display contents of the first field and the second field are greatly changed in displaying a moving image or the like. For example, if the maximum voltage (V _S / 2) is applied in the first field and the minimum voltage (V _N / 2) is applied in the second field,
In the reference example of FIG. 4, the DC component is (V _S −V _S ) / 2,
In the reference example of FIG. 14, at least the most significant bit of the A / D conversion output can be AC-converted in the field, so that there is an advantage that the DC component can be almost halved.

FIG. 15 shows the relationship between the AC drive waveform of each pixel and the information of each bit of the digital PCM signal in the present invention.

In FIG. 15, the horizontal axis represents time, and the vertical axis represents polarity. (A), (b), and (c) are second examples in which the configuration example of the reference example of FIG. 3 is described using a 3-bit PCM signal as an example.
These are examples of 8 bits, 7 bits, and 6 bits when driven by the driving methods shown in FIGS.

Figure 15 (d) are, as in the driving method shown in FIG. 13 and FIG. 14, and 2 min period corresponding to the most significant bit b ₅ in (c), an example in which the polarity inversion in one field in, shows a two-minute period with b ₅₁ and b _52. (E) is a one b ₅₂ most significant bits and 2 minutes, by previously inverting the polarity in the field a period corresponding to the next order bit b _4, is a method to further reduce the DC component in the video .

In this way, the method of polarity reversal in the field,
Various arrangements and the like of each bit in the field can be considered.

Next, specifically, as an embodiment of the present invention, as a video signal, for example, when each of the 262.5 NTSC system and 312.5 PAL / SECAM system TV signals is displayed in one field, it corresponds to each bit of the PCM signal. An example of the retention period
These are shown in FIGS. 16 and 17.

In addition, (a), (b), (c),
(D) and (e) show the driving waveforms (a) and (d) in FIG.
(B), (c), (d) and (e) are taken into account, and b ₅₁ and b ₅₂ have the same value as bit b _{5 of the} PCM signal, but correspond to b ₅ Since the period is divided into two, b ₅₁ ,
b ₅₂ is given a different code.

16 and 17, the first feature is that almost all of one field period is given to the holding period and the selection time.

For example, in FIG. 16 (a), when the total value of the holding period of each bit, 261.5H, and the period of selecting one row selection time (1/8) H eight times are added, it becomes 262.5H, which is equal to one field period. . As described above, by using almost all of one field period, there is an advantage that the effective voltage of the display cell can be increased.

The second feature is that the holding period a _i for i bits is twice or more the holding period a _i-1 for the lower (i−1) bits. Therefore, assuming that the most significant bit is n bits, a _n > 2 ⁿ · a _o (28) holds.

The reason is as follows. That is, when trying to satisfy a _i = 2a _i−1 , the following problem occurs. For example, the 16th
In the diagram (c), b ₀ = 4, b ₁ = 8, b ₂ = 16, b ₃ = 32, b ₄ = 6
The setting is 4, b ₅ = 128.
53H is fine. In order not to apply the voltage to the difference of 9.5H from 262.5H in one field, the number of times of selection of each pixel in one field must be increased, which causes a problem in the scanning speed of the display unit.

Further, as described in the first feature, it is necessary to use all the fields from the viewpoint of increasing the effective voltage. For this reason, the remaining 9.5H is allocated to each bit. However, in order to minimize the error as much as possible and to secure the linearity with respect to the minute voltage, a _i ip _{i ai-1} (where ,
(p _i ≧ 2) and p _i are almost equal.

A third feature is that a 0.5H fraction is allocated to the most significant bit, and is used by increasing or decreasing 0.5H for each field. For example retention period of the most significant bit b ₅ of FIG. 16 (c) is a 133.5H, which the 133H for each field 13
Indicates that 4H is switched and used. As described above, this is a fraction process for using the entire period of one field.

Although the description has been made mainly on the time-division scanning in the field unit, it is apparent that the same time-division scanning can be performed in the unit of one frame for two fields.

〔The invention's effect〕

According to the present invention, using a horizontal scanning circuit of a type that selects and outputs a predetermined voltage which is relatively small, has a relatively small circuit scale, has small variation in output voltage, and can easily obtain a high withstand voltage at high speed. There is an effect that it is possible to realize a low-cost, high display effective voltage and high-definition multi-gradation display device.

For example, a ferroelectric liquid crystal having a relatively high response speed and a high driving voltage, and a PDLC (Polymer Dispersion Liquid C)
A multi-grayscale display device using (rystal) or the like as a display element can be easily realized.

In addition, the combined use with the thinning-out display by the analog processing also has an effect that a display with more gradations can be performed without increasing the number of times of field time-division scanning.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a multi-gradation display device as a reference example of the present invention, FIG. 2 is an explanatory diagram showing the relationship between scanning lines and scanning time for showing field time-division scanning of a display panel, and FIG. FIG. 4 is a circuit configuration diagram of a main part of a multi-gradation display device as a reference example of the present invention. FIG. 4 is a timing chart showing operation waveform examples of respective parts when the reference example of FIG. 3 is driven by the scanning method shown in FIG. FIG. 5 is an explanatory view of a truth table showing a selected output state of an analog multiplexer in a horizontal driver, FIG. 6 is a block diagram showing an example of a vertical scanning pulse generation circuit, and FIG. 7 is another reference of the present invention. FIG. 8 is a circuit configuration diagram of a main part of a multi-gradation display device as an example, FIG. 8 is a timing chart showing an operation waveform example of each part of the reference example of FIG. 7, and FIGS. 9 and 10 are digital thinning circuits, respectively. Block diagram showing an example of FIG. 11, FIG. 12 and FIG. FIG. 13 is a block diagram showing an analog thinning circuit according to an embodiment of the present invention. FIG. 13 is an explanatory diagram showing a relationship between a scanning line and a scanning time for showing field time-division scanning when dividing the most significant bit into two. 13 is a timing chart showing operation waveforms of respective parts when the reference example of FIG. 3 is driven by the scanning method shown in FIG. 13, and FIG. 15 is a diagram showing the relationship between the driving polarity of each pixel and the time division within a field in various scanning methods. FIG. 16 is a timing chart showing the relationship, FIG. 16 and FIG. 17 are explanatory diagrams showing an example of a holding period corresponding to each bit in the NTSC and PAL / SECAM television signal display according to the present invention, and FIG. FIG. 4 is a schematic diagram illustrating a conventional example of a configuration of a matrix liquid crystal display device. DESCRIPTION OF SYMBOLS 1 ... Video signal input terminal 2 ... Video signal processing circuit, 3
... A / D converter, 4 memory, 5 vertical scan pulse generation circuit, 6 horizontal scan pulse generation circuit, 7 AC control circuit, 8 vertical driver, 9 horizontal driver , 11 display panel, 12 control circuit, 14 contrast adjustment circuit, 15 brightness adjustment circuit, 121 PLL circuit, 141, 142, 151, 152 differential amplifier, 81, 91 shift register, 82, 92: Latch, 83, 84, 93, 94, 157: Analog multiplexer, Dr: Data bus, Ga: Gate bus, 111: Pixel transistor, 112: Display element, V
_COM: Common electrode, 32, 33, 34, 35 Adder, 36 Look-up table

Claims (2)

(57) [Claims] 1. A multi-gradation image display device for displaying a video signal represented by digital data having n bits in multiple gradations with the number of gradations determined by the bit number n, wherein the image signal is written in a certain selection period. A display panel configured by arranging a display element that maintains a display state by controlling the electro-optical characteristics by substantially holding the signal even during periods other than the selection period as pixels as a pixel, and a matrix configuration forming the display panel A vertical drive circuit for sequentially selecting and scanning the display elements for each row; and a plurality of voltages previously assigned to the display elements of the row selected by the vertical drive circuit in accordance with a value of a video signal to be displayed. A horizontal drive circuit for writing the selected voltage; and a horizontal and vertical drive circuit for synchronizing with the video signal to be displayed, during one field period. In addition, by sequentially selecting and scanning each display pixel at least n times, a multi-gradation display determined by the number of bits n is realized, and the period during which a signal corresponding to the most significant bit is held in each pixel is the least significant bit. And ^(c) a control circuit for setting the period to be longer than 2 ^(n-1) times of a period for holding a signal corresponding to ⁽ b ^{), wherein} n is a natural number. 2. A multi-gradation image display device for converting an input video signal into digital data of n bits by an A / D converter and displaying the inputted multi-gradation image, the data being written in a certain selection period. A display panel configured by arranging a display element that maintains a display state by controlling the electro-optical characteristics by substantially holding the signal even during periods other than the selection period as pixels as a pixel, and a matrix configuration forming the display panel A vertical drive circuit for sequentially selecting and scanning the display elements for each row; and a plurality of voltages previously assigned to the display elements of the row selected by the vertical drive circuit in accordance with a value of a video signal to be displayed. A horizontal drive circuit for writing the selected voltage, and a voltage equal to or lower than the least significant bit of the A / D converter,
Generating means for generating an analog signal having a voltage equal to or more than half the voltage, an adder for adding the analog signal and the input video signal to an A / D converter, and the horizontal and vertical drive circuits, At least A /
The number of times n equal to the number n of bits output from the D converter,
A control circuit for sequentially performing selective scanning of each display pixel during one field period in synchronization with the input video signal, thereby realizing a multi-gradation display determined by the bit number n. (Where n is a natural number).