JPH04186282A - Multi-contrast image display device - Google Patents

Abstract

PURPOSE:To facilitate control of a wide range of contrast/brightness, and improve reliability using a digital horizontal scanning circuit by employing a pulse width modulation method, and changing voltage given to common electrodes such as data drivers, etc. CONSTITUTION:An image signal processing circuit 2 forms an original colored image signal from an image signal from a terminal 1, converts the signal into a PCM signal by an A/D converter 3, and stores the signal in a memory 4. A vertical scanning pulse generating circuit 5 and a horizontal scanning pulse generating circuit 6 takes in a pulse for vertically scanning a display panel 11 through a vertical driver 8 and a horizontal driver 9, and an image signal of a memory 4 by a control signal from a control circuit 12, and generate a writing pulse to display picture elements arranged in the horizontal direction. These pulses are applied in proper timing. In a display unit 13, the driver 9 displays contrasts which correspond to the values of digital data to the picture elements selected by the driver 8.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an active device that maintains a signal voltage written during a selection period for a period other than the selection period to control its electro-optical characteristics and maintain a display state. It relates to an image display device in which display elements such as matrix type liquid crystals are configured as pixels, and more specifically, it displays multi-gradation images by controlling the signal voltage holding period according to the level of the video signal to be displayed. The present invention relates to a multi-gradation image display device.

[Prior Art] FIG. 18 is a schematic diagram showing a conventional example of the configuration of an active matrix liquid crystal display device.

In the figure, DR is a data driver circuit, SC is a scanning circuit, CB is a gate bus, DB' is a data bus (drain bus), Tr is a transistor (FET), Cr is a liquid crystal cell, and CE is a common electrode.

In FIG. 18, an active matrix liquid crystal panel is constructed by arranging pixels each consisting of an active circuit element such as a transistor Tr and a liquid crystal cell Cr at each intersection of a gate bus GB and a data bus DB. A transistor Tr is selected by a gate bus CB, and a liquid crystal cell C is selected from a data bus (drain bus) DB via the transistor Tr.
Write a voltage signal to r. The liquid crystal cell Cr functions as a capacitor that stores the written voltage, and at the same time controls the electro-optical characteristics using the held voltage to perform display. Multi-gradation display is performed by varying the level of the voltage signal written to the liquid crystal cell Cr.

Such an active matrix liquid crystal display device is, for example,
As described on pages 1) 3 to 1) 5 of "Flat Panel Display 90" (published by Nikkei BP, January 1, 1990), the display brightness is controlled by multiple data buses of an active matrix liquid crystal panel. Halftone display is performed by applying appropriate analog voltages.

-4. Using a binary display panel like a plastic display, which emits light when a sustain pulse sufficient to maintain light emission is applied, and does not emit light when no sustain pulse is applied, during F-yield (n+1 ) By selecting each pixel and controlling the number of sustain pulses applied, pulse width modulation allows
An example of an image display device that realizes 2″ gradation display is published in Japanese Patent Application Laid-Open No.
-163794 and Japanese Unexamined Patent Application Publication No. 163794, 63795
It is stated in the No.

[Problems to be Solved by the Invention] In the first prior art described above, in FIG. A circuit that samples the analog video signal for one scanning line sent from the main frame, holds it, and outputs the held analog sampling signal in synchronization with the timing of the gate hash (1, B scanning signal). , it is necessary to have the number of data buses DB.

If the output voltages of the large number of required analog sampling circuits vary in this way, the brightness will vary in halftone display, causing display unevenness, so the output voltage accuracy of the sampling circuits is required. Analog horizontal scanning circuits (data driver circuits) that satisfy such requirements have a large circuit scale, which makes it difficult to reduce the size, price, and power consumption.

Furthermore, for example, Niss I Day, '90. Digest (1990) pp. 220-223 (SI
D'90 DIGEST (1990) PP220-2
23) NCAP (Nemati
c Curvilinear Aligned
Phase) Even if you try to drive a display element with a high drive voltage of several tens of centimeters, such as a liquid crystal, expanding the dynamic range (that is, adopting a process with a large maximum rated voltage) generally leads to a decrease in analog sampling speed. , there is a problem that the video signal cannot be sampled with good resolution. In other words, this hinders the improvement of the display panel's resolution.

In the second conventional technique, even when displaying halftones, the voltage output by the horizontal scanning circuit is binary, and the signals handled are digital data. Therefore, there are advantages in that it is easy to obtain a horizontal scanning circuit with a small circuit scale, little output voltage variation, and high speed and high breakdown voltage.

However, display devices such as active matrix type liquid crystals do not have a signal corresponding to the sustaining pulse of a plasma display, so they cannot display halftones by pulse number modulation. It is also not possible to perform contrast/brightness adjustment over a wide range beyond the adjustment range limited by the input dynamic range of the D converter. )Also, since the subject is a plasma display, there is no mention of AC drive technology, which is commonly employed as an effective way to improve the reliability of liquid crystal cells.

Furthermore, in the second conventional technology, when trying to increase the number of display gradations, the number of times each row is selected within one field increases, which reduces the time required to select one row. In some cases, it became impossible to scan the LCD panel.

An object of the present invention is to solve the above-mentioned problems of the prior art, use a digital horizontal scanning circuit that has a small circuit scale (and can easily be made high withstand voltage), easily adjusts contrast/brightness over a wide range, and has high reliability. An object of the present invention is to provide a multi-gradation image display device using an active matrix type liquid crystal panel with high brightness.

[Means to solve the problem]

To achieve the above object, the present invention uses a digital data driver to maintain a period for holding the voltage written in the display cell of each pixel during the selection period, instead of modulating the number of sustain pulses, in order to display halftones. In addition to adopting a pulse width modulation method, the voltage applied to the data driver and the common electrode of the display cell is varied to achieve a wide range of contrast/brightness adjustment.

In addition, in order to obtain a multi-gradation display device with high reliability, the period during which the display cell is driven by the most significant bit of the digital data to be displayed is roughly divided in half, the maximum voltage holding period is halved, and the liquid crystal cell is At the same time, by driving the liquid crystal cell with opposite polarity during the divided periods, the display element (liquid crystal cell) can be driven more completely with alternating current. did.

Furthermore, in order to make it possible to display many gradations while reducing the number of times each row is selected within one field of the video signal to be displayed, thinning driving is also used for each field and each pixel.

[Effect]

For example, an analog video signal to be displayed can be converted to an 8-bit A/D
When performing pulse width modulation with the 8-bit output obtained by digitizing it with a converter, the lowest bin of the A/D converter output) (LSB).

For example, the signal holding period of ao is assigned to the most significant bit (b+), and the signal holding period of a is assigned to the next most significant bit (b+), and in the same way, the most significant bin) (MSB
, which is referred to as b7) is assigned the signal holding period of a7.

Then, the output voltages V, , Vs of the horizontal scanning circuit are assigned according to the state of 0.1 of each bit of the output data b0 to b7 of the A/D converter.

At this time, assuming that the response time of the display element is sufficiently shorter than the signal holding period, the luminance l of the display element is given by the following equation.

However, f (VH), f (vs) C, and the deviation voltage V)l.

(2) indicates the brightness when applied to the display element, and A is.

The signal holding period a is 8, U2..., ao...
If (3) is set, brightness control by pulse width modulation becomes possible in combination with A/D converter output b, and multi-gradation display can be realized.

From the above equation (1), the maximum brightness 1 max and the minimum brightness ff
1m1n is calculated as follows.

1 ff1ax = f (V s)
--(4) l wain = f (V N)
--(5) Let the contrast ratio be CR, and set this as i! tax/j! When defined as ++in, it is given by the following formula.

CR Mi 1max / l + min yo f (Vs) / f (VN) ・Old... (6) In this way, the output voltage V of the horizontal scanning circuit,
V.

By adjusting these, it is possible to adjust the contrast OR, minimum brightness, and gain, respectively.

Further, assuming that the response time of the display element is longer than the signal holding period and that the luminance l of the display element depends on the average applied voltage, the luminance 2 of the display element is given by the following equation.

......(7) From the above equation (7), the maximum brightness 42 s a x + minimum brightness 15 hin is calculated, as in the case of calculating from the above equation (1), the above (4), (5 ) holds true. Therefore, even if the response time of the display element is long, the contrast and minimum brightness can be adjusted by adjusting the output voltages (5) and (8) of the horizontal scanning circuit.

Furthermore, according to the second means of the present invention, by dividing the holding period a7 assigned to the most significant bit b7 into two and selectively driving it twice, the longest signal holding period is halved, and a
It will be 7/2. As a result, even if signal leakage occurs in each display element as a capacitor, the maximum period to be held can be halved, so signal attenuation due to leakage is halved or less, improving reliability of gradation display.

Furthermore, when using a liquid crystal element that requires AC drive to ensure reliability as a display element, each display element is usually driven with a signal whose polarity is reversed for each field to achieve AC drive with a two-field period. There is. However, if the signal changes between fields, such as when displaying a moving image, complete alternating current cannot be achieved. Under these circumstances, when driving display elements with the same polarity within a field, all A/D conversion data b is "1".
When the voltage changes from "0" to "0", the maximum DC component VDC expressed by the following equation is applied.

Voc= (first field applied voltage) - (second field applied voltage) V, -V, ...... (8
) (Here, the relationship in equation (2) above is used.) On the other hand, if we divide the retention period a7 assigned to the most significant bit b7 into two and give signals of opposite polarity to each half, we get Regarding the most significant bit b7, there is no need to consider the DC component even if the signal changes between fields. At this time, the maximum DC component VOC is expressed by the following equation.

Knee (Vs Vs) ・・・・・・(9
) (Here, from formulas (2) and (3) above, a7 yuzu.

The relationship of 8° above □ was used. ) In this way, by dividing the holding period a7 assigned to the most significant bit b7 into two and giving signals of opposite polarity to each half, the maximum DC component VDc when the inter-field signal changes can be halved. Reliability can be improved.

Further, according to the thinning driving means as the third means according to the present invention, for example, the first field displays the jth gradation, the second field displays the (j+1)th gradation, and the second field displays the jth gradation. By repeating this on a field-by-field basis, it is possible to display an intermediate gradation between the j-th and (j+1)-th average brightness. Furthermore, even if adjacent pixels display the j-th and N+1)th gradations, respectively, it is possible to similarly display an intermediate gradation as the average luminance.

In this way, it is possible to display more gradations without increasing the number of repeated selections in the ■ field.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment is an example in which the present invention is applied to a multi-gradation display device that uses pulse width modulation in field time-division scanning as a typical example.

In FIG. 1, the multi-gradation display device includes a video signal input terminal 1, a video signal processing circuit 2, an A/D converter 3, a memory 4,
Vertical scanning pulse generation circuit 5, horizontal scanning pulse generation circuit 6
, AC control circuit 7, vertical driver 8, horizontal driver 9
, an active matrix display panel 1), a control circuit 12 for separating a synchronization signal from an input video signal and controlling the operation of each circuit based on the synchronization signal, a contrast adjustment circuit 14, and a brightness adjustment circuit 15. Ru.

Also, horizontal driver 9, vertical driver 8, display panel 1
) are collectively defined as the display section 13. The operation of the first block diagram will be explained below.

The video signal processing circuit 2 forms image signals such as R, G, and B primary color signals based on the video signal input to the terminal 1. The formed image signal is converted into PCM (Pulse Code Module) of the required number of bits by the A/D converter 3.
lation ) signal and stored in the memory 4 bit by bit.

The control circuit 12 forms various control signals synchronized with the input video signal and supplies them to each circuit.

The vertical scanning pulse generation circuit 5 generates a vertical scanning pulse for the display panel 1) based on the control signal from the control circuit 12, and generates a pulse for vertical scanning of the display panel 1) via the vertical driver 8.
). The horizontal scanning pulse generation circuit 6 takes in the image signal for each bit of the memory 4 in synchronization with the control signal from the control circuit 12, and forms write pulses to the display pixels arranged in the horizontal direction. This write pulse is applied to the display panel 1) via the horizontal driver 9 in synchronization with vertical scanning.

The AC conversion control circuit 7 controls the polarity of the output voltage of the horizontal driver 9 based on the control signal from the control circuit 12 so that the voltage applied to each pixel of the display panel 1) becomes AC. When the display element is a liquid crystal cell, alternating current driving is performed to prevent the liquid crystal from deteriorating).

In the display unit 13, the horizontal driver 9 selects and outputs a predetermined voltage corresponding to each bit of digital data obtained by A/D conversion to the pixels in the row selected by the vertical driver 8. It is written to pixels (for example, liquid crystal cells) to display gradation according to the value of digital data.

In this embodiment of the present invention, a contrast adjustment circuit 14 and a brightness adjustment circuit 15 are provided to adjust the voltage applied to the horizontal driver 9 to a predetermined voltage in a normal state. Furthermore, when it is necessary to finely adjust the contrast or to specifically lower the black level, the video signal processing circuit 2 reduces the amplitude of the video signal input to the A/D converter 3 or lowers the DC level. It acts on Of course, there are other methods of equivalently changing the amplitude and DC level of the video signal, but the method shown in FIG. 1 is a typical example.

FIG. 2 shows the relationship between scanning lines and scanning times in a field period to specifically explain field time-division scanning as an operating principle for performing multi-gradation display on the display panel 1) in FIG. 1. FIG.

In FIG. 2, the vertical axis indicates the scanning line number, and the horizontal axis indicates the scanning time. A normal TV signal is the solid line L0 shown in Figure 2.
scanned along. That is, in the solid line L0, scanning line number 1 is scanned at the left end (in terms of a 1-field screen) that indicates the beginning of one field (in terms of a 1-field screen, the top edge), and thereafter, at the right end (in terms of a 1-field screen) that indicates the end of 1 field. Indicates that scanning of scanning line number n is performed at the lower end).

On the other hand, in the solid line L2, scanning with scanning line number 1 is performed at the center indicating the middle of one field (in terms of a one-field screen, the center between the top and bottom edges), and subsequent scanning is performed in order, so the solid line This shows that screen scanning is started and performed with a phase shift of half from the top of one field screen at a time, compared to scanning by L0. Solid line. Also, the only difference is the start phase of screen scanning,
The rest is the same.

For simplicity, the image signal to be displayed is
It is assumed that A/D conversion is performed to an M signal. That is, the image signal is A/D converted using 3 bits, and the LSB to MSB are expressed as 2 bits, , b, , and each bo, t.
it, 1) Each solid line L corresponds to each bit of z.
Scanning is started in a phase-shifted manner along Lz, Ll, and Lz, and the scanning is performed in a time-division manner.

As can be seen from Figure 2, in a normal television receiver, Lo
In contrast, in the image display according to the present invention, one field is temporally divided into three, and the LO.

Image display is performed by field time division scanning scanned by L, , L2. In FIG. 2, the dotted line represents scanning associated with image display in the previous field.

FIG. 3 is a circuit diagram showing a specific configuration example of the display section 13, the contrast adjustment circuit 14, and the brightness adjustment circuit 15 in the embodiment of FIG. 1.

The vertical driver 8 and the horizontal driver 9 are both composed of shift registers 81 and 91, latches 82 and 92, and analog multiplexers 83 and 93. For example, the "Hitachi LCD Driver LSI Data Book" published by Hitachi, Ltd. It is preferable to use the liquid crystal driver HD66107T described in "(5th Edition)" (published March 1990), pages 274 to 292.

The display panel 1) has gate buses C, , C2. ...
, data bus D r l + D r Z ,...
, pixel transistor 1) formed at their intersection
, pixel electrode S0. .

S02. . . . It is composed of, for example, an electro-optical display element 1) 2 such as a liquid crystal element sandwiched between a pixel electrode and a common electrode to be described later, and a common electrode 1) 3.

PLL (Phase Locked Loop)
121 is a part of the control circuit 12, and a terminal 126
Phase comparator 1 based on the horizontal synchronization signal given from
22, Low frequency filter (LPF; Low P
a5sFilter) 123, voltage controlled oscillator (V
CO；Voltage Controlled 0
It is composed of a frequency divider 124 and a frequency divider 125, and forms a dot clock according to the number of horizontal pixels of the display panel 1).

The alternating current control circuit 7 uses a frequency divider 72 that divides the frequency of a vertical synchronization signal inputted to a terminal 71 by two, and a clock that is synchronized with a dot clock formed by a PLL 121, for example, a clock that is three times the horizontal synchronization frequency. It is composed of an input counter 73, a decoding circuit 74, and an exclusive OR circuit 75.

The contrast adjustment circuit 14 and the brightness adjustment circuit 15 include operational amplifiers 141.142, 151.152, and a current source 144.
, resistors 145, 146, 154° 155, and variable resistors 143, 153. 88 and 89 are voltage sources.

FIG. 4 shows an example of operating waveforms when the configuration example of FIG. 3 is driven according to the field time division scanning method shown in FIG.
The operation will be explained below.

A pulse is applied to the gate bus Gml by a vertical driver 8 (where IH indicates one horizontal scanning period), which are represented by go, g+, and gz symbols, respectively.

Gate bus G a2+ Ga3 has the same waveform as G1, but go and g are IH and 2H delayed from G1), respectively.
Apply a pulse of hg2.

Note that these gate pulses g+, gz, and g3, when selected,
It is obtained by switching the voltage (1)8 of the voltage source 88 and the voltage (2) of the voltage source 89 when not selected using the analog multiplexer 83.

The data bus DrI has go, which is applied to the gate lot G il+ ciz and Gin by the horizontal driver 9.
g+.

3 bits b of data obtained by A/D converting the image signal in accordance with the pulse of g2. , b+ , the voltage corresponding to bz,
Four pre-given voltage levels V1. Vz,
V: Give a selection from l and Va.

At this time, the analog multiplexer 93 outputs the level of the output M of the AC conversion control circuit 7 and the A/D conversion data b. ,b+
, the output of the latch 92 which sequentially outputs signals corresponding to bz, the voltage level is selected as shown in FIG.
When v, ,b.

-0(7) when V 3 and M are at “O” level, b
When L=1, select ■2, and when b=0, select ■4.

In the waveform example of FIG. 4, the voltage V, (field of M=1) of the drain bus DI-1, which is applied in synchronization with the gate pulses go, g+, and gz of the gate lot Gml, and the voltage V
, (field with M=0) are written to the pixel electrode S o l and held until the next data is written.

Therefore, the pixel electrode Sol has an amplitude voltage V, (=V+V
z) will be applied.

Similarly, the pixel electrode SoZ is given synchronized with the gate pulses go, g+, and gz of the gate lotus Gag.
The voltage V i (field where M=1) and voltage V4 (field where M=O) of the drain lotus Dr2 are written to the pixel electrode Sag and held until the next data is written. Therefore, the amplitude voltage VN
An AC waveform of (=V:l V4) will be applied.

In this way, depending on the A/D conversion data content, the effective voltage V
Voltages 9 to 2 are applied to each pixel electrode.

It is clear that the display brightness at this time is expressed by the above-mentioned equation (1) when the response of the display element is fast, and when the response is slow it is expressed by the above-mentioned equation (7). It becomes possible to display halftones according to the converted data.

At this time, the brightness characteristic of the display element is f (V) = k V ---
...Assuming that (10) is approximated, the above (5
) formula, the minimum brightness fmin is fmin =, k VN = k (V3- V4)
・−=(1)). On the other hand, the contrast ratio Ca+ is given by equation (6) above.

Here, assuming that the display element is driven by AC, the waveform given to the pixel electrode S O1+ 802 needs to have a symmetrical voltage waveform for each field with respect to the potential V CON of the common electrode 1) 3. Therefore, the following conditions are satisfied.

2 Substituting the above equation (13) into the above-mentioned equations (1) and (12), the following equation is obtained.

fmin=2k(Vcoq Va) --(1
4)...(15) Therefore, in the brightness adjustment circuit 15, the common electrode potential ■ is applied to the terminal 156. 0i is applied to the brightness adjustment variable resistor 15.
The above (14
) shows that the minimum brightness l1m1n can be adjusted.

Further, in the contrast adjustment circuit 15, a voltage level shift circuit consisting of a constant current circuit 144 and a variable resistor 143 forms a voltage (2) lower by a certain set voltage than the output voltage (4) of the brightness adjustment circuit 14, and acts as a buffer. It can be seen from equation (15) above that the contrast ratio CR can be adjusted by inputting the signal to the analog multiplexer 93 in the horizontal driver 9 through the differential amplifier 142.

Other voltages input to analog multiplexer 93■1
and V are the common electrode potentials v co and 4, respectively, in order to satisfy the above-mentioned conditional expression (13) for converting the display element to alternating current.
A circuit that inverts the potentials of voltages (2) and (4) with reference to differential amplifiers 141, 151, resistors 145, 146 .
1, 54, 155.

In Fig. 4, the reason why the M signal exists within the field is because it is the period during which the video signal of the opposite polarity of the previous field (corresponding to the broken lines (L,) and (Lz) in Fig. 2) is added. .

FIG. 6 is a block diagram showing an example of the configuration of the vertical pulse generating circuit 5 in FIG. 1.

In FIG. 6, a clock is inputted to an input terminal 53 from the control circuit 12 shown in FIG. get a pulse of
It is input to the vertical driver 8 from terminals 54 and 55.

The vertical driver 8 is composed of a shift register 81, a launch 82, and an analog multiplexer 83 as shown in FIG. 3, and has a gate lotus waveform G as shown in FIG.
, G, 2. ...is obtained.

Another embodiment of the invention is shown in FIG. Components equivalent to those shown in the configuration diagram of FIG. 3 are given the same numbers. The difference from the embodiment shown in FIG. 3 is that the selected output voltage of the horizontal driver 9 is set to two values (1) and V3, and the common electrode potential (2) is set. 8 is changed to AC. 73 is an exclusive OR inverter (Ex-
NOR), 84°94.154 is an analog multiplexer that selectively outputs a binary voltage. Hereinafter, the circuit operation of FIG. 7 will be explained using an example of the operation waveform of each part shown in FIG. 8.

As can be seen from the operation waveform example in Fig. 4 already explained,
In the embodiment of FIG. 3, in the field of M=1, the voltage ■1
and ■, and the voltages ■2 and V4 were selected in the M=O field, whereas in the embodiment of FIG. 7, in the M=O field, the input data D to the horizontal driver 9 is It is inverted in advance by an exclusive OR inverter 73,
Voltages ■3 and ■1 are selected.

Further, the common electrode potential V Con is switched between the voltage V7 and the voltage V8 by the output M of the AC conversion control circuit 7 to convert it into AC. The waveform of gate nose C,,,C,□,G,3 is as follows.
It is similar to that in FIG.

The pixel electrode S ol is Vt in the field of M=1, M=0
V3 is applied in the field of , and the common electrode 1)3 is
V in the field of M=1, , ■ in the field of M=O
7 is applied.

At this time, the voltage felt by the display element 1) 2 sandwiched between the pixel electrode S Of and the common electrode 1) 3 is V S I = V I V II in the field of M=1.
・・・・・・(16) In the field of M=O, VSZ=V3 Vt ・・・・・・
(17), and as a result, the amplitude voltage ■, applied to the display elements 1) and 2 is ■5=Vs+Vsz=(V, -VD+(Vt-VB)...
18).

Similarly, for the pixel electrode So2, V N l = V : I V B
・・・・・・(19)■8□−v, −v,
・・・・・・(20)VN=VNI
VN2 = (V3-Vl) + (V7-VB) ・・・・・・
(21).

In this way, depending on the A/D conversion data content, the effective voltage
Voltages 9 to 2 are applied to each display element 1) 2, making it possible to display halftones as in the embodiment shown in FIG.

Here, the conditions for AC drive are V, 10 V, 2-0, so from the above equations (16) and (17), V +
10V3-V7+Ve...
...(22) is obtained.

Then, from equations (18) and (21) above, Vs
-2(2Vcen -V3- Vll) --(
23) VN = 2 (VI VB)
......(24) When the brightness characteristics of display elements 1) and 2 are approximated as in equation (10) above, the average brightness BR and contrast ratio C++ are as shown in (23) above, (
24) is calculated as follows.

8R=(f(VN)+f(Vs))=2
k (Vcen-Ve) ・-125
) Therefore, it can be seen that the average brightness Bm can be adjusted by adjusting the voltage of (2), and the contrast ratio CR can be adjusted by adjusting the voltage of (2).

The brightness adjustment circuit 15 in FIG. Two voltages (7) and (2) are switched and applied to the common electrodes 1) and 3.

Voltage VB is a reference potential V ce applied to terminal 158
n is divided by a variable resistor 153 and passed through a differential amplifier acting as a half sofa to an analog multiplexer 157.
giving to The voltage ■7 is changed to the voltage ■7 by an inverting amplifier composed of a differential amplifier 151 and resistors 154 and 155.
8 is inverted with respect to the reference potential V cen and applied to the analog multiplexer 157, and it is clear that the above equation (22) is satisfied. In this way, by adjusting the variable resistor 153, the voltage 7 can be adjusted, and the above (
It can be seen that the average brightness B8 can be adjusted as shown in equation 25).

Similarly to the brightness adjustment circuit 15, the contrast adjustment circuit 14 in FIG. ,V, is obtained. That is, it can be seen that the contrast CR can be adjusted as shown by the above equation (26).

The multi-gradation display device described above is, for example, 3b
By sequentially selecting each pixel three times in one field using the IT A/D converter, 8 (=23) gradation display is realized. In order to increase the number of gradations, it is necessary to increase the number of times each pixel is selected in one field, but this may not be possible due to the operating speed of the transistor formed in each pixel, for example. FIG. 9 shows an example of an auxiliary circuit necessary to display a larger number of gradations without increasing the number of pixel selections in one field.

A portion surrounded by a broken line frame 31 in FIG. 9 is an attached thinning circuit, which is used by being inserted, for example, into the connection portion between the A/D converter 3 and the memory 4 shown in the embodiment of FIG.

In FIG. 9, a video signal is applied to the terminal 31, and A
/D converter 3 converts, for example, a 4-bit PCM signal b
o” + b+” + bz” + b2”. An output signal M, which is inverted for each field, of the AC conversion control circuit 7 shown in FIG. 3, for example, is input to the terminal 73, and is used as the thinning signal MB.

32.33, 34.35 are composed of, for example, 1-bit adders, each carry signal is input to the next stage, and the output of the adders 33, 34.35 is input to the input signal b0 of the memory 4. ．． Used as b+, riz. The OR circuit 36 forms a logical OR of the carry signal and the addition output as a countermeasure against overflow.

By connecting in this way, the lowest pitch of the A/D conversion output (b). When 1 is 0, b,=b,”.

b+=bz", t+z=b3", and the second "+2 (b2°+2b3") gradation among the 8 gradations is displayed.

That is, the least significant bit of the A/D conversion output is discarded and the upper three bits are used for display.

Next, if the lowest bit (be) of the A/D conversion output is 1, bo=b+ in the field where M=0.

b+ = bz", bt = b3", and the first +" +2 (bz" + 2 bi") floor tA(
(upper 3 bits of A/D conversion output) is displayed, but M=1
In the field, the attached thinning circuit 31 adds 1 to the 2nd ``+2(b2°+2b3'')+1 gradation (A
In order to display the highest 3 bits obtained by rounding up the least significant bit of the /D conversion output, the average gradation in 2 fields is calculated as d-+2(bz'''+2b3°)+0.5.
It will display gradations.

However, b0°=b1'=b2'=b? If =1, then
If 1 is added in the field where M=1, a carry occurs, and therefore it becomes impossible to display the gradation by adding 1. Therefore, the OR circuit 36 uses the 7th gradation to display the gradation.

That is, when b-=b2°"bz"=1, b
(Regardless of the value of 1", all fields are displayed at the 7th gradation out of 8 gradations. As a result, 15 gradations from 0 to 7 can be displayed in 0.5 gradation steps. In this way, the number of display gradations can be almost doubled without increasing the number of sequential selection circuits for each number of strokes in one field.

At this time, when b,”=1, the field of M=O and M
Since the displayed gradation is shifted by 1 in the field where M = 1, when the display element is driven with AC by providing a negative polarity electrode in the M = O field and a positive polarity electrode in the M = 1 field, the display element A DC component will be applied to the

However, the voltage difference between the fields is 8 orders of magnitude,
The DC component (1) applied to the display element is half of that.

Voc= (VS VN) --(
27) For example, Vs = 13 VPP, VN =
4 Vrp and ■. ,=0.3V. Of course, the display of bo''=0 assumes ■.,=0■.

Now, the common electrode potential V,. 9 in DC terms, for example 0.
If you raise 15 V in advance, the maximum DC voltage will be +0
．． Within 15 V, it can be set at an acceptable level.

In the above example, the data handled after memory 4 was 3 bits, but if this number of bits is increased to provide even more gradations, the DC component in equation (27) above will become even smaller. is clear.

In addition, in the explanation so far, the signal given to the terminal 73 is
It was a field-by-field inversion signal, but this is a signal obtained by dividing the dot clock by 2 or a horizontal synchronization signal by 2, etc., and controlling the rounding down and rounding up of the least significant bit between adjacent pixels. Accordingly, the number of gradations that can be displayed as average luminance can be increased.

A main part of another embodiment of the present invention is shown in FIG.

Similar to the thinning circuit of FIG. 9, the aim is to display multiple gradations through thinning. A feature is that, instead of the thinning circuit 31, a look-up table (LUT) 36 constructed of, for example, a read-only memory (ROM) is used.

In FIG. 10, the output signal of the 8-bit A/D converter 3 is shown. For example, a thinning signal that is input from the terminals 74.75 and switched for each field or pixel together with ''' to b7' is supplied as the address of the ROM used as LUT3, and the 6-bit Pc signals b0 to b5 are The data is supplied to the memory 4 as

In this way, by using the LUT 36, there is an advantage that it also has the function of so-called gamma correction, which corrects the signal when the voltage-luminance characteristic of the display pixel is different from that assumed by the input video signal. .

In the embodiment whose main part is shown in FIGS. 9 and 10, an A/D converter with the number of bits corresponding to the number of gradations to be displayed is required, regardless of the number of bits of the PCM signal handled by the memory. Become. Generally speaking, as the number of bits handled by an A/D converter increases, the price, power, etc. will increase.
I want to use a converter.

To meet this demand, we use an A/D converter with the same number of bits as the PCM signal handled by the memory.
The main part of an embodiment that realizes multi-gradation display by thinning display is as follows.
This is shown in Figure 1) and Figure 12.

In the main part of the embodiment shown in FIG. 1), the part surrounded by the broken line 21 is the attached thinning circuit. For example, the MB multiplied signal, such as a field-by-field inverted signal, applied to the terminal 73 controls the analog multiplexer 24 and outputs a voltage of half the minimum gradation voltage (KLSB) of the A/D converter 3 outputted from the voltage source 25. , 0■ are switched and applied to the adder 23, added to the video signal input to the terminal 22, and applied to the A/D converter 3. This is just an analog implementation of the attached decimation circuit 31 in the main part of the embodiment shown in FIG. The operations after the memory 4 are the same as in the case of FIG.

In the main part of the embodiment shown in FIG. 12, instead of the analog multiplexer 24 shown in FIG. 26 is used.

This random number voltage generation source 26 has a random voltage amplitude, and by using a source that generates each voltage with the same frequency over the voltage range of the I LSB, it is possible to thin out the voltage without using a thinning control signal. A PCM signal can be obtained. The random number voltage generation source 26 includes thermal noise of a resistor, avalanche breakdown noise of a transistor, and the like.

An alternative approach to field time division scanning for use in other embodiments of the invention is shown in FIG.

The difference from that shown in Figure 2 is that the signal retention period of each pixel corresponding to the most significant bit bz of A/D conversion data is divided into two, and each pixel within one field is divided into two. The point is that the selection was made sequentially a total of four times, including one time. One real wAL2 shown in FIG.
Figure 7: The two lines L 2 I and L z z represent this. FIG. 14 shows an example of the operation waveforms of each part when this scanning method is applied to the embodiment shown in FIG. 3 and driven.

The main difference between the operating waveform examples in Fig. 4 and Fig. 14 is that
In addition, since each pixel is sequentially selected four times within one field, the holding period corresponding to the topmost via) bz required to select one row is divided into two, and aZl+ azz (az
+= azz:2 az ), the longest retention period in the field was halved. Thirdly, all and aZ20
The point is that the polarity of the video signal is reversed during the period.

The first problem is that the time required to select one line becomes shorter and the scanning speed required of the display panel becomes higher, but I think this can be solved by using the above-mentioned thinning scan in combination.

The second point is that, for example, if we consider an active matrix liquid crystal panel in which each pixel uses a display element consisting of a transistor and a liquid crystal cell, it is necessary to effectively hold the written voltage even outside the selection period. Although it is desirable to add a storage capacitor in parallel with the liquid crystal cell capacitor, halving the maximum retention period means that the storage capacitor to be added can be reduced. This leads to a reduction in the area for forming the storage capacitor, which leads to an improvement in brightness due to an improvement in the aperture ratio.

The third point is that even when the display contents of the first field and the second field change greatly, especially in the case of displaying a moving image, transiently applied DC components can be suppressed. For example, in the first fee, the DC component is (vs V
However, in the embodiment shown in Fig. 14, at least the most significant bit of the A/D conversion output can be converted to AC within the field, so the DC component can be reduced by almost half. There is.

FIG. 15 shows the relationship between the AC drive waveform of each pixel and the information of each bit of the digital PCM signal in the present invention.

In FIG. 15, the horizontal axis represents time and the vertical axis represents polarity. (a) and (bL) (c) show the case where the configuration example of the embodiment in FIG. 3 is driven by the driving method shown in FIGS. 2 and 4, which is explained using a 3-bit PCM signal as an example. Examples are 8 bits, 7 bits, and 6 bits, respectively.

FIG. 15(d) is an example of the driving method shown in FIGS. 13 and 14, in which the period corresponding to the most significant bit b5 in (C) is divided into two and the polarity is reversed within one field. in,
The periods divided into two are indicated by bsl and bsz. (e) shows one half of the most significant bit, bs2, and the next bit, b.
This method further reduces the direct and current components in the moving image by inverting the polarity within the field during the period corresponding to 4.

In this way, various methods of inverting the polarity within a field, the order of arrangement of each bit within the field, etc. can be considered.

Next, specifically, as a video signal, for example, NTSC system with 262.5 lines per field, and PAL system with 312.5 lines per field.
/PC for displaying SECAM format TV signals
Examples of retention periods corresponding to each bit of the M signal are shown in FIGS. 16 and 17, respectively.

In addition, (a), (b), (c) in Fig. 16,
(d).

(e) shows the drive waveforms (a) and (b) in FIG. 15.

This corresponds to (c), (d), and (e),
bSin bSR has the same value as bit b of the PCM signal, but since it divides the period corresponding to b into two,
For convenience, b Sl and b 52 are given different symbols.

The first feature of FIGS. 16 and 17 is that almost all of the l-field period is given to the holding period and selection time, respectively.

For example, in FIG. 16(-a), the total value of the holding period of each bit is 261.5 H, and the period of selecting one row selection time -H eight times becomes 262.5 H, which is equal to the l field period. be equal. In this way, by using almost the entire l-field period, there is an advantage that the effective voltage of the display cell can be increased.

The second feature is the retention period a for i bits.

However, the holding period for the lower (i-1) bits is more than twice the holding period a, -1. Therefore, if the most significant bit is n bits, a -> 2 ''' a o
-=428) holds true.

The reason for this is as follows. That is, a, e=23i
If we try to satisfy -1, the following problem arises. For example, in FIG. 16(C), bo=4°b+ =8. b
z=16. bz=32. ba=64゜bs=12
The setting is 8, and together with the selected time IH minutes, it is 253
H is fine. 9.5 difference from 1 field 262.58
In order to avoid applying voltage to H, 1
This necessitates increasing the number of times each pixel in the field is selected, causing a problem with the scanning speed of the display section.

Furthermore, as described in the first feature, it is necessary to use the entire field' from the viewpoint of increasing the effective voltage. Therefore, the remaining 9.5H will be allocated to each bit, but in order to minimize the error and ensure linearity with respect to minute voltages, we will distribute the remaining 9.5H to each bit in order of a, Pia, and Pia from the upper bit.
i−+ (however, P, ≧2), and p,
are arranged so that they are almost equal.

The third feature is that the fraction of 0.5H is placed in the most significant bit,
The point is that it is used by increasing or decreasing 0.5H for each field. For example, the most significant bit bs in FIG. 16(C)
The retention period is 133.5H, which indicates that 133H and 134H are switched and used for each field. As described above, this is rounding to use the entire period of the l field.

Although the above explanation has focused on time-division scanning in units of fields, it is clear that similar time-division scanning can be performed in units of one frame corresponding to two fields.

[Effects of the Invention] According to the present invention, a horizontal circuit that selects and outputs a predetermined voltage has a relatively small circuit scale, has little variation in output voltage, and is easy to obtain a high withstand voltage at high speed. Easily adjust brightness and contrast using a scanning circuit
Since J adjustment is possible, it is possible to realize a multi-gradation display device with low cost, less display unevenness, and high definition.

For example, ferroelectric liquid crystals with relatively fast response speed (and high driving voltage), PDL C (Polymer Di
spersion Liquid Crystal
) etc. as a display element can easily realize a multi-gradation display device.

In addition, when used in combination with thinning display, it is possible to display more gradations without increasing the number of field time-division scans.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a multi-gradation display device as an embodiment of the present invention, FIG. 2 is an explanatory diagram of the relationship between scanning lines and scanning times to show field time-division scanning of the display panel, and FIG.
The figure is a circuit configuration diagram of the main parts of a multi-gradation display device as an embodiment of the present invention, and FIG. 4 is an example of operation waveforms of each part when the embodiment of FIG. 3 is driven by the scanning method shown in FIG. 2. FIG. 5 is an explanatory diagram of a truth table showing the selected output state of the analog multiplexer in the horizontal driver. FIG. 6 is a block diagram showing an example of the vertical scanning pulse generation circuit. FIG. A circuit configuration diagram of the main parts of a multi-gradation display device as another embodiment, FIG. 8 is a timing chart showing an example of operation waveforms of each part of the embodiment of FIG. 7, and FIGS. 9 and 10 are digital A block diagram showing an example of a system thinning circuit, Figures 1) and 12 are block diagrams showing an example of an analog system thinning circuit, and Figure 13 shows field time division scanning when the most significant bit is divided into two. FIG. 14 is a timing chart showing the operation waveforms of each part when driving the embodiment shown in FIG. 3 using the scanning method shown in FIG. 13, and FIG. Timing charts showing the relationship between drive polarity of each pixel and intra-field time division in the scanning method, FIGS. 16 and 17
The figures are an explanatory diagram showing an example of a retention period corresponding to each bit in NTSC and PAL/SECAM television signal display, respectively, and Fig. 18 is a schematic diagram showing a conventional example of the configuration of an active matrix liquid crystal display device. It is. Explanation of symbols 1...Video signal input terminal, 2...Video signal processing circuit, 3...A/D converter, 4...Memory, 5...Vertical scanning pulse generation circuit, 6...・Horizontal scanning pulse generation circuit, 7... AC conversion control circuit, 8... Vertical driver,
9...Horizontal driver, 1)...Display panel, 12.
...Control circuit, 14...Contrast adjustment circuit, 15
...Brightness adjustment circuit, 121...PLL circuit, 141
, 142.151.152...Differential amplifier, 81.9
1...Shift register, 82.92...Latch, 8
3,84.93.94,157...Analog multiplexer, Dr...Data bus, Ga...Gate bus, 1)1...Pixel transistor, 1)2...Display element, V CON・・・Common electrode, 32, 33, 34.3
5... Adder, 36... Lookup table agent Patent attorney Akio Namiki @1m 121!1 5th illustration b Figure 7 iris 8! ! ! + Figure 10 Figure 1) Figure 13 Figure 814 ■ Figure 16 Figure 17 Procedural amendment March 19, 1991 Director General of the Patent Office Toshi Uematsu 1, Indication of case Patent Application No. 314348 of 1990 2, Name of the invention: Multi-gradation image display device 3, relationship with the amended case Patent applicant name (510) Hitachi, Ltd. 4, Agent
Person ◎105 Speak 03 (3580) 9513
Address Namiki Patent Office 6, 5th floor, Fujita Building, 2-12-8 Shinbashi, Minato-ku, Tokyo Subject of amendment Description and drawings (3, Ryu 3j 7, Contents of amendment (1) Specification page 31 In formula (12) on line 10, do. (2) In page 46, line 18 of the specification, ' a 22
do. (3) In the attached drawings, Figure 7 is corrected as shown in the attached sheet. That is, in FIG. 7, subscripts are added to the names "v" of the output signals of the differential amplifiers 141 and 142, respectively, such as ry, j,
ry,” he corrected. (4) In the attached drawings, Figure 9 is corrected as shown in the attached sheet. Correction No. 7 Figure Correction No. 9 Prisoner

Claims (1)

[Claims] 1. In a multi-gradation image display device that displays a video signal represented by digital data with a number of bits n in multiple gradations with a number of gradations determined by the number of bits n, in a certain selection period. A display panel configured by arranging display elements in a matrix as pixels, which maintain almost the written signal outside the selected period to control the electro-optical characteristics and maintain the display state; and the display panel is configured. A vertical drive circuit that sequentially selectively scans display elements in a matrix row by row, and a plurality of voltages that are pre-assigned to the display elements in the rows selected by the vertical drive circuit according to the value of the video signal to be displayed. A horizontal drive circuit for writing a voltage selected from among them, and the horizontal and vertical drive circuits sequentially write each display pixel at least n times in one field period in synchronization with the video signal to be displayed. A control circuit that performs selective scanning, and a control circuit that enables multi-gradation display according to the value of the video signal to be displayed. A multi-gradation image display device comprising: adjusting means for adjusting the brightness or contrast of a displayed image by varying the voltage level of the selected voltage signal. 2. In a multi-gradation image display device that displays a video signal represented by digital data with a number of bits n in multiple gradations with a number of gradations determined by the number of bits n, a signal written in a certain selection period is A display element that maintains its display state by controlling its electro-optical characteristics during periods other than the selection period, and one of the two electrodes for signal writing is a common electrode that is shared with other display elements. a display panel configured by arranging display elements connected to the display panel as pixels in a matrix; a vertical drive circuit that sequentially selects and scans the display elements in the matrix forming the display panel row by row; and a vertical drive circuit. a horizontal drive circuit that writes a voltage selected from among a plurality of pre-assigned voltages to a display element in a row selected by the method according to the value of a video signal to be displayed, and the horizontal and vertical drive circuits. and a control circuit that sequentially selectively scans each display pixel at least n times during one field period in synchronization with the video signal to be displayed, according to the value of the video signal to be displayed. A multi-gradation image display device, which enables multi-gradation display and further comprises: adjusting means for adjusting the brightness or contrast of a displayed image by varying the voltage level of the common electrode. 3. In a multi-gradation image display device that displays a video signal represented by digital data with a number of bits n in multiple gradations with a number of gradations determined by the number of bits n, a signal written in a certain selection period is A display panel configured by arranging display elements as pixels in a matrix, which maintain almost the same state of display by controlling their electro-optical characteristics during a period other than a selection period; and a matrix-shaped display element constituting the display panel. A vertical drive circuit that sequentially selects and scans each row, and a voltage that is selected from a plurality of pre-assigned voltages to the display elements of the row selected by the vertical drive circuit, depending on the value of the video signal to be displayed. A horizontal drive circuit for writing a voltage and the horizontal and vertical drive circuits are used to sequentially select each pixel m times (where n+1≦m) in one field period in synchronization with the video signal to be displayed. a control circuit that causes the pixel to scan and sets the first and second holding periods, starting from the longest period, during which each pixel is selected once and holds a signal until the next selection to be equal in one field period; A multi-gradation image display device comprising: 4. The multi-gradation image display device according to claim 3, wherein the display element comprises an element that needs to be driven for writing by an AC drive signal, and
A multi-gradation image display device, characterized in that at least one of the m times of writing drive for the display element in a field period, the writing drive is performed using a signal whose polarity is inverted. 5. In a multi-gradation image display device that displays a video signal represented by digital data with a number of bits n in multiple gradations with a number of gradations determined by the number of bits n, a signal written in a certain selection period is A display panel configured by arranging display elements as pixels in a matrix, which maintain almost the same state of display by controlling their electro-optical characteristics during a period other than a selection period; and a matrix-shaped display element constituting the display panel. A vertical drive circuit that sequentially selects and scans each row, and a voltage that is selected from a plurality of pre-assigned voltages to the display elements of the row selected by the vertical drive circuit, depending on the value of the video signal to be displayed. A horizontal drive circuit for writing a voltage and the horizontal and vertical drive circuits are used to sequentially selectively scan each display pixel at least n times in one field period in synchronization with the video signal to be displayed. a control circuit that sets a period in which a signal corresponding to the most significant bit is held in a pixel to be longer than 2^(^n^-^1^) times a period in which a signal corresponding to the least significant bit is held; A multi-gradation image display device comprising: 6. In a multi-gradation image display device that receives a video signal expressed as digital data with k bits and displays it in multiple gradations, the signal written in a certain selected period is almost retained during periods other than the selected period. A display panel is constructed by arranging display elements as pixels in a matrix to control their electro-optical characteristics and maintain a display state, and the matrix-shaped display elements constituting the display panel are sequentially selectively scanned row by row. a vertical drive circuit; and a horizontal drive circuit that writes a voltage selected from among a plurality of pre-assigned voltages to display elements in a row selected by the vertical drive circuit, according to the value of a video signal to be displayed. , the video signal with k bits is input, and every field or period corresponding to one display pixel,
a signal processing circuit that alternately outputs the signal by rounding down the lower digits of the number of bits k to obtain the number of bits n (k>n) or rounding up the lower digits of the number of bits k to obtain the number of bits n; a control circuit configured to act as a drive circuit and sequentially selectively scan each display pixel in synchronization with the input video signal at least n times equal to the number n of bits output from the signal processing circuit; A multi-gradation image display device characterized by: 7. After converting the input video signal into digital data with n bits by an A/D converter, in a multi-gradation image display device that displays the input video signal in multiple gradations, the signal written in a certain selection period is A display panel configured by arranging display elements as pixels in a matrix, which maintain almost the same state of display by controlling their electro-optical characteristics during a period other than a selection period; and a matrix-shaped display element constituting the display panel. A vertical drive circuit that sequentially selects and scans each row, and a voltage that is selected from a plurality of pre-assigned voltages to the display elements of the row selected by the vertical drive circuit, depending on the value of the video signal to be displayed. a horizontal drive circuit for writing a voltage; means for generating an analog signal having a magnitude that is less than the voltage corresponding to the least significant bit of the A/D converter and more than approximately half the voltage; the analog signal and the input video signal; an adder that adds the A/D converter and provides the A/D converter; and the horizontal and vertical drive circuits add at least the A/D converter;
a control circuit that sequentially selectively scans each display pixel in one field period in synchronization with the input video signal the same number of times n as the number n of bits output from the /D converter; A multi-gradation image display device characterized by: