JPH07129132A - Liquid crystal display - Google Patents

Abstract

PURPOSE:To display an image of high image quality by reducing a noise, and reducing tailing. CONSTITUTION:A liquid crystal display has a data converting circuit 19 to convert display data into display data which can express the same gradation with every signal electrode, a signal electrode driving circuit 20 to offset a spike waveform generated in a scanning electrode by outputting the display data by data conversion with every prescribed signal electrode, a scanning electrode driving circuit 21 to scan the scanning electrode horizontally, a liquid crystal display panel 22 and a driving voltage generating circuit 23, and a controller 15 outputs a control signal to a field memory 18, the data converting circuit 19 or the like, and the data converting circuit 19 performs data conversion on the display data to be supplied to the signal electrode driving circuit 20 to drive the signal electrodes by time sharing by plural frames. When single gradation is expressed by four frames, voltage in the inverse direction of the direction of voltage impressed with every frame of the first signal electrode is impressed correspondingly on the respective frames of the next second signal electrode, and these two kinds of display data are selected by the same scanning electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device used for a liquid crystal television or the like, and more specifically, in a liquid crystal display device which realizes gradation expression by thinning out frames, a tailing phenomenon which leads to deterioration of image quality is reduced. The present invention relates to a possible liquid crystal display device.

[0002]

2. Description of the Related Art For example, a voltage averaging method is used to drive a liquid crystal display panel of a conventional liquid crystal display device. In the case of displaying halftone, a pulse width modulation method (PWM: pulse: PWM: pulse) in which an ON voltage is applied for a certain period within one common selection period, that is, a period corresponding to display data, and an OFF voltage is applied for the remaining period. width modulation) has been adopted.

Further, in a liquid crystal display circuit for driving a matrix type liquid crystal display panel, the segment drive waveform influences the common drive waveform via the liquid crystal, and the common drive waveform rises or falls, that is, depending on the data. A glitch occurs due to the switching of the applied voltage. This glitch causes so-called crosstalk, which is so-called stringing, and causes deterioration of image quality. In particular, many liquid crystal display devices used in office automation equipment and the like have a phenomenon such as tailing, which causes deterioration of image quality.

A phenomenon which is one factor of the tailing will be specifically described.

For example, as shown in FIG. 5, there is an LCD panel 1 having eight signal electrodes (Y1 to Y8) and six scanning electrodes (X1 to X6), and this LCD panel 1 is shown in FIG.
It shall be driven by a signal as shown in. The signal in FIG. 6 is an example of a case where gray scale display is performed by thinning out frames, and in this case, one gray scale can be expressed by 4 frames, and 5 gray scales are possible. That is, (000
There are 5 gradations of 10,000, 0011, 0111, and 1111), and Y (A), Y (F), and Y (S) of FIG. 6 are examples in which the entire screen has halftones.

[0006]

[Problems to be Solved by the Invention] However, at this time,
Actually, the change of the signal electrode (segment) appears as noise on the scanning electrode (common), which causes an error in the effective voltage applied to the liquid crystal, causing a problem of tailing. For example, in the case of the Y (f) waveform in FIG. 6, a glitch (gli
The noise called "tch" is overlaid, and the effect of this glitch causes an error in the effective voltage applied to the liquid crystal, resulting in tailing.

Therefore, an object of the present invention is to provide a liquid crystal display device capable of displaying a high quality image by reducing noise and reducing trailing.

[0008]

The invention according to claim 1 is
To achieve the above object, in a liquid crystal display device that performs gradation display on a liquid crystal display panel in which a plurality of scan electrodes and signal electrodes are arranged in a matrix, a memory for storing display data and a display data read from the memory are provided. Data conversion means for converting display data capable of expressing the same gradation for each predetermined signal electrode, and a signal electrode drive circuit for outputting the display data converted by the data conversion means to the signal electrode, The conversion means performs data conversion on the display data supplied to the signal electrode drive circuit which drives the signal electrodes in a time division manner in a plurality of frames, and when expressing one gradation in a predetermined frame, The voltage opposite to the direction of the voltage applied to each frame of the first signal electrode corresponds to each frame of the next second signal electrode. Over, and to select the two types of display data in the same scan electrodes.

As described in claim 2, for example, the data converting means can express the same gradation by reversing the direction of the voltage applied to the signal electrode for each predetermined signal electrode group. You may make it convert into display data.

As described in claim 3, for example, the data converting means expresses the same gradation by reversing the direction of the voltage applied to the signal electrode for each of the signal electrodes. The display data may be converted into possible display data.

The data conversion means may perform data conversion on display data supplied to a signal electrode drive circuit for time-divisionally driving the signal electrodes in a plurality of frames. Good.

[0012]

According to the present invention, when the video signal is input, the input video signal is converted into a digital signal by the A / D conversion means and stored in the memory. The display data stored in the memory is read in frame units for time-division driving, for example, and is converted into display data capable of expressing the same gradation for each predetermined signal electrode by the data conversion means.

In this case, for example, when expressing one gradation in four frames, a predetermined voltage is applied to each frame of the first signal electrode and each frame of each first signal electrode is applied. Data conversion is performed so that a voltage in the direction opposite to the voltage applied to each of the second signal electrodes is applied corresponding to each frame of the next second signal electrode.

The data-converted display data is output to the signal electrode drive circuit, and the two types of display data are applied to the first and second signal electrodes by the signal electrode drive circuit, and the same scan electrode is used to apply the two types of display data. Two types of display data are selected.

Therefore, the reverse voltage applied to the first and second signal electrodes reduces the effective voltage error and cancels the spike waveform generated in the scan electrodes, and in the liquid crystal display device using the frame thinning display. The trailing phenomenon can be made less visible.

[0016]

EXAMPLES Examples will be described below with reference to FIGS.

1 to 4 are views showing an embodiment of a liquid crystal display device, and this embodiment is an example in which the liquid crystal display device is applied to a liquid crystal television.

First, the structure will be described. FIG. 1 is a block configuration diagram of a liquid crystal television including a liquid crystal display device.

In FIG. 1, a liquid crystal television 10 includes an antenna 11, a tuner 12, an IF circuit 13, and a chroma circuit 1.
4, controller 15, reference voltage generation circuit 1
6, an A / D converter 17, a field memory 18, a data conversion circuit 19, a signal electrode drive circuit 20, a scan electrode drive circuit 21, a liquid crystal display panel 22, and a drive voltage generation circuit 23.

The antenna 11 receives radio waves from the tuner 1
The tuner 12 selects the designated channel according to the tuning control signal VT input from the controller 15, converts the received radio wave supplied from the antenna 11 into an intermediate frequency signal, and outputs the intermediate frequency signal to the IF circuit 13.

The IF circuit 13 is composed of an intermediate frequency amplification circuit, a video detection circuit, a video amplification circuit and the like. The intermediate frequency signal input from the tuner 12 is subjected to video detection by the video detection circuit to extract a color video signal, An audio signal is taken out from the color video signal and output to an audio circuit (not shown), the video amplification circuit amplifies the color video signal and outputs it to the chroma circuit 14, and the horizontal sync signal Hsync is output from the color video signal. And vertical sync signal Vs
The ync is taken out and output to the controller 15.

The chroma circuit 14 separates the R, G and B color video signals from the color video signal input from the IF circuit 13 and outputs them to the A / D converter 17.

The controller 15 is the A / D converter 1
7, a CPU (Central Processing U) that controls the field memory 18, the data conversion circuit 19, the signal electrode drive circuit 20, the scan electrode drive circuit 21, and the drive voltage generation circuit 23.
nit) etc., and outputs a tuning control signal VT to the tuner 12 according to the tuning key operation,
The signal electrode drive circuit 20 is based on the horizontal synchronizing signal Hsync and the vertical synchronizing signal Vsync input from the F circuit 13.
And various timing control signals for controlling the scan electrode drive circuit 21 are generated and output to the signal electrode drive circuit 20 and the scan electrode drive circuit 21.

That is, the controller 15 generates and outputs the sampling clock φs to the A / D converter 17, the RAM control signal and the clock CKd to the field memory 18, and the selection signal Sel and the clock CKd to the data conversion circuit 19. Control signals a, b, c, d
To the signal electrode drive circuit 20 and the signal electrode drive circuit 21, respectively.

The reference voltage generating circuit 16 is an A / D
The high-side reference voltage VH and the low-side reference voltage VL supplied to the converter 17 are generated.

The A / D converter 17 includes a chroma circuit 14
Each color video signal separated by is converted into a predetermined digital signal based on the sampling clock (High side reference voltage VH, Low side reference voltage VL) from the controller 15 and output to the field memory 18.

The field memory 18 comprises a RAM 31 (FIG. 2) provided on a memory board.
Reference numeral 31 is a frame memory for temporarily storing image data digitized to a predetermined bit, here 3 bits, from the A / D conversion circuit 17. Here, in this image display device, a period for scanning the entire one screen is referred to as one frame, and one screen is displayed in one field of the video signal, and thus the cycle (frame frequency) is 1 / 60S.

The data conversion circuit 19 is a circuit for converting display data read from the field memory 18 (RAM 31) in units of frames into display data capable of expressing the same gradation for each signal electrode. Data is read from the field memory 18 (RAM 31) having the data of one screen at the timing of the clock CKd, selected at the timing of the control signals a, b, c, d, and the noise given to each scanning electrode (common) is reversed. This is a decoding circuit for converting data supplied to the signal electrodes (segments) so as to be oriented in the same direction so as to invert the polarity for each signal electrode.

The data converted by the data conversion circuit 19 is output to the signal electrode drive circuit 20.

The drive voltage generating circuit 23 is the controller 1
The signal electrode drive circuit 20 based on the control signal output from
And a drive voltage to be supplied to the scan electrode drive circuit 21. For example, the drive power generation circuit 23 generates voltage values V0, V2, V4 supplied to the scan electrode drive circuit 21 and voltage values V1, V3 supplied to the signal electrode drive circuit 20, and each drive circuit outputs these voltage values. Based on this, a predetermined potential is output to the electrodes of the liquid crystal display panel 22.

In the liquid crystal display panel 22, a plurality of scanning electrodes and a plurality of signal electrodes are arranged so as to face each other with a liquid crystal layer in between and arranged in a matrix, and the signal electrode drive circuit 20 for driving the signal electrodes and the scanning. A scan electrode drive circuit 21 for driving the electrodes is provided. For example, as in the case of FIG.
Eight signal electrodes (Y1 to Y8) and six scanning electrodes (X1
To X6), the gradation display is performed by thinning out the frames, which displays 5 gradations in 4 frames.

As described above, in the present embodiment, in order to reduce the trailing phenomenon, two kinds of display signals are selected and displayed so that noises in the same scanning electrode are in opposite directions as much as possible. There is.

FIG. 2 is a circuit diagram of the field memory 18, the data conversion circuit 19, and the signal electrode drive circuit 20.

In FIG. 2, the field memory 18 is
The RAM 31 is composed of a RAM 31. The RAM 31 temporarily stores the 3-bit digital image data from the A / D conversion circuit 17, and the data A2, A at the timing of the clock CKd.
1, A0 is read.

The data conversion circuit 19 includes AND circuits 32 to 32.
37, OR circuits 38 to 40, an inverter 41, and a flip-flop (FF) circuit 42.

The most significant bit (MSB) data A2 read from the field memory 18 (RAM31) is input to the OR circuits 38 and 39, and similarly the data A1 read from the RAM31 is input to the AND circuits 32 and 34. OR through
The least significant bit (LSB) data A0 input to the circuits 38 and 39 and read from the RAM 31 is stored in the AND circuit 33,
It is input to the OR circuits 38 and 39 via 35.

Control signals a, b, c, d (see FIG. 4) are input to the AND circuits 32 to 37 from the controller 15, and the data A1 is output at the timing of the control signals a, b, c, d shown in FIG. , A0 are output to the OR circuits 38 and 39. Figure 4
, The control signal b has a phase opposite to that of the control signal d,
The control signal a is a signal shifted by one frame from the control signal c. The outputs of the OR circuits 38 and 39 are the AND circuits 36 and 3
7 and the OR circuit 40, the flip-flop (F
F) It is output to the circuit 42. A selection signal Sel is input from the controller 15 to the AND circuits 36 and 37,
The selection signal Sel selects the data output from the OR circuit 38 at the timing of the control signals c and d and the data output from the OR circuit 39 at the timing of the control signals a and b, and the flip-flop (FF). It is output to the circuit 42. The flip-flop (FF) circuit 42 is shown in FIG.
Signal electrode drive circuit 2 at the clock CKd timing shown in
Output data to 0.

In the data conversion circuit 19, the RAM 31
The respective data read from are Y (F) and Y in FIG.
The data is converted so that the noise given to each common is in the opposite direction as in the relationship of (G).

Further, in FIG. 2, the signal electrode drive circuit 2
0 indicates the flip-flop (FF) circuits 51 to 57 that hold the data from the data conversion circuit 19 at the clock CKd timing shown in FIG. 4 and the data from the flip-flop (FF) circuits 51 to 57 at the clock CKh timing. Flip-flop (FF) circuits 58 to 6 for holding
5 and level shifters 66 to 73 having buffers for forming driving waveforms for each gradation of the flip-flop (FF) circuits 58 to 65.

Flip-flop (FF) circuits 51 to 57
Has a function as a shift register, latches an input signal with a transfer clock CKd, and flip-flop (FF) circuits 51 to 57 and flip-flop (FF) in the next stage.
The signals are sequentially output to the circuits 58 to 65.

In the signal electrode drive circuit 20, for example, as the flip-flop (FF) circuits 51 to 57, a dynamic shift register or the like is actually used.

Flip-flop (FF) circuits 58-65
Are latched at the timing of the clock CKh shown in FIG. 4 and output to the level shifters 66 to 73.

The level shifters 66 to 73 raise the input signal to a predetermined potential level, and output it by the buffer based on the high level selection potential V1 and the low level selection potential V3 supplied from the drive voltage generation circuit 23. .

Next, the operation of this embodiment will be described.

First, the basic idea of this embodiment will be described.

In general, the change of the signal electrode (segment) appears as noise on the scanning electrode (common), which causes an error in the effective voltage applied to the liquid crystal, which is a cause of tailing. In this case, all the voltages applied to the signal electrodes are changed in the same direction (for example, from H level to L level).

The present inventor pays attention to this point, and when the signal electrodes are time-divisionally driven in a plurality of frames by the time-divisional driving (matrix drive), the direction of the voltage applied to the signal electrode is set for each signal electrode Considering that the direction is reversed (for example, when one signal electrode is changed from H to L, the next signal electrode is changed from L to H), this causes glitches on the scan electrodes even if the same gradation display is performed. Reverse the direction to eliminate glitches and eliminate trailing.

For example, in the case of an intermediate tone such as Y (f) in FIG. 6, this embodiment corresponds to Y (f) in FIG. 3, and Y (key) in FIG. Also prepare a halftone like. Although Y (f) and Y (ki) in FIG. 3 have the same gradation,
As shown in the scanning electrode (common) of Y (f) and Y (ki) in FIG. 3, the noise is transferred to the scanning electrode (common) in the opposite directions in Y (f) and Y (ki). become. That is, as shown in FIG. 3, in the case of expressing one gradation in four frames, when "1010" is applied to the first signal electrode, the following second
"0101" is applied to the signal electrode of. In this way, by selecting these two types of display signals (segment signals) Y (F) Y (K) with the same common, noise can be reduced by canceling glitches, and liquid crystal using frame thinning display is used. The tailing phenomenon can be made difficult to see on the display device.

The specific operation will be described below with reference to FIG.

In FIG. 2, data is read from the field memory 18 (RAM 31) having one screen data at the timing of CKd (see FIG. 4), and A0 and A1 are a, b or d, c in four frames. Select at the timing of the signal. In this way, the serially converted 5 gradation data is output from the OR circuits 38 and 39. At this time, in each data, the noise given to each common is in the opposite direction as shown in the relationship between Y (f) and Y (ki) shown in FIG.

Then, one of the two signals output from the OR circuits 38 and 39 is fed to the inverter 4
1, a gate circuit composed of AND circuits 36 and 37 and an OR circuit 40, and a flip-flop (FF) circuit 42.
Then, the timing is adjusted again and the signal is output to the signal electrode drive circuit 20.

Here, the timing of selection will be described. For example, when the selection signal is the Sel1 signal of FIG. 4, it is selected every 1 data, and when it is the Sel 2 selection signal, it is selected every 2 data.
In the case of a signal, there is a signal for canceling noise for each signal electrode (segment), and for the Sel2 signal, for each two signal electrodes. The selection signal is not limited to the case of the above-mentioned one or two signal electrodes, and may be every three, four, or more, but the frequency of this Sel signal may not be too low. There is also (of course 1
It doesn't mean anything slower than common). The reason is that there is a lot of similar data (similar gradations) between neighboring data, and it is often possible to cancel noise appropriately, but for example, the right and left edges of the screen This is because there are many cases where the data (grayscale) has completely different grayscales, and in many cases noise cannot be canceled.

The serial data whose timing is adjusted by the flip-flop (FF) circuit 42 is sent to the signal electrode drive circuit 20, and the flip-flop (FF) circuits 51 to 5 are supplied.
The corresponding signal electrodes are sequentially shifted at 7 and 1H (1 common) at the flip-flop (FF) circuits 58 to 65.
During the period, the data is charged to display the same data, and the level shifters 66 to 73 shift the levels to V1 and V3.

At this time, switching (common inversion) is performed by the CKF signal shown in FIG. When the signals Y1 and Y2 thus obtained are Sel1 signals, the Y (F) in FIG.
And Y (ki), and cancel the noise given to each other in common.

In this way, by reducing the noise of the common, the effective voltage error is also reduced, and as a result, the trailing is hard to see and high quality display can be realized.

As described above, the liquid crystal display device of this embodiment outputs the control signal to control each part, the reference voltage generating circuit 16, and the A / D converter 17 for converting the video signal into digital data. , A /
A field memory 18 for storing the video signal converted into digital data by the D converter 28, and a data conversion for converting the display data read from the field memory 18 in frame units into display data capable of expressing the same gradation for each signal electrode. A circuit 19, a signal electrode drive circuit 20 that outputs display data that has undergone data conversion for each predetermined signal electrode to cancel spike waveforms generated in the scan electrodes, a scan electrode drive circuit 21 that horizontally scans the scan electrodes, a liquid crystal display panel 22, and a drive. The controller 15 outputs a control signal to the field memory 18, the data conversion circuit 19 and the like, and the data conversion circuit 19 supplies the signal electrodes to the signal electrode drive circuit 20 which drives the signal electrodes in a time division manner in a plurality of frames. Converts display data to 4 frames In the case of expressing one gradation, a voltage opposite to the direction of the voltage applied to each frame of the first signal electrode is applied corresponding to each frame of the next second signal electrode, and the same voltage is applied. Since these two types of display data are selected by the scan electrodes, noise can be reduced by canceling the glitch, and the trailing phenomenon can be made less visible in the liquid crystal display device using the frame thinning display. . As a result, by reducing the noise of the scan electrodes (common), the effective voltage error is also reduced, and as a result, the trailing is less visible, and high-quality display can be realized.

In each of the above embodiments, the video signal is time-division driven (matrix drive), but the display data is converted into display data capable of expressing the same gradation for each predetermined signal electrode. It goes without saying that any method can be used. If the time division drive is not performed, the field memory becomes unnecessary.

In each of the above embodiments, the liquid crystal display device is applied to a liquid crystal television, but the present invention is not limited to this, and it goes without saying that it may be used in other devices such as a liquid crystal projector. .

Further, it goes without saying that the circuits, elements, the number of gates, and the types of the data conversion circuit are not limited to those in the above-described embodiments.

[0060]

According to the first, second, third and fourth aspects of the present invention, the display data read from the memory is converted into display data capable of expressing the same gradation for each predetermined signal electrode. The spike waveform generated in the scan electrodes can be canceled out, and the trailing phenomenon can be reduced in the liquid crystal display device using the frame thinning display, and high quality image display can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a liquid crystal television as an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a circuit diagram of a field memory, a data conversion circuit, and a signal electrode drive circuit of the same embodiment.

FIG. 3 is a timing chart of signal waveforms of the liquid crystal display device of the example.

FIG. 4 is a timing chart of signal waveforms of the liquid crystal display device of the example.

FIG. 5 is a diagram showing an LCD panel of a conventional liquid crystal display device.

FIG. 6 is a timing chart of drive signal waveforms of a conventional liquid crystal display device.

[Explanation of symbols]

 10 liquid crystal television 11 antenna 12 tuner 13 IF circuit 14 chroma circuit 15 controller 16 reference voltage generation circuit 17 A / D converter 18 field memory 19 data conversion circuit 20 signal electrode drive circuit 21 scan electrode drive circuit 22 liquid crystal display panel 23 drive voltage generation Circuit 31 RAM 32-37 AND circuit 38-40 OR circuit 41 Inverter 42, 51-65 Flip-flop (FF) circuit 66 Level shifter

Claims (4)

[Claims] 1. A liquid crystal display device that performs gradation display on a liquid crystal display panel in which a plurality of scan electrodes and signal electrodes are arranged in a matrix, and a memory for storing display data and display data read from the memory, Data conversion means for converting display data capable of expressing the same gradation for each predetermined signal electrode, and a signal electrode drive circuit for outputting the display data converted by the data conversion means to the signal electrode, the data conversion The means performs data conversion on display data supplied to a signal electrode drive circuit that drives the signal electrodes in a time-divisional manner in a plurality of frames, and in the case of expressing one gradation in a predetermined frame, Is the voltage in the opposite direction to the voltage applied to each signal electrode for each frame for each frame of the next second signal electrode? A liquid crystal display device which is characterized in that so as to select the two types of display data in the same scan electrodes. 2. The data conversion means converts the voltage applied to the signal electrodes for each predetermined signal electrode group in the opposite direction to convert display data capable of expressing the same gradation. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is a liquid crystal display device. 3. The data converting means converts the voltage applied to the signal electrode for each one of the signal electrodes in the opposite direction to convert display data capable of expressing the same gradation. The liquid crystal display device according to claim 1, wherein: 4. The data conversion means is adapted to perform data conversion on display data supplied to a signal electrode drive circuit for time-divisionally driving signal electrodes in a plurality of frames. Liquid crystal display device.