JPH07104715A - Picture display device - Google Patents

Abstract

PURPOSE:To realize the high contrast and high speed response of a liquid crystal display panel and to provide picture display device without undesired radiation. CONSTITUTION:A liquid crystal display device 40 is provided with a liquid crystal display panel 11, a driving electrode circuit for display 12, a driving circuit 13 for scanning electrode, an LC voltage generating circuit 14, a synchronizing processing circuit 15, a Gray code A/D converter 41 for converting an analog video signal to digital data in accordance with a Gray code style, RAM 17 (RAM 1), RAM 18 (RAM 2), a multiplexer 19, a ROM 26 for converting code/data for storing a look-up table for converting the Gray code to a binary code and a look-up table(LUT) tabulating the values of a previous frame and present frame for converting a tone signal, a flip-flop(FF) 21 and a controller 43 and the data between the Gray code A/D converter 41 and the ROM 42 for converting code/data are transferred by the Gray code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device which performs gradation display using a matrix type liquid crystal display panel, and more specifically, to a response speed of gradation change of the liquid crystal display panel while suppressing unnecessary radiation. An image display device that can be improved.

[0002]

2. Description of the Related Art LCD screen displays have high resolution,
High-performance and high-quality display functions such as high gradation, high-speed response, and high contrast are required. TN as the display method
(Twisted Nematic) type, STN (Supertwisted Nemati)
c) type is used, and the driving method is TFT (Thin Film)
Active matrix drive using a transistor and simple matrix drive are adopted. There are two types of image display devices, the simple matrix system and the TFT system, and it is said that the TFT is superior in image quality and response speed. That is, the simple matrix has the drawbacks that i) the response time is slow due to the effect of cumulative response, and ii) the margin is small and the contrast is low due to the high duty.

Particularly, the response of liquid crystal is slow, and when STN is adopted, the contrast is improved but the response is further deteriorated.

Further, in such a conventional image display device, since the image quality is determined by the number of control bits, the circuit scale and the number of wirings are increased in order to obtain a high quality display. There was a problem. For example, if the number of bits can be reduced in a liquid crystal drive circuit that displays gradation on a liquid crystal by pulse width modulation (PWM), the number of wirings and the circuit scale can be reduced, and the device cost can be reduced. However, it was difficult to improve the image quality without reducing the number of bits.

Further, since the liquid crystal display panel generally operates by a cumulative response effect, it has a property of slow response speed.

Therefore, a memory for storing image data is provided, data between old and new frames are compared, and display data corresponding to the data is created by a data conversion circuit using a ROM, so that a liquid crystal display panel is appropriately formed. An image display device using a speed-up circuit for overdriving has been proposed.

FIG. 8 is a block diagram of a conventional high-quality image display device using the speed-up circuit.

In FIG. 8, an image display device 10 includes a liquid crystal display panel 11, a display signal electrode drive circuit 12, a scan electrode drive circuit 13, an LC voltage generation circuit 14, a synchronization processing circuit 15, and a binary code A / D converter. 16, RAM17
(RAM1), RAM18 (RAM2), multiplexer 19, data conversion ROM 20, flip-flop (FF) 21, and controller 22.

In the liquid crystal display panel 11, a plurality of common electrodes and a plurality of segment electrodes are arranged so as to face each other with a liquid crystal layer interposed therebetween and arranged in a matrix, and a display signal electrode drive circuit 12 for driving the segment electrodes. And a scan electrode drive circuit 13 for driving the common electrode.

The synchronization processing circuit 15 is a circuit which discriminates an odd field and an even field from the composite video signal in order to invert and drive the polarity of the video signal for each field, and outputs a field discrimination signal.

The binary code A / D converter 16 converts the analog video signal into image data digitized into 2 bits in accordance with the binary code format.

RAM 17 (RAM 1) and RAM 18
The (RAM2) is a frame memory for temporarily storing image data digitized to a predetermined bit by the A / D converter 16, here 2 bits.

Here, in the image display device, a period for scanning the entire one screen is referred to as one frame, and one screen is displayed in one field of the video signal, so that the cycle (frame frequency) is 1 / 60S. The image display device displays one screen twice by scanning the liquid crystal display panel 11 twice during 1/60 S, and the frequency is 120 Hz. In order to realize this, in this example, two frame memories (RAM 17, RAM 18) are provided, and the frame frequency is increased by reading the data once stored in the memory twice at a predetermined timing.

The analog multiplexer 19 is the RAM 1
Image data stored in RAM 7 (RAM1) or RAM 18
It is a switching circuit for directly passing through or switching the image data stored in the (RAM2) based on the control signal of the controller 22 and outputting it.

The data conversion ROM 20 stores a ROM table in which the values of the previous frame and the current frame are tabulated in order to convert the gradation signal.

That is, the data conversion ROM 20 is an RO in which the values of the previous frame and the current frame are tabulated.
An M table is provided, and the gradation table is converted by referring to this ROM table to speed up the process.
For example, the previous frame is "0" and the current frame is "0"
When it is, the table data is “0”, the previous frame is “2”, and when the current frame is “10”, the table data is “15”. As described above, the display data (gradation signal) of the video signal is not directly applied to the display signal electrode drive circuit 12 of the liquid crystal display panel 11, but is modified and applied using the ROM table. Thereby, the response speed can be increased.

The flip-flop (FF) 21 is a ROM
The display data, which has been data-converted by being looked up from the table, is displayed at a predetermined timing based on a control signal from the controller 22.
Output to 2.

The controller 22 outputs a control signal to each section based on the field discrimination signal input from the synchronization processing circuit 15 and controls each section and the entire apparatus.

FIG. 9 shows the above binary code A / D converter 1.
6 is a circuit configuration when 6 is configured by a 2-bit flash type (normal type) A / D converter.

In FIG. 9, the binary code A / D converter 16 is connected in series between the high-potential reference voltage H and the low-potential reference voltage L, and the reference resistors R1, R2, which express a predetermined reference voltage at each node. R3, R4, comparators 31-33 for comparing the analog input signal with the reference voltage from the reference resistors R1-R4, and the inverted output * X2 of the comparator 32 (where * X indicates the inverted output of X, In the figure, the upper bar represents the same, and so on.) And the output X1 of the comparator 33 take the NAND logic N.
Inverted output * X of AND gate 35 and comparator 31
NA taking the NAND logic of 3 and NAND gate 35 output
An ND gate 36, a latch circuit 37 that latches the output X2 of the comparator 32 according to the clock CK and outputs it as a binary code b1, and a latch circuit 37 that latches the output of the NAND gate 36 according to the clock CK and outputs it as a binary code b0. It is composed of a circuit 38. The input signals are input in parallel to the comparators 31 to 33, and the comparators 31 to 33 compare the input signals with the reference voltage levels of the comparators 31 to 33.

Binary codes b1 and b in this circuit
0 is represented by the equation (1), and the state of the converted data is shown in FIG.
It is indicated by 0.

B1: = X2 b0: = X3 + * X2 × 1 (1) As described above, in the image display device 10 shown in FIG. 8, it is possible to increase the frame frequency for the purpose of improving contrast. Frame memory (RAM17, RA
It is also possible to read the data from M18) at a speed of m times and increase the frame frequency to m times.

[0023]

However, in such an image display device using the conventional speed-up circuit, when the system is assembled, many data buses run on the substrate and are wired on the substrate. The frequency of the data bus tends to increase as the definition of the panel becomes higher, and electromagnetic waves are radiated from the data bus to cause EMI (electromagnetic interface).
erence: Radio noise interference) There is a problem that countermeasures are becoming difficult.

Therefore, an object of the present invention is to provide an image display device which realizes high contrast and high-speed response of a liquid crystal display panel and has less unnecessary radiation.

[0025]

The invention according to claim 1 is
To achieve the above object, an image display is provided with A / D conversion means for converting a video signal into a digital signal and display means for displaying based on the display data converted into a digital signal by the A / D conversion means. A device, wherein the A
The data between the D / D conversion means and the display means is transferred in gray code.

According to a second aspect of the present invention, an A / D conversion means for converting a video signal into a digital signal, a memory for storing display data converted into a digital signal by the A / D conversion means in frame units, Image display including a table for outputting display data corresponding to the display data of the previous frame and the display data of the current frame, which is read out from the memory with a delay, and display means for performing display based on the display data read from the table The device is configured to transfer data between the A / D conversion means and the table by a Gray code.

According to a third aspect of the present invention, there is provided a first aspect of storing A / D conversion means for converting a video signal into a digital signal, and display data of a previous frame converted into a digital signal by the A / D conversion means. A memory, a second memory for storing display data of the current frame, display data of the previous frame read from the first memory, and the second memory
Image display device including a table for inputting the display data of the current frame read from the memory and outputting the display data corresponding to the input data, and a display unit for displaying based on the display data read from the table In addition, the data between the A / D conversion means and the table is configured to be transferred by the Gray code.

The A / D conversion means may be, for example, a Gray code A / D converter for converting an analog video signal into digital display data according to a Gray code format.

The table may be constituted by a look-up table for converting the Gray code into the binary code as described in claim 5, for example.

As described in claim 6, for example, the table is composed of gradation data having a value such that the response speed becomes faster with respect to the input signal when read according to the previous frame and the current frame. May be.

The table is a look-up table for converting a gray code to a binary code, for example, as described in claim 7, and the look-up table is a floor table corresponding to the values of the previous frame and the current frame. The key data may be output.

[0032]

According to the present invention, the gray code A / D conversion means converts the analog video signal into digital image data according to the gray code format, and the data between the A / D conversion means and the display means is gray code. Transferred,
Display is performed based on the display data transferred by the Gray code.

Therefore, since the data bus is in the gray code format and the gray code is used, only 1 bit always changes in successive transitions, so that the frequency component is reduced and the image display device with less unnecessary radiation is provided. realizable.

In the inventions of claims 2, 3, 4, 5, 6, 7 and 8, the display data converted into the gray code is stored in the memory in frame units, and the display data of the previous frame read from the memory is read. Then, the display data of the binary code is read from the table according to the display data of the current frame, and the display is performed based on the display data read from the table.

Therefore, since the gray code is transferred between the A / D conversion means and the table, a high contrast and high speed response of the liquid crystal display panel can be realized, and an image display device with less unnecessary radiation can be realized. .

[0036]

EXAMPLES Examples will be described below with reference to FIGS.

1 to 7 are views showing an embodiment of an image display device, which is an example applied to a high quality liquid crystal display device using a speed-up circuit. In explaining the present embodiment,
The same components as those in the conventional example shown in FIGS. 8 to 10 are designated by the same reference numerals, and the description of the overlapping portions will be omitted.

FIG. 1 is a block diagram of a high quality liquid crystal display device using a speed-up circuit.

In FIG. 1, a liquid crystal display device 40 includes a liquid crystal display panel 11, a display signal electrode drive circuit 12, a scan electrode drive circuit 13, an LC voltage generation circuit 14, a synchronization processing circuit 15, and a gray code A. / D converter 41,
RAM17 (RAM1), RAM18 (RAM2), multiplexer 19, code / data conversion ROM 42,
It is composed of a flip-flop (FF) 21 and a controller 43.

In the liquid crystal display panel 11, a plurality of common electrodes and a plurality of segment electrodes are arranged so as to face each other with a liquid crystal layer in between and arranged in a matrix, and a display signal electrode drive circuit 12 for driving the segment electrodes. And a scan electrode drive circuit 13 for driving the common electrode.

The synchronization processing circuit 15 is a circuit which discriminates an odd field and an even field from the composite video signal in order to invert and drive the polarity of the video signal for each field, and outputs a field discrimination signal.

The Gray code A / D converter 41 converts the analog video signal into image data digitized into 2 bits in accordance with the Gray code format.

The Gray code is one of the binary notations for representing numbers, in which the numerical representation of two consecutive numbers differs only in one digit position. For example, the numbers 0 to 15 in decimal are displayed in binary binary code and gray code as shown in FIG. That is, with Gray code,
1,0011,0010,0110,0111,010
1,0100,1100,1101,1111,111
The numbers 0 to 15 in decimal are displayed as 0,1010,1011,1001,1000. Using the Gray code, adding or subtracting 1 only changes 1 bit. So for binary code:
For example, the transition of 7 ← → 8 simultaneously changes 4 bits, but in the case of the Gray code, only 1 bit always changes in successive transitions.

RAM 17 (RAM 1) and RAM 18
The (RAM2) is a frame memory for temporarily storing image data digitized with a predetermined bit in the Gray code A / D converter 41, in the present embodiment, a 4-bit Gray code. In this embodiment, two frame memories (RAM 17, RAM 18) are provided, and the frame frequency is increased by reading the data once stored in the memory twice at a predetermined timing.

The analog multiplexer 19 is the RAM 1
Image data stored in RAM 7 (RAM1) or RAM 18
It is a switching circuit for directly passing through or switching the image data stored in the (RAM2) based on the control signal of the controller 22 and outputting it.

The code / data conversion ROM 42 is a look-up table for converting a gray code to a binary code and a look-up table (LUT) in which the values of the previous frame and the current frame are tabulated in order to convert the gradation signal. ) Is stored.

That is, as shown in FIG. 4, the code / data conversion ROM 42 is provided with a lookup table (LUT) for speed-up in which the values of the previous frame and the current frame are tabulated, and this lookup table ( It differs from the conventional one in that it has a speed conversion data conversion function for converting a gray scale signal by referring to the LUT) and a function for converting a gray code to a binary code.

The flip-flop (FF) 21 is a lookup table (L of the code / data conversion ROM 42).
The display data code-data converted by the table lookup from UT) is output to the display signal electrode drive circuit 12 at a predetermined timing based on the control signal from the controller 43.

The controller 43 outputs a control signal to each section based on the field discrimination signal input from the synchronization processing circuit 15 and controls each section and the entire apparatus.

As described above, the image display device 40 of the present embodiment.
Uses a Gray code A / D converter 41 in a Gray code format instead of a binary format as an A / D converter, and sets a data bus up to an address input of a code / data conversion ROM 42, which is a data conversion circuit, in a Gray code format. This is different from the conventional example in FIG. 8 in terms of hardware.

Then, the code as the data conversion circuit /
The look-up table (LUT) for speed-up in the ROM 42 for data conversion also has a function of converting from gray code to binary code in terms of software.

FIG. 2 shows the Gray code A / D converter 41.
Is a circuit configuration in the case where is composed of a 2-bit flash type A / D converter, and corresponds to FIG.

In FIG. 2, the Gray code A / D converter 41 is connected in series between the high potential reference voltage H and the low potential reference voltage L, and the reference resistors R1, R2, which express a predetermined reference voltage at each node. AND of R3, R4, comparators 31-33 for comparing the analog input signal with the reference voltage from the reference resistors R1-R4, the inverted output * X3 of the comparator 31 and the output X1 of the comparator 33.
An AND gate 50 that takes a logic, a latch circuit 37 that latches the output X2 of the comparator 32 according to the clock CK and outputs it as a gray code g1, and an AND gate 5
The latch circuit 38 latches the 0 output in response to the clock CK and outputs it as the gray code g0. The input signals are input in parallel to the comparators 31 to 33, and the comparators 31 to 33 compare the input signals with the reference voltage levels of the comparators 31 to 33.

Gray codes g1 and g0 in this circuit
Is expressed by equation (2), and the state of the converted data is shown in FIG.

G1: = X2 g0: = * X3 × 1 (2) As described above, in the image display device 40 shown in FIG. 1, it is possible to increase the frame frequency for the purpose of improving the contrast, and two frames can be displayed. Memory (RAM17, RA
It is also possible to read the data from M18) at a speed of m times and increase the frame frequency to m times.

Next, the operation of this embodiment will be described.

As shown in FIG. 1, the composite video signal is input to the synchronous processing circuit 14, and the synchronous processing circuit 15 discriminates the odd field and the even field from the composite video signal,
A field discrimination signal is output to the controller 43.

In the Gray code A / D converter 41, the analog video signal input through the synchronization processing circuit 14 is converted into 2-bit digitized image data in accordance with the Gray code format, and RAM 17 (RAM 1) and RAM are provided.
18 (RAM2). The image data digitized by the 4-bit gray code by the gray code A / D converter 41 is RAM17 (RAM1) and RAM18.
(RAM2) is temporarily stored in the frame memory (R
The data stored in the AM 17 and RAM 18) is stored at a predetermined timing according to the control signal from the controller 43.
The analog / multiplexer 19 which has been read once and has received the control signal of the controller 22 is switched and output to serve as an address input of the code / data conversion ROM 42. With this, the frame frequency is increased.

In this case, the Gray code A / D converter 41
The data bus from the input to the address of the code / data conversion ROM 42 is transferred in the Gray code format.

A look-up table (LUT) for speed-up in the ROM 42 for code / data conversion is used to perform a table look-up based on the values of the previous frame and the current frame by a code which is input in the Gray code format. That is, the gray code is converted into the binary code and the gradation signal is also converted.

The code / data-converted display data, which is table-looked up by the look-up table (LUT) of the code / data conversion ROM 42, is latched by the flip-flop (FF) 21 and is displayed at a predetermined timing. It is output to the drive circuit 12.

In this embodiment, the gray code A / D converter 41 converts the analog video signal into digital image data according to the gray code format, and the data bus up to the address input of the code / data conversion ROM 42 is gray coded. The format is. Since the Gray code is used, only 1 bit always changes in successive transitions. For example, the states of the data converted by the 2-bit Gray code A / D converter 41 and the binary code A / D converter 16 shown in FIG. 2 are schematically shown in FIGS. The highest frequency components included in g0 and g1 shown in the figure are half of those in the case of b0 and b1 shown in FIG. 2 and 9 are examples of 2 bits,
When the number of bits is larger, further frequency component reduction is realized. FIG. 6 shows an example of 3-bit binary code and gray code data, and FIG. 7 shows an example of 4-bit binary code and gray code encoding. As is clear from this figure, when using the Gray code, it is always 1 for consecutive transitions.
Since only bit changes, frequency components are reduced.

As described above, the image display device 40 of the present embodiment.
Then, among the data buses (A) to (K) of the conventional image display device 10 shown in FIG. 8, the binary code A / D converter 16 is used.
To data conversion ROM 20 (a) to (e)
However, as shown in FIG. 1, the data bus of the image display device 40 is
As shown in (a) to (e), it becomes a gray code bus, and the unnecessary radiation from the data bus on the board is greatly reduced by the frequency component reduction effect of the gray code.

Further, since the segment driver which constitutes the signal electrode drive circuit 12 normally accepts a binary code, a Gray code A / D converter (Gray code A / D converter) is used.
When the converter 41) is used, it is necessary to provide a conversion circuit from the gray code to the binary code at any of the segment drivers, but in the high quality image display device 40 of this embodiment, as shown in FIG. Since the ROM for speed-up (ROM for code / data conversion 42) also serves as this, the code conversion and the data conversion are performed at the same time.
It is sufficient to change the contents of the lookup table (LUT) on M and it is not necessary to newly provide a code conversion circuit.

As described above, the liquid crystal display device 40 of this embodiment includes the liquid crystal display panel 11, the display signal electrode drive circuit 12, the scan electrode drive circuit 13, and the LC voltage generation circuit 1.
4, a synchronization processing circuit 15, a gray code A / D converter 41 for converting an analog video signal into digital data according to a gray code format, a RAM 17 (RAM 1), a RAM
18 (RAM2), multiplexer 19, lookup table for converting gray code to binary code, and lookup table (LUT) storing values of previous frame and current frame for conversion of gradation signal ROM for code / data conversion
2, flip-flop (FF) 21 and controller 4
3, the data between the gray code A / D converter 41 and the code / data conversion ROM 42 is transferred by the gray code, so that high contrast and high speed response of the liquid crystal display panel can be realized, and unnecessary radiation can be realized. An image display device with less power consumption can be realized.

That is, the gray code is used when A / D converting the image data, and the code conversion from the gray code to the binary code is also performed at the same time when the speed-up data is generated by the data conversion circuit using the ROM. Since the speed-up data is output as a binary code to the signal electrode drive circuit 12 that receives the code, in the high-contrast, high-speed response high-quality panel display circuit, between the A / D converter 41 and the speed-up ROM 42. By transmitting the data of the gray code, unnecessary radiation on the board is reduced,
There is an advantage that EMI countermeasures are easy.

In a pocket TV or the like, a flash type A / D converter is often incorporated in the controller from the viewpoint of cost and circuit scale. In the case of the flash type A / D converter, an output higher than that of a certain comparator is output. Are all 0, and the output of comparators below that is 1, so Gray code is more efficient than binary code when encoding those outputs, and the number of gates is smaller, It is also advantageous in terms of circuit scale and speed.

In this embodiment, the liquid crystal display device using the speed-up circuit is used as the image display device, but the present invention is not limited to this, and any kind of device may be used as long as it uses a gray code for transfer data. Of course, it may be applied to an apparatus.

Further, in the present embodiment, the flash type is used for the A / D converter, but it goes without saying that it is not limited to this.

Furthermore, it goes without saying that the circuits and matrixes of the liquid crystal display device, the number of gates, their types, etc. are not limited to those in the above-mentioned embodiments.

[0071]

According to the first aspect of the invention, since the data between the A / D conversion means and the display means is transferred by the Gray code, the frequency component is reduced,
An image display device with less unnecessary radiation can be realized.

According to the second, third, fourth, fifth, sixth, seventh and eighth aspects of the present invention, the data between the A / D conversion means and the table is transferred by the gray code. Since the gray code is transferred between the conversion means and the table, a high contrast and high speed response of the liquid crystal display panel can be realized, and an image display device with less unnecessary radiation can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of an image display device according to the present invention.

FIG. 2 is a gray code A / D of the image display device of the same embodiment.
It is a circuit diagram of a converter.

FIG. 3 is a gray code A / D of the image display device of the same embodiment.
It is a timing chart of the data converted by the converter.

FIG. 4 is a diagram for explaining the configuration of a conversion ROM of the image display device of the same embodiment.

FIG. 5 is a decimal 0 to 15 of the image display device of the same embodiment.
It is the figure which represented the number of with the binary code and the binary code of binary.

FIG. 6 is a diagram showing an example of 3-bit binary code and gray code data of the image display apparatus of the embodiment.

FIG. 7 is a diagram showing data examples of a 4-bit binary code and a gray code of the image display device of the same embodiment.

FIG. 8 is a configuration diagram of a conventional image display device.

FIG. 9 is a circuit diagram of a binary code A / D converter of a conventional image display device.

FIG. 10 is a binary code A / D of a conventional image display device.
It is a timing chart of the data converted by the converter.

[Explanation of symbols]

 11 liquid crystal display panel 12 display signal electrode drive circuit 13 scan electrode drive circuit 14 LCD driver circuit 15 synchronization processing circuit 17 RAM (RAM1) 18 RAM (RAM2) 19 multiplexer 21 flip-flop (FF) 22 source driver 23 gate driver 40 liquid crystal Display device 41 Gray code A / D converter 42 Code / data conversion ROM 43 Controller

Claims (7)

[Claims] 1. A for converting a video signal into a digital signal
An image display device comprising: an A / D conversion means; and a display means for displaying based on display data converted into a digital signal by the A / D conversion means, the A / D conversion means and the display means An image display device, characterized in that data between the two are transferred by Gray code. 2. A for converting a video signal into a digital signal
A / D conversion means, a memory for storing the display data converted into a digital signal by the A / D conversion means in frame units, and a display data of a previous frame and a display data of a current frame which are read out from the memory with a delay. An image display device comprising: a table for outputting display data, and a display means for displaying based on the display data read from the table, wherein data between the A / D conversion means and the table is grayed out. An image display device characterized by being transferred by a code. 3. A for converting a video signal into a digital signal
An A / D conversion unit, a first memory for storing the display data of the previous frame converted into a digital signal by the A / D conversion unit,
A second memory for storing the display data of the current frame, the display data of the previous frame read from the first memory and the display data of the current frame read from the second memory are input, and in response to the input data An image display device comprising: a table for outputting display data, and a display means for displaying based on the display data read from the table, wherein data between the A / D conversion means and the table is grayed out. An image display device characterized by being transferred by a code. 4. The A / D converter is a Gray code A / D converter for converting an analog video signal into digital display data in accordance with a Gray code format, wherein the A / D converter is a Gray code A / D converter. Item 5. The image display device according to any one of items 3. 5. The image display device according to claim 2, wherein the table is a lookup table for converting a gray code into a binary code. 6. The table is composed of gradation data having a value such that a response speed becomes faster with respect to an input signal when read according to a previous frame and a current frame. Alternatively, the image display device according to claim 3. 7. The table is a look-up table for converting from Gray code to binary code,
4. The image display device according to claim 2, wherein the look-up table outputs gradation data according to the values of the previous frame and the current frame.