JPH021812A - Gradation control method, gradation controller, and multigradational display system - Google Patents

Abstract

PURPOSE:To eliminate a brightness irregularity and a flicker by controlling the pulse width of a driving signal to a signal electrode and controlling gradations, and further performing gradation control among the gradations of the pulse width control by frame rate control. CONSTITUTION:The gradation control is performed by a combination of a PWM system and the frame rate control to control the gradations of a display panel consisting of a matrix of signal electrodes and scanning electrodes. For example, a display controller 3 reads image data out of a VRAM (video RAM) 4 under the control of a CPU 1 corresponding to scans on a display surface and supplies gradation data CC corresponding to the read image data to a gradation control circuit 5. The gradation control circuit 5 outputs two-bit gradation data FM1 and FM0 for PWM obtained according to the gradation data CC. The liquid crystal panel 6 consisting of a PWM type liquid crystal drivr and the liquid crystal display matrix is driven, dot by dot, according to the gradation indication data FM1 and FM0.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a gradation control method, gradation control device, and multi-gradation display system suitable for use in gradation control of liquid crystal displays and the like.

``Prior Art'' Conventional liquid crystal displays have only been monochrome and have single gradations, so frame rate control has been required when displaying multiple gradations. With this frame control, one screen is made up of a plurality of frames, and gradations are expressed by controlling the number of frames in which dots are turned on.

However, when the number of gradations is large, the number of frames increases, causing noticeable flicker (flickering of dots) and making the screen difficult to see.

On the other hand, the effective value of the signal that drives the dots is controlled by pulse width control (PWM), and the multi-level 7a+
Display drivers that enable display have been developed in recent years. According to this method, there is no relationship between the number of gradations and the number of frames, so there is no need to increase the number of frames even when displaying multiple gradations, and flicker does not become a problem.

[Problem to be solved by the invention] However, when trying to display 11 levels of 16 gradations in a PWM display driver, for example, 16 types of drive signal pulse widths are required; The width is short, and the drive signal contains many high frequency components. In this case, since the matrix electrodes constituting the display have high impedance and a large floating capacitance 1, the waveform of the drive signal becomes poor in parts where there are many high frequency components. As a result, a problem arises in that, in the display barrel, brightness is uneven between areas with a large amount of high-frequency components and areas with a small amount of high-frequency components.

The present invention was made to solve the above problems, and an object thereof is to provide a gradation control method, a gradation control device, and a multi-gradation display system that are free from uneven brightness and do not cause flicker problems. It is said that

``Means for solving the problem'' - In order to solve the stated problem, the method stated in claim (1)
In one aspect of the invention, in a one-round control method for controlling the gray level of a display panel configured by a matrix of signal 7u poles and scanning electrodes, the method comprises: controlling the pulse width of a drive signal to the signal TTS pole; The present invention is characterized in that, in addition to controlling the level J1q, tone control is further performed between each tone level of this pulse width control by frame rate control.

In the invention according to claim (2), a display panel configured by a matrix of signal electrodes and scanning electrodes;
Based on the supplied gradation data, the signal 7T! The pulse width of the drive signal to the poles is controlled, and thereby the multi-order, Jll,
A pulse width control driver that performs 1 drive, and a frame 2-, late control [1] between each gradation of this pulse width control driver.
The present invention is characterized in that it further comprises a data converting means for creating gradation unit TL data for multi-level translation and conversion based on manual gradation data indicating the gradation of the display surface.

In the invention as set forth in claim (3), there is provided a tally counting means for counting the weighted clock set at the output timing or a, and a count value of the clock counting means and a frame rate control [1-1]. The pulse width of the drive signal supplied to the display panel is changed based on the applied gradation data J', +4' and the pulse width J! , 1 means =1-.

In the invention described in claim (4), rj includes claim (2).
), the data conversion means in the gradation control device described in I
The Yj notation non-display panel dots are divided into frequency digits F11, and the frame whose display is turned on by the frame rate control [1-] is configured so that it does not shift to each (1γllJ fi). In the inventions described in 5) and (6), different types of phases are further combined to reduce flicker.

In the invention described in claim (7), there is provided an image memory in which at least one screen worth of image data is stored, and the image data in the image memory is read out, gradation data corresponding thereto is outputted, and the image data is displayed. A display controller that outputs a control signal, a display panel configured by a matrix of signal 7Ji poles and scanning electrodes, and a display panel that controls the pulse width of the drive signal to the riQ signal electrode based on the supplied gradation data, As a result, a pulse width control driver that performs multi-gradation driving, and gradation data that further increases the number of gradations between each gradation level of this pulse width control driver by frame rate control, based on the gradation data output by the display controller. It is characterized by comprising a data conversion means for creating data, and a central processing unit for controlling the display controller.

In the invention as set forth in claim (8), the signal electrode and the running j'! In a gradation control method for controlling the gradation of a display panel configured by a matrix of ET [f poles, the gradation is controlled by controlling the pulse width of the drive signal to the signal electrode. The process of further controlling the gradation between each gradation of the width control by using the frame rate control roll, and n) changing the dots on the display panel to 1!
Divide into the losing phase and display the seven frames that are turned on by the frame rate control. 1 small matrix of
A plurality of small 7 trixes with different types of phases used are arranged adjacently to form a 2nX2m (n,
The method is characterized by composing a large matrix (where m is an integer) and nurturing the process of arranging the positions of each line in this large matrix so that they are all older.

``Function'' Since frame rate control and tone control using PWM are combined, the number of tone control steps using each method can be reduced to 14 degrees, which is smaller than in the case of a single method. Therefore, compared to the case where only frame rate control is used, the number of frames is reduced, thereby reducing flicker. Furthermore, the pulse width of the drive signal can be made longer than when only PWM is used, thereby making it possible to lower the frequency component of the drive signal. therefore,
When driving a high-impedance display panel, there is no change (rounding) in the drive waveform, and no uneven brightness occurs.

"Embodiments" Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(l: Principle of Operation) First, the principle of gradation control in this embodiment will be explained.

■Operating principle for multi-gradation control In this embodiment, gradation control is performed by a combination of the PWM method and frame rate control. That is, a multi-gradation PWM liquid crystal display driver controls four gradations (a 2-bit input PWM liquid crystal display driver is used), and between each gradation by this PWM, a 5-frame frame rate control is used to control 51 to 4 gradations. I am trying to control ＠凋. Here, an example of a dot drive pattern using five-gradation frame rate control is shown in FIG. 9.

Here, FIG. 1O shows the relationship between the floor IT data CCr0J to rFJ and the display state of dots in each frame when the method described in "-" is followed. In this figure, ■
, ■, ■, ■ indicate the gradation rOJ, rlJ, r2J "3" by the PWM display driver, and if the above gradation j numbers ■, ■, ■ are in the frame number column, the corresponding dot is It is displayed in the corresponding gradation in that frame.

Furthermore, when the gradation number is ■, the dot is not displayed in that frame. As can be seen from the figure, for the gradation data CCrOJ ~ "5", P'v
In combination with the VM display driver's level 140 and frame rate control, 5L's level 8 control is performed, and the gradation data CCr5j ~ "Δ" is controlled by the PWM display driver's gradation ■. ,■ and the frame rate control, and for the gradation data "A j~r F J, the combination of the gradation ■, The gradation is controlled by .

■Flicker reduction is achieved by using predefined frame rate control to reduce flicker.
In order to do this, the phases of adjacent frames in the frame rate control are shifted. Specifically, each dot is grouped into four phases, and frame 12 rate control is performed individually for each phase.

Here, if one (hikawa is l\, r3.C, and D, then the relationship between Rf, river, B, C, and ri is as follows:
Phase B and phase B are 180 degrees apart, and phase C and phase il
L and D are 180 degrees older than each other. Also, position i]A
, B and the average of phases C and D are deviated from each other by 180°. For example, when the brightness is l (when only one frame is turned on), the timing of turning on the dots in each phase is set as shown in FIG.

Here, the gradations in each phase are AO, AlA2,...
- When expressed as BO, [31, I32, . . . , the on timing of the dot at luminance "1" and "2" is as shown in FIG.

'' Each of the two consecutive phases A-D is set to 4 on the display screen as shown in FIG. 13. As shown, the phases ABCDΔ
BCD...The 0th line is the place (eye B A
I) Cr3 A DC... The first line is the phase D CI3 A I) CB A... The second line is the phase CD A 13 Cl) ΔB
The third lines are configured in the order of... The following lines also have the same phase configuration as the 0th to 3rd lines, and the above relationship is repeated.

According to the double phase configuration, the display screen is divided into a 2 x 2 dot block consisting of phase to phase B, and a 2 x 2 dot block consisting of phase C and phase difference. Moreover, -Each brozok is fm, )'! 'Divided into two taroubs with the I position reversed. If this is expressed as plotter No. 1 [3, Iε8013.013' as shown in the figure, these blanks will appear in the scanning direction as blocks E13. 112 alternately around 1 of OB, Er3Or3..., and block O13'lΣB is placed in the row below.
', OB-, r': +3- are lined up.

Then, a screen is formed in which these columns are arranged alternately in the retrieval direction. The reason for the above-mentioned phase arrangement is that the i4 tangent l and the f are arranged alternately as much as possible.
Kota. /), and the flicker is significantly reduced (1 mo).

In Figure 13, D is the dot count, and L is the dot count.
C indicates line count.

① - Operation principle when combining the operations ① and ② to control a two-hit human-powered PWM liquid crystal display driver.

First, let the manual gradation data of the PNVM liquid crystal display driver be PMI (2' bit) and F'MO (2° bit), and frame f7j between these and gradation data CC.
FIG. 14 shows the relationship between phase and phase. This FIG. 14 corresponds to FIG. In the corresponding part, it matches the number in circles (i.e., floor J, j1 number).

For example, in the third frame of the gradation data CCr8j, FMl is "1" (21st - 1), and F to 10 are "0".
(2.

Pi-== 0), so the (:1'i is [
-2'', which coincides with the numerical value [■'' in FIG. 1O of the corresponding upper part.

1) ~■\1 LCD display driver input floor 7J, jl data F! ~
11. After creating FMO, set 1]\■M and frame rate control [Knoll's IL1] as shown in Figure 10.
Floor by joining; 1. ',] can be controlled.

Then, apply this to the other phase r3. The same process is performed for C and D, and a gradation pattern corresponding to the (i'7. position) of the dot on the display surface is selected.

Here, gradation data FMI is obtained from floor J1-1 data CC.

The method for creating an FMO will be explained. In this embodiment, the following method is used to perform this data conversion efficiently and at high speed.

First, the gradation patterns AO, AI, A2, . . . for each phase defined as described above have the following relationships as can be seen from FIG.

, to 0 ・-A5. AI ・-A 4 , A
2 ・-A 3 ... ... (1) (Here, - indicates reversal, and in Fig. 14 it is represented by bar [-1.) Also, other (keHIB, C, The same relationship as in I) is established. Here, regarding the phase (1
), the gradation J, l pattern at each gradation is represented by the code PIIC.

Next, floor 7J7J pattern Δ0. Δ1. A2. -A.O.

A1. -A2... If there is a "-" (that is, in the case of a complement), the 22nd digit is set as "!", and if it is not a complement, the corresponding digit is set as "0", and furthermore, in the numerical part of the gradation pattern, A binary number is defined in which 1-Oj, rlj, and r2j are directly converted into digits of 21.2°.

Then, convert this binary number into F for the gradation data FMI.
Sl2. FSI 1. I”SIO (2221.2° each
For eaves i), gradation data FMO, FSO2, FSO
l, FSoo (22.2+, Q"1, respectively). Then, if these binary values are FSl and Fso, these are IOJ, Il, as shown in Figure 1.1.
There are six values: l, r2j, r4J, and r5J "6".

Then, as shown in Fig. 14, h+I F S
The combination of l and Fso corresponds one-to-one to the floor 1 data CC. Is that a floor? Decode the JM data CG (directly FS1.FS(), and from now on
, -1 data I"Ml, FNlo are read out and supplied to I-) W~1 liquid crystal display driver data 1"16, frame rate control [1-le and l) W Is it possible to display the 16th floor with the M combination?

This is the Jl (principle of operation) of this embodiment.

(Configuration of 2nd embodiment) Next, a specific example (1) will be explained.

FIG. 1 is a block diagram showing the overall configuration of the embodiment.

In the figure, I is a CPU (solid processing unit) that controls each part of the device, and 2 is a memory that is used by the CPU I and consists of a program area and a work area in which one gram of data is stored. 3 is CP Ull, 7) Under the control, the image data in vn\M (hideorum) 1 is read out against the screen of the display tube, and the read image data is read out from the corresponding floor. , Jl', I data CC:
, 1ηHJ, +4 control 11 circuits 5. The gradation control circuit 5 follows the gradation control method shown in FIG. , I'-taF~11.1-"MO(
(See Figure 1.1) Output Tenro 9, 6 is a liquid crystal panel made of (1") WM type (k crystal driver and liquid crystal display 7 tritas). 12~i
1. Drive up each dot according to FTh, 10. Here, FIG. 2 is a block diagram showing the configuration of the liquid crystal panel 6. In the figure, 10 is a liquid crystal display matrix consisting of a signal 1u pole and a scanning electrode, and the signal is driven by a segment driver 11, and the scan electrode is driven by a common driver 12.The segment driver 11 is supplied with gradation instruction data F'MIF'MO from the floor DAI control circuit 5, and also has data for display. Various control signals are supplied.Here, these control signals will be explained.

Noft clock SCK second floor E data FMI, FMO,
This data is sequentially stored in registers in the segment driver 11 according to SCK.

Horizontal synchronizing signal HSYNC: A signal indicating the start of a scanning line. When the segment driver 11 is supplied with the horizontal synchronizing signal 1 (SYNC), it starts driving the signal electrodes.

Weighted clock WC, T CK/segment driver 1
1 outputs a drive signal whose pulse width is changed by J and -1 based on the values of the floor IA [data FMI, FMO and the count value of the weighted clock WGTCK.

Here, the operating waveform diagram of the segment driver 11 is shown at the third Δ
The circuit configuration of the output stage is shown in FIG. 3B.

The circuit shown in FIG. 3F3 is an output circuit of the segment driver 11, and this output circuit is used for the 0th to mth signals 'i'.
They are provided corresponding to the u-poles, respectively. Note that the circuit indicated by the dashed line in FIG. 31 is the J (plate part), and the parts other than the dashed line are installed corresponding to the six signal electrodes.

In the output circuit shown in FIG. 313, Frisobuch C)
-7 output signal of F F l or signal tu as a drive signal
It is designed to be output to l-jg. I wanted to,
) ν while flip-flop 12F1 is set
A moving signal is output.

In addition, gradation data P M to be applied to the valley signal electrode
The IP MO is then taken into the register LITEG at the noft clock as shown in FIG. 3B. This register fl E G
The 0th and 1st bit outputs of
IO, OItl l is supplied to one input terminal. W
CTfl is a ternary counter that counts the weight clock WGTCK, and the 0th bit, 1j, and
The bit output signal is the OR gate OI”tlO, 0fll
+ is supplied to the input end of each curved blade. These or gates 0
Each output signal of R10Orjll, horizontal synchronization signal HS Y
The inverted signal of NC and the inverted signal of the insect clock WGTCK are ANDed by ant game 1-AN3. Then, the output signal of this AND gate AN3 is supplied to the set input terminal of the flip-flop FF1, and when it rises to a "1" signal, the flip-flop I? F1 is set and a drive signal is output. Also, flip-flop FF
A horizontal synchronizing signal 1-r S
Y N C (j1)

In the two-legged configuration, when the horizontal synchronizing signal ISYNC is output as shown in Figure 3A (a), the flip-flop FF 11 is set, and the drive signal is then set to 11. Regardless of the state, it will be in a 1゛stop state. Then, the gradation data PM1. When FMO is "0", a "0" signal is always supplied to one terminal of each of Orb I711 and Orb I2, and the 11th 0th bit output of the ternary counter WCTfl is supplied to both terminals. These or gates 0fll 1. OR+2 never outputs a "1" signal to "(". Therefore, AND gate AN3 or "l"
It does not output a signal, and the flip-flop F'FI
is not set. That is, as shown in FIG. 3A (d), no drive signal is output.

Gradation data FM1. When FMO is rlj, a "1" signal is supplied to one input terminal of OR gate 0R10.

Furthermore, 211. 'l1 market clock WG i'
At Iji time L2 where CK is output, the counter \V
A "1" signal is output from the first bit output terminal of Ci'H, and an "l" signal is supplied to the input terminal of the (crested edge) of OR gate 0R11, 01t12. The respective output signals of both become "l" signals.Therefore, the second side weight clock W G ′r
Ant gate AN3 at the time when CK h<falls
A "1" signal is output from the flip-flop FFI, and the flip-flop FFI is set. The set state of the flip-flop FFI continues until time t4 when the next horizontal synchronization signal HSYNC is output.

Gradation data FM1. When FMO is "2", a "1" signal is supplied to one input terminal of ORGAME 1-0R11,
Furthermore, l fl, “pl-th weight clock ~■GTC
At time L2 when K is output, an "l" signal fJ% is supplied from the 0th hit output terminal of the counter WCTR to the input terminal of the OR gate 0R10. Therefore, at time t2, a "1" signal is output from both output terminals of OR gates 01111.01 and 12, and as a result, at the time when the first side weight clock W G T CK falls, a signal of "1" is output from AND gate ΔN3. A "1" signal is output, and the free-turn-flow-turn F Fl is set. This cent state is the same as the above case, when the next horizontal synchronization signal rises (
Since the drive signal continues until time L4), the drive signal is output from time L1 to +4.

When the gradation data FMI and FMO are "3", regardless of the output of the counter WCTR, the OR gate 0rt11.0
Since the "1" signal is supplied to both input terminals of the 1112, the AND gate ΔN3 immediately outputs the "1" signal at the fall of the horizontal synchronization signal that rose at time 1, and the flip-flop PFI is set. and output as a drive signal.

According to the above circuit, the counter Wc ′r
The count value of rt is the gradation signal FM1. A drive signal is output from when it becomes the complement of FMO. As a result, the values of the gradation data FMI and FMO correspond to the output time of the drive signal, so that the contrast of the display surface corresponds to the gradation data.

Furthermore, in this embodiment, as shown in FIG. 3A (b), the weighted clocks WGTCK are not output at regular intervals. This is because the relationship between the contrast of the liquid crystal display and the effective value of the drive signal is not linear. Therefore,
In order to create an accurate linear relationship between the gradation data and the contrast on the actual display screen, depending on the characteristics of the liquid crystal display,
The interval of the weighted clock WGTCK is shifted to correct the effective value at each gradation level.

For example, the relationship between the liquid crystal display and the effective value of the drive signal is as shown in Figure 3C. In this characteristic, if the effective value is divided into equal intervals and the gradation is set, the effect of the nonlinear part As a result, the gradation data and the actual brightness do not match.

Therefore, in this embodiment, as shown in the figure, the magnitude of the effective value at each gradation is made different, in order to solve the problem described above. In this case, since the intervals between each gradation divided by the magnitude of the effective value are further controlled by the frame rate control, the interval between each gradation is a straight line hlt by the frame rate control. In FIG. 3C, the portions indicated by dots in the dashed-dotted line are the gradations of linear interpolation by frame rate control.

Furthermore, in this embodiment, the output interval of the weighted clock W G'I''OK output by the display controller 3 is set to 1% Q by a parameter set in the display controller 3. Therefore, the 1 degree interval between gradations ■ and ■ by PWM, the luminance interval between ■ and ■, and the luminance interval between ■ and ■ (T:
= can be set. As a result, [) ~ V M
The slope of the linear interpolation portion (the slope of the one-dot diagonal line in FIG. 3C) can be set for the group fi of the gradation data placed between each gradation (1" 1.).

In general, there is no linear relationship between brightness and visual sensitivity. Therefore, it is necessary to set the slope of the linear interpolation part by visual inspection for each system flj, or it is possible to set the slope freely like two feet. It is extremely suitable to be able to do this.

Next, the gradation control circuit 5 will be explained.

FIG. 4 is a block diagram showing the configuration of the gradation control circuit 5. As shown in FIG. In the figure, 20 is a gradation pattern generator, and 11[i mentioned gradation patterns At, A2.131. [
32, CI, C2, DI, B2 (see FIG. 12). Specifically, as shown in FIG. 5, 5flJi(7) D 9 If7') Sofa a7' DFF F l- are connected in cascade in a loop shape.
D F F5 and 4 or games 1-ORI~OR4
It consists of A vertical synchronizing signal VSYN and an initial reset signal IN1'! from the display controller 5 are supplied to the clock terminals and recent terminals of these D-type flip-flops DFF I to DFF5. ' are supplied respectively.

” According to the two-leg configuration, ■] type flip-flop D
I;" The Q output signal of F5 becomes a "1" signal in the initial state, and every time this "L" signal is supplied with the vertical synchronization signal VSYN,
l -D I” F2- D F F 3 →D F
F 4-1) [? It circulates in a loop called F5. Therefore, l) the output signal of the type flip-flop DI"I'I is "1" according to the 0th frame, and
It becomes "0" in one frame, and becomes the ora corresponding to the floor: JA] pattern Δl. Also, in the same way, ■] type flip-flop D [;' F 2 I) l
) Each output signal of F 3 D F B4 becomes a signal corresponding to the floor pattern CI, +31, I) I.

Also, as can be seen from FIG. 12, if the logical sum of the 1.1 pattern Δl and B1 is taken, the gradation pattern A2 is obtained, so the output signal of the OR gate 0rtl corresponds to the 1-bit pattern A2. becomes. Similarly, orgate or
't2. Or't3. Each output signal of OR4 has one gradation pattern 132. C2, corresponds to I)2.

The following is the configuration of the gradation pattern generator 20.

Next, 21, not shown in FIG. 4, is a data conversion circuit.
The gradation data CC is converted into data FS1. Convert to FSo. The configuration of this data conversion circuit 21 is shown in FIG. In FIG. 6, DIEcI is a decoder that decodes 4 hits of data, and OI't 6 0
R70R80R9 is a decoder I) which encodes the output signal of I> CI and generates data F'SOO, F'5 (11
, FSIOFSII is created. In this circuit, no conversion processing is performed on the data Fs12.

This is because the data FS12 is the same as the gradation data CC3, so the 1st level data CC3 is directly converted to the data PS.
This is because it can be used as 12.

Next, 22 shown in FIG. 4 is a phase identification circuit, which identifies which river the dot to be displayed belongs to. As shown in FIG. 7, this phase discrimination circuit 22 is composed of three exclusive knobs or outputs EXOR1 to EXOR3, and is supplied with a signal 1) from the display controller 5.
Co, 1) Perform logical operations on CI, LCO, and LCI. Signals DCO1DCI are the 0th dot counters, respectively.
bit and first hint signal, signal LCO.

LCI are the output signals of the 0th hit and the 1st hit of the line counter, respectively. Therefore, the signal DCO is inverted between "1" and "0" for each dot, and the signal [7CO is inverted between "l" and "0" on the l line I7N. Also, signal 1
) CI inverts "1"/"0" in units of 2F, and signal LCl inverts "1"/"0" in units of 2 lines. By performing logical operations on these signals, the position (•II) can be identified as follows.

Assuming that the output signal of the exclusive or gate EXOR1 is the signal 13LS, and the output signal of the exclusive knob or gate EXOrt2 is the signal EO9,
The relationship between these signals and phases A-D is as shown in the following table, as is clear from the relationship between dot count DC and line count LC shown in FIG.

Table 1 ``Biped);! As can be seen from 1, the signal [3L S and EO
Which phase is identified by the combination of 9 values.

Next, 23 and 24 shown in FIG. 1 are each gradation data F
This is a gradation data selection section that outputs MO and FMl. The gradation data selection section 23 uses signals BLS, EO8 and data F.
Based on SOO, FSOI, and FSO2, the gradation pattern for each location is selected, and the gradation data selection unit 24
LS, EO9 and data F'SI O, FS 11
．． A gradation pattern at each phase is selected based on FS l 2 (CC3). Gradation data selection section 23.2
The configuration of No. 4 is as shown in FIG.

First, the gradation data JA selection section 23 is composed of a selector 30 and a selector 31, as shown in FIG. 7, and the selector 30 has a 4-bit input terminal.
, 30b, 30c, and 30d. The first bit input terminal of each select section 30a, 30b, 30c30d receives the gradation pattern A1.131. CIDI is supplied respectively,
Also, the second bit input terminal has the floor, 'JMI pattern A2
．． r32. C2 and D2 are each supplied. The 0th bit and 3rd input terminal of each selector 30a, 30b, 30c30 (j are grounded.
The 0th and 1st hit control terminals of 0 each have data FSOO.
and FSOI are provided. Therefore, the data FS
00, FSOI (direction is rlJ, r2J), the valley select sections 30a to 30d select the gradation patterns A1 to DI and A2 to D2 supplied to the first pit input terminal and the second bit input terminal, respectively. .

Further, when the values of the data F S 00 and FSOI are "0", the select sections 30a to 30d select the grounded 0th bit input terminal. In this case, a pattern that is always "0" has been selected, that is, the floor...
This means that lAI patterns AO to DO have been selected. In this way, the selection process in the selector 3'0 is performed by the data F.
This is a process of selecting a gradation pattern corresponding to the value of SOO1FSol. Next, the selector 31 has 8 bit input terminals, and the signals from the Y output terminals of the select sections 30a to 30d are supplied to the 0th to 3rd bit input terminals, and the signals from the Y output terminals of the select sections 30a to 30d are supplied to the 0th to 3rd bit input terminals, and
A signal from the output terminals of the select sections 30a to 30d is supplied to the seventh input terminal. Signals EO9 and BLS are supplied to the 0th and 1st hit control input terminals of the selector 31, respectively, and data FS()2 is supplied to the 752 hit input terminal.
Therefore, when the value of the signal FSO2 is "1", one of the 4th to 7th bits is selected, and when the signal FSO2h<"0", the 0th to 7th bits are selected. 3
Select one of the bit input terminals. Here, signal F'
When SO2 is "1", the gradation pattern is shown as a complement, and in this case, the 4th to 7th bit input terminals are selected and the main output terminals of the select sections 30a to 30d are selected. The function of signal FSO2 corresponds to the selection operation of selector 31. Also, the signal EO
If 9,l13LS does not show phase A (see Table 1),
The selector 31 selects the 0th gradation pattern to which the phase A gradation pattern is supplied.
Or select the first bit input terminal. Similarly signal IE
When O8,BLS indicates phases B, C and Select the 3rd and 7th human power inputs, respectively. As described above, the phase of the signals EO3 and BLs matches the phase of the gradation pattern selected by the selector 31.

The floor data selection section 24 is composed of select sections 32a to 32 (one focus input selector 32 for selecting "j" and an 8-bit manual selector 33). has the same configuration as the 1-1 data selection section 23. However, data FSIO1FSII is supplied to the 0th and 1st hit control input terminals of the selector 32, and the 0th and 1st data selection portions of the selector 33 1, 2nd bit human power controller 11, respectively (No. 3 EO8, 13LS and data 1?S l 2
(CC3) is supplied. Therefore, the output signal of the selector 33 is 1.5 gradation data [2
M1 becomes a pattern corresponding to the digit (1) and the gradation by -4° (see FIG. 14).

(Operation of Embodiment 3) Next, the operation of this embodiment will be explained by forming R/ in -53.

Yo, 3゛, display controller; uh, V IN
The image data in A\11 is scanned sequentially through χ1, and 1) 11x data CC is output to the gradation control circuit 5. The gradation jλ1 control circuit 5 controls the M
] Data FM1. Create F'MO.

Now, when creating gradation data F M l and F M O for the O-th dot of line 0, which is not shown in FIG.
II according to the values of the above signals LCI, O and r) CI, O
11] or Δ is identified by the +1J identification circuit 22. As a result, the 4-gradation data selection iNB 23, 24 (7) cell L/lid 3I is shown in FIG.
, :33 h< Select the input terminal to which the pattern to the common phase is supplied. Then, the floor Jhj data CC is converted into data FSO1FSt by the data conversion circuit 20, and the selectors 30, 31, L and 32, .
33 corresponds to the gradation (AO-A3, -Δ0 to -A, 2
) Select and measure the pattern. As a result, position +'llΔ
Gradation data of the θth frame corresponding to the relevant floor, Jl, + FM 11? MO is output from selectors 31 and 33, respectively, and sent to segment driver +1 (see Figure 2) (J
l, to be provided. Next, the gradation data F M l and F M O for the first tosoto of the 0th line are created in the same manner as for the two pairs. However, the phase of this dot is B (see FIG. 13). Thereafter, gradation data FMI and FMO corresponding to the phase are created in the same manner one after another. Then, the O-th line gradation data FM l and FMO created as described above are provided to the segment driver 111 j' in accordance with the shift clock SCK.

FIG. 8 shows a timing diagram of each signal when displaying the 0th frame.

Figures (a) and (b) show the vertical synchronizing signal and horizontal open 1υ (signal), respectively, and (c) shows the output timing of the one-bamboo tone data F Ml and P M O during each horizontal display M interval. In addition, (d) to (g) in the same figure show 1.
This is an enlarged view of the time in U diagrams (A) to (C). As shown in the figure, the Oth
The line gradation data FMI and FMO are transmitted to the segment driver 11 (see Fig. 2) by the shift clock SGK.
The signals are taken in and output all at once to the signal [[] at the falling time tlo of the next horizontal synchronizing signal 14 S Y N C after the rise of the vertical synchronizing signal V S Y N C. At this time, the controller 12 (see FIG. 2) drives the 0th common electrode, thereby causing the θth
The 0th line in the frame is displayed. Also,
FIGS. 8(H) and 8(S) are diagrams in which the time is further expanded, showing the shift clock SCK and the gradation data FM1. It shows the relationship of FMO.

Thereafter, each line is displayed in the same manner as above, and the display of the 0th frame ends. Next, after outputting the vertical synchronization signal VSYNC, the display controller 3 scans the image data in the VRAMd again, and
It is output to the gradation control circuit 5 in the same manner as in the frame case.

The floor 1 week control circuit 5 processes floor:y;, +data FM1. Create F'MO,
Since the vertical +01 signal ■SYNC is output,
The pattern output from the gradation pattern generator 20 is the same for the first frame. And the first
Floor E data FMI and FMO for the frame are created, and <PWM gradation display is performed based on this. Thereafter, each frame is displayed in the same manner, and when the display of the fourth frame is completed, the display of one screen is completed. As a result, as shown in FIG. 1O, 16 gradations are performed using the combination of PWM and frame rate control.

In addition, in the case of "1-Record", since the frame ray control was performed by providing four phases, the effect of extremely reducing flicker can be obtained.

In this case, if flicker is not a big problem, frame rate control using two phases may be used.

Furthermore, the number of frame rates shared between the frame rate and the PWM is not limited to the embodiment, but is up to 45. For example, ri ~ ■ ~ 1 5th floor, +7. I, frame rate control 1-(J-ru te 41 all, ;17.1
< 3 divisions) or PWNl on the 9th floor 2-1,
3rd floor +7 with frame rate control. I (divided into two) may be used.

Furthermore, the frame rate control [l
- may be used in combination. For example, 4 divisions, 3
It is possible to periodically perform frame rate control such as division or two-division. In this way, by mixing frame rate controls with a small number of divisions,
The flicker reduction effect can be further improved.

Further, by combining with tiling or the like, it is possible to create more gradations.

Further, the embodiment described in 2 can be modified as follows.

For example, in addition to the phases A-D used in the embodiment, a new phase E is set, and this phase E is switched to a different phase for each predetermined line. That is, as shown in FIG. 15(a), the phase difference and the position 411E are switched in units of two lines.

In the figure, the out-of-phase portions of the second and third lines are converted to phase E. Here, when gradation levels 1-1'' and [2-1 for phase E are shown, FIG. 16 (
As shown in a) and (b), in the gradation 1] rlJ (gradation pattern El), the display is turned on in the fourth frame, and in the gradation "2" (gradation pattern E2), the display is turned on. ,
The display is turned on in the first and fourth frames.

In order to perform the above-mentioned phase setting, for example, the 17th
A selector 35 as shown in the figure is provided, and as shown in FIG.
Type Flip Fronob Install OR gate 01"+5 that takes the logical sum of DFF5 and DFF2, and this or game 1-
The output signal of O+75 is used as the gradation pattern E2. And selenium l- of selector 35! :i 35
Gradation pattern DI, l) 2 at each 0th input terminal of a, 35b
is supplied, and gradation patterns El and E2 are supplied to the respective first hit input terminals of the select sections 35a and 35b. Further, the first pit signal LCI of the line counter is supplied to the control input terminal of the selector 35 ("), and each output signal of the select sections 35a and 35b is divided into DI and D2-, so that the select section 30d shown in FIG. to the first and second humans.

-, when displaying the 4th nth and (4n+1)th lines (n is an integer of O, l, 2, etc.),
Signals 1 and C1 become “0” and gradation patterns D1 and D2
become the signals 1)l- and D2-, respectively. As a result, the 4th n
, in the (4n→-1)th line, a phase-shifting pattern is used as in the multiplex embodiment (Fig. 15(A)).
(See the O1 first line shown in ). Also, the (4n+2)th
, when the (4n+3)th line is displayed, the signal LCI is “
1”, and the gradation patterns E1 and E2 are respectively signal DI-
, D2'. As a result, the (4n+2)th and (4th
In the n+3) line, phase E is used instead of phase shift. (See the second and third lines shown in FIG. 15(a)).

Further, when the signal LC2, which is the second bit signal of the line counter, is supplied to the control input terminal of the selector 35 shown in FIG. 17, the phase is switched every four lines by the same operation as described above. That is, the phase D h< is used for the nth to (n+3) lines, and the phase E is used for the (n+4) to (n+7) lines (see the 0th to 7th lines shown in FIG. 15 (b)). jjj().

In this way, if the phase difference and the phase E are switched and used for each predetermined line, one frame will be composed of five types of phases. When a frame is composed of five types of phases, the on/off of dots due to each phase is averaged out more than when four types of phases (Δ~D) are used41, and the effect of eliminating flicker is greater. A score of 11 points was obtained.

In addition, in the above modification, the matrix composed of the different order of the first dots was 4 x 4 or 4 x 8 dots (see Figure 15 (a) and (b)), but the types of 11 phases were further changed. Please try to further expand the control range to increase the phase arrangement and change by 1+P.

For example, FIG. 18 shows an example in which a phase F is further added and a matrix of different phases is combined into 8×8 dots. Here, the phase F is set so that the on-timing of the display is different from other phases, and is the 19th phase.
In the figure, the gradation pattern A of each phase in the case of gradation "2"
2 to F2 are shown.

Further, the circuit that realizes the phase arrangement shown in FIG. 18 may be configured as shown in FIG. 20 for phase "2", for example. In the figure, 40 is a selector, which has a two-hit manual selection section 40a. The first bit input terminal of this select section 402L has a gradation pattern A2.
is supplied, and the first bit input terminal has the floor, tool 1 pattern F
2 is supplied. At the control input terminal of the selector 10, there is an AND gate 42 which takes the AND of the second bit output signal of the line counter and the second hint output signal of the dot counter.
output signal is provided. Then, the selection section 5103
The output signal is supplied as signal A2- to the second input terminals of select sections 30a and 32a shown in FIG. 41 is a select section 41 that selects the input end of 2 hits (i).
It is a selector with a and 1", and an exclusive OR game 1...13 which takes the exclusive OR of the second bit output signal of the line counter and the second hit output signal of the dot counter at the control input terminal. Output (No. 3 is supplied. And,
The output signal of the selector 11a is the signal D2-, which is not shown in FIG.
Supplied to the input end.

According to the above configuration, the fourth to seventh lines in the phase arrangement shown in FIG. 13 (generally speaking, 4 to (4 + 3):
is an integer greater than or equal to 1) is switched to phase pattern F2, and at the same time, phase pattern D2 on the same line is switched to phase pattern E2. Therefore, the phase pattern arrangement shown in FIG. 18 is obtained.

Next, the effect of configuring the phase arrangement matrix shown in FIG. 18 will be explained using the case of gradation [2] as an example.

Now, if we focus on the 0th line, the on/off states of the 0th to 3rd dots are as shown in FIG. 21(a). In the 0th frame, the dots of phases A and I) are on, in the 1st frame, only the dots of phase B are on, and in the 2nd frame, the dots of phases A and C are on, and the 3rd dot is on. In the frame, phase B and D dots are on, and in the fourth frame,
Only the phase C dot is turned on. As a result, the 0th to 4th
In the frame, sequentially 2f1711, 1, 2, 2
Each time, one dot turns on, and the contrast ripple for these dots is 50%.

Furthermore, the ripples for the 4th to 7th donots of the 0th line are also 50%, similar to the above. Then, if we focus on the 4th line, we can see the O-3rd line and the 4th-3rd line.
Regarding the 7th dosoto, the ripple is 50% as in the case of double series (Figure 21 ([1) to (d))
reference).

Next, for the same dot numbers on the 0th and 4th lines, l'? As shown in FIG. 21(E), the number of dots that are off for each frame is 3.3.4, 3°3 or 3.3.3 in the order of the 0th to 4th frames. ，
It becomes 3.4. As can be seen from this, the ripple of the contrast is 25% for tosotos with the same number. Furthermore, the 4th to 7th tots,
The 4th to 7th dots are dots that make up one frame on the same screen, so the number of dots on for each frame that makes up one screen is the sum of the number of L-metal dots on, and the 21st As shown in the figure (f), it becomes G, 6,7 6°7. Therefore, the contrast ripple is about 14
%.

In this way, if the display block (matrix) is configured with the same groove structure as shown in FIG. 18, the frame rate can be controlled to be low, and flicker can be significantly reduced. Be able to do it.

Note that the valley line is composed of ・1 (2) of the phase of Tatsumi, and the fire 5 of 1-rubu vJtsuk is not 1≦iJ in the example shown in Fig. 18, but the number of phases and their arrangement. Depending on how
Of course, it is also important to make people even better.

[Effects of the Invention] As explained in 4, according to this invention, the signal set (・
1j! and the scanning electrode matrix (114/:!Indication, the floor, s, '.j to control the floor.
J! , I 1+ control method, if the gradation is controlled by controlling the pulse width of the drive signal to the li'j 5O signal 1 [B], then the interval between each gradation 1 of the Jl/s width control is Frame rate con!・C! - further sub-control 19 times by means of the above method;
:Since the filter device and system are configured, there is no unevenness in brightness.
In addition, a score of 111 was obtained indicating that there was no flicker problem.

Further, as described in claims (4), (5), (6), and (8), the F-soto in the display panel is 'fSJ. By dividing the display into several phases and using frame rate control to shift the frame on which the display is turned on for each phase, flicker can be significantly reduced. In this case, the number of divided phases is (MoQ), and the divided phases can be combined appropriately to construct any block. Therefore, depending on the system etc., the most appropriate phase can be selected. Can you change it to defeat and bu[Jtsuku form?

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the entire embodiment of the present invention (1vt configuration), FIG. 2 is a block diagram showing the configuration of the liquid crystal panel 6 used in the same embodiment, and FIG. 3 is a block diagram showing the operation of the liquid crystal panel 6. 4 is a block diagram showing the configuration of the gradation control circuit 5 in the same embodiment; FIG. 5 is a circuit diagram showing the configuration of the gradation pattern generator 20 in the gradation control circuit 5; Figure 6 shows +M of the data conversion circuit 21 in the gradation control circuit 5.
7 is a circuit diagram showing the configuration of the phase discrimination circuit 22O, J,
8 is a timing chart showing the overall operation of the same embodiment, and FIG. 9 is a diagram showing the frames and gradations in which dots are turned on in the frame rate control. Figure 1O is a diagram showing the relationship between P'iV fVl, frame rate control data, and dot contrast in each frame in the same example. Figure 11 is a diagram showing the relationship between the phase A- In case of gradation rlJ in D, 1ζ
12th section 1 is a diagram showing frames where dots are on for each phase A-D in the case of gradations rlJ and r2J. A front view showing the phase of the display surface, and FIG.
Gradation data PMI, FM supplied to PWM driver)
15 is a front view showing the arrangement of phases in a modified example of the same embodiment; FIG. 16 is a diagram showing the gradation pattern of each phase in the modified example. , Fig. 17 is a circuit diagram showing the configuration of a switching circuit that switches the gradation pattern in the same modification, Fig. 18 is a front view showing the phase arrangement in another modification, and Fig. 19 shows the gradation in the same modification. FIG. 20 is a circuit diagram showing the configuration of a switching circuit for switching gradation patterns in the same modification, and FIG. 21 is a diagram for explaining the ripple reduction effect in the same modification. be. 1...CPU (central processing unit), 3...Display controller/roller, 4...VIIAM (image memory), 5...gradation control circuit (data conversion) means), 6...Liquid crystal panel, 10...Liquid crystal display matrix (display panel), 11...Segment driver (pulse width control driver). Figure 1

Claims (8)

[Claims] (1) In a gradation control method for controlling the gradation of a display panel constituted by a matrix of signal electrodes and scanning electrodes, the gradation is controlled by controlling the pulse width of a drive signal to the signal electrode, and , a gradation control method characterized in that gradation control is further performed between each gradation level of this pulse width control by frame rate control. (2) A display panel composed of a matrix of signal electrodes and scanning electrodes, and a pulse width that controls the pulse width of the drive signal to the signal electrodes based on the supplied grayscale data, thereby performing multi-grayscale driving. a width control driver; and a data conversion means for creating gradation data for further increasing the number of gradations between each gradation level of the pulse width control driver by frame rate control based on input gradation data indicating the gradation level of a display surface. A gradation control device comprising: (3) A clock counting means for counting weighted clocks whose output timing is arbitrarily set, and a drive signal supplied to the display panel based on the count value of this clock counting means and gradation data subjected to frame rate control. A gradation control device comprising: pulse width modulation means for modulating the pulse width of the gradation control device. (4) The data conversion means is characterized in that the dots on the display panel are divided into a plurality of phases, and the frame in which the display is turned on is shifted for each phase by frame rate control. gradation control device. (5) The data converting means is configured to convert two data that are adjacent to each other on the same line.
4 dots consisting of 1 dot and 2 dots adjacent above or below the above 2 dots are set as 1 group, and the group is formed by 1st and 2nd phases. A first group is configured such that adjacent dots have different phases, and a second group is configured with third and fourth phases and is configured such that adjacent dots have different phases. 5. The gradation control device according to claim 4, wherein the gradation control device is divided into two groups, and these groups are arranged alternately on the display surface. (6) The data conversion means also sets phases other than the first to fourth phases, and switches a specific phase among the first to fourth phases to the other phase for each predetermined line. The gradation control device according to claim 5, characterized in that: (7) an image memory in which at least one screen worth of image data is stored, and reading out the image data in this image memory;
a display controller that outputs gradation data corresponding to the gradation data and a display control signal; a display panel configured of a matrix of signal electrodes and scanning electrodes; A pulse width control driver that controls the pulse width of a drive signal to thereby perform multi-gradation driving, and gradation data that further increases the number of gradations between each gradation of this pulse width control driver by frame rate control. What is claimed is: 1. A multi-gradation display system comprising: a data converter that generates data based on gradation data output by a display controller; and a central processing unit that controls the display controller. (8) A gradation control method for controlling the gradation of a display panel constituted by a matrix of signal electrodes and scanning electrodes, characterized by comprising the following steps (a), (b), and (c). gradation control method. (a) The process of controlling the gradation by controlling the pulse width of the drive signal to the signal electrode, and further controlling the gradation between each gradation of this pulse width control by frame rate control (b) The display The process of dividing the dots on the panel into multiple phases and shifting the frame at which the display is turned on by frame rate control for each phase (c) Arranging two of the phases so that they are not adjacent to each other A large matrix of 2n x 2m (n and m are integers) is constructed by arranging a plurality of small matrices that are composed of a small matrix of 2 dots and suitably different types of phases are used, and a large matrix of 2n x 2m (n and m are integers) is constructed. The process of making the phase alignment of each line different