JP3526471B2 - Multi-tone display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a liquid crystal display device and an electroluminescence (EL) display device, and more particularly to a multi-gradation display device capable of multi-gradation display.

[0002]

2. Description of the Related Art In recent years, in display devices typified by liquid crystal display devices, not only high definition but also multi-gradation display have been demanded. For each display pixel, a thin film transistor (hereinafter,
It is abbreviated as TFT. ) And the like are taken as an example of an active matrix type liquid crystal display device, each pixel electrode, a counter electrode facing the pixel electrode, and a liquid crystal held between the pixel electrode and the counter electrode. An image display is performed by holding a predetermined potential between the electrodes that are composed of the composition and that form one display pixel for one frame (F) period.

In such a liquid crystal display device, in order to prevent the deterioration of the liquid crystal composition, the voltage applied to the pixel electrode in order to realize the above-described multi-gradation display, for example, 64 (2 ⁶ ) gradation Since it is necessary to perform AC driving, the voltage level of 64 × 2 is required.

However, preparing 64 × 2 voltage levels increases the power consumption of the IC that constitutes the drive circuit,
Alternatively, it is not a preferable method in terms of cost. Therefore, as another method for realizing multi-gradation display, the voltage level of the gradation voltage applied to each pixel electrode is not made different according to the display gradation, but the voltage application period, that is, There is known a so-called pulse width modulation method in which the pulse width is changed to realize display corresponding to each gradation. However, such a method also has a problem that the display circuit is complicated and the control is difficult in multi-gradation display such as 64 (2 ⁶ ) gradation.

[0005]

As another method for solving the above-mentioned problems, one display period is formed by setting a plurality of consecutive frame (F) periods as one cycle, and a frame is turned on within one display period. (F) A so-called frame rate control (FRC) method is known, which realizes multi-gradation display by controlling the period. Also, for example, Japanese Patent Laid-Open No.
In addition to the above-mentioned FRC method, there are no.
There is also known a method in which a plurality of adjacent display pixels are used as one control unit and the frame (F) periods that are turned on between the adjacent display pixels are made different to prevent the occurrence of flicker.

According to such an FRC system, it is possible to eliminate the need for a plurality of gray scale voltages, and it is also possible to eliminate the disadvantages of the pulse width modulation system described above. However, it is necessary to further increase the number of frame (F) periods constituting one display period in order to realize further multi-gradation display by such an FRC method. For example, 64 (2 ⁶ )
If an attempt is made to realize multi-gradation display such as gradation, problems such as the multi-gradation display being visually unrecognizable and the occurrence of flicker are caused as the number of frame (F) periods increases. .

The present invention has been made in response to the above technical problems, and it is possible to realize multi-gradation display which does not cause flicker and which does not impair the display quality. It is intended to provide a display device.

[0008]

According to a first aspect of the present invention, there is provided a multi-gradation display device for displaying a color image by selecting a predetermined voltage level according to input multi-gradation display data. Table for at least red, green, and blue colors
A display panel in which a plurality of display pixels are arranged , red,
A first gradation that generates a first gradation pattern in which one display gradation is obtained in m (m is a positive integer of 2 or more) frame period with the array of the display pixels including each color of green and blue as one control unit. Corresponds to the pattern generation circuit and one of red , green and blue
A second gradation pattern generating circuit for generating a second gradation pattern for obtaining one display gradation in an m frame period with the array of the plurality of display pixels as one control unit; and the first gradation pattern.
Screen generation circuit or the second gradation pattern generation circuit is selected.
Selection circuit and, electrostatic the multi gradation display data of said predetermined that
If it corresponds to the pressure level , the corresponding predetermined voltage level
Selected and output the multi-gradation display data to the predetermined
If it does not correspond to the voltage level of
Selection control means for selecting and outputting one of the predetermined voltage levels based on the output of either the selected first gradation pattern generation circuit or the selected second gradation pattern generation circuit, It is characterized by having.

According to a second aspect of the invention, the multi-gradation display data according to the first aspect is k (k is a positive integer greater than 2).
It is characterized by being a bit digital signal.
The invention according to claim 3 is characterized in that the multi-gradation display device according to claim 2 is provided with a gradation voltage generating circuit for supplying a voltage level lower than 2 ^{k + 1} .

[0010]

[0011]

[0012]

[0013]

[0014]

According to the multi-gradation display device of the present invention, as described above, one display is performed in the m (m is a positive integer of 2 or more) frame period with the plurality of first arranged display pixels as one control unit. The gradation is controlled so as to be obtained, and the display pixels are controlled so that one display gradation is obtained in the m frame period with the plurality of second arrayed display pixels as one control unit.

As described above, by adopting a configuration in which control can be performed by two or more different control units, the optimum control can be selected according to the form of the display image, and this enables excellent control with a small number of voltage levels. It is possible to realize gradation display.

Further, in a display device which has at least red (R), green (G) and blue (B) display pixels and is capable of color display, red (R), green (G) and blue ( By controlling the pixel unit including each display pixel of B) as one control unit or controlling each color pixel group as one control unit, an optimal multi-gradation display is realized with a small number of voltage levels. be able to.

[0017]

EXAMPLE As an example of the present invention, 64 (2
⁶ ) An active matrix liquid crystal display device capable of gradation display will be described as an example with reference to the drawings. As shown in FIG. 1, this liquid crystal display device (1) is a color display device in which one display pixel is composed of three display pixels of red (R), green (G), and blue (B). , (640 x 3) rows x 4
A liquid crystal panel (11) having display pixels arranged in a matrix of 80 columns, an X driver (101) and a Y driver (201) electrically connected to the liquid crystal panel (11), and these X drivers A liquid crystal controller (251) for controlling the (101) and the Y driver (201), and a floor for converting 6-bit gradation display data input from the outside into 4-bit gradation display data and outputting it to the liquid crystal controller (251). Tonal signal conversion circuit (3
01) and the gradation voltage (V0, V1, V2 ... V15) consisting of 16 square wave voltages whose polarities are inverted with respect to the reference voltage every frame (F) period as shown in FIG.
And a gradation voltage generating circuit (501) for outputting to (101). In this embodiment, the frame inversion drive is taken as an example, but in order to prevent the occurrence of flicker and the like, line inversion drive and the like may be combined with the frame inversion drive. In this case, one frame (F) period When a square wave voltage whose polarity is inverted with respect to the reference voltage every time and which is also inverted with respect to the reference voltage every predetermined horizontal scanning line period is used as the gradation voltage (V0, V1, V2 ... V15). good.

This liquid crystal panel (11) is of a so-called active matrix type, and is composed of three primary colors of R (red), G (green) and B (blue) in stripes parallel to the signal line (15). It is equipped with a color filter (71). The liquid crystal panel (11) includes a TFT (31) for each display pixel electrode (21).
Is provided. Scan line (13) connected to TFT (31)
A scanning pulse (VG) is supplied from a Y driver (201) composed of a shift register to the TFT (3
1) becomes conductive. As a result, the gradation voltage from the signal line (15) connected to the X driver (101) is written to the display pixel electrode (21) through the TFT (31), and the liquid crystal capacitance (Clc)
And a storage capacitance (Cs) provided in parallel with the liquid crystal capacitance (Clc) by the storage capacitance line (51) is held for one frame (F) period to display an image.

The X driver (101), as shown in FIG.
A shift register (111) that sequentially transfers input 4-bit gradation display data based on a shift clock (CK) and a start pulse (ST), and a decoder (113) that converts the output from the shift register (111). , A selection circuit (115) for selecting and outputting one of 16 gradation voltages (V0, V1, ... V15) according to the output of the decoder (113), and a latch for holding this output for a predetermined period. Circuit (117).

Next, the gradation signal conversion circuit (301) of the liquid crystal display device (1) will be described. This gradation signal conversion circuit
Reference numeral (301) corresponds to 6-bit gray scale display data inputted from the outside with any of 16 gray scale voltages (V0, V1, ... V15) prepared in the gray scale voltage generation circuit (501). Control circuit to convert 4-bit gradation display data (331)
Is equipped with.

Further, in the gradation signal conversion circuit (301), the input 6-bit gradation display data is supplied to the gradation voltage generation circuit (5
01) corresponds to the grayscale voltage prepared in advance, the converted 4-bit grayscale display data is output without arithmetic processing, and the input 6-bit grayscale display data is the grayscale voltage generation circuit. When the gray level corresponding to the intermediate voltage level of the gray scale voltage prepared in advance in (501) is corresponded, the 4-bit gray scale display data is arithmetically processed to output the intermediate gray scale, and then output. And an arithmetic processing circuit (351) that operates.

The arithmetic processing circuit (351) is a dot-unit gradation control circuit for expressing gradation corresponding to an intermediate voltage level of gradation voltages prepared in advance in the gradation voltage generating circuit (501). (315) and the pixel unit gradation control circuit (325) are connected via a selection circuit (341).

The dot unit gradation control circuit (315) includes a red (R) dot unit gradation pattern generation circuit (311a) and a green (G) dot unit gradation pattern generation circuit corresponding to each display pixel color.
(311b) and blue (B) dot unit gradation pattern generation circuit
(311c) 3 dot unit gradation pattern generation circuit (311c)
It has a), (311b), and (311c). The pixel unit gradation control circuit (325) includes a pixel unit gradation pattern generation circuit (321).

Red (R) dot unit gradation pattern generation circuit
(311a) shows the display pixel area of the liquid crystal panel (11) as shown in FIG.
As shown in (b), 36 display pixels (6 with a square shape composed of red (R) dots in 6 rows and 6 columns adjacent to each other are formed.
(* 6 matrix) is used as a red (R) dot control unit, and one display screen is divided into blocks of 80 rows by 240 columns for control. The green (G) dot unit gradation pattern generation circuit (311b) is also connected to the red (R) dot unit gradation pattern generation circuit (311b).
As in the case of 11a), 36 display pixels (6 × 6 matrix) in a quadrangular shape composed of green (G) dots in 6 rows and 6 columns adjacent to each other in the display pixel area of the liquid crystal panel (11) are green. (G)
As a dot control unit, one display screen is divided into blocks of 80 rows × 240 columns for control. The blue (B) dot unit gradation pattern generation circuit (311c) also forms a quadrangle shape composed of 6 rows and 6 columns of adjacent blue (B) dots in the display pixel area of the liquid crystal panel (11). This display pixel (6 × 6 matrix) is used as a blue (B) dot control unit, and one display screen is divided into blocks of 80 rows × 240 columns for control. The dot unit gradation pattern generation circuits (311a), (311b), (311c) control each dot control unit with a continuous 6 frame (F) period as one display period.

Therefore, in each gradation pattern for realizing one display gradation, one table composed of 36 pieces of gradation auxiliary data corresponding to each dot control unit is, for example, (a) to (f) in FIG. As shown in FIG. 6, each dot unit gradation pattern generation circuit (3
11a), (311b), and (311c) store such gradation patterns for five gradations, respectively.

A dot-unit gradation control circuit (315)
Is a dot-unit gradation pattern generation circuit (311a), (311b),
A 6-frame counter for selecting one of the first to sixth tables constituting each gradation pattern of (311c), a 6-line counter and a 6-column counter for obtaining gradation compensation data corresponding to display pixels from the one table And a first designating circuit (313) consisting of

A pixel unit gradation pattern generating circuit
(321) shows the display pixel area of the liquid crystal panel (11) in FIG.
As shown in (a), 36 display pixels (6 × 6 matrix) forming a quadrangular shape with 6 rows and 6 columns adjacent to each other, that is, 12
Pixel control unit is pixel, and one display screen is 80 rows x 2
The control is divided into blocks of 40 columns.

Therefore, each gradation pattern for realizing one display gradation corresponds to each pixel control unit 36.
One table consisting of individual gradation auxiliary data is, for example, as shown in FIG.
As shown in (a) to (f) of 4, four display gradations are realized by six sheets, and the pixel unit gradation pattern generating circuit (321) has 5 gradations of such gradation patterns. Minutes are remembered.

A pixel unit gradation control circuit (325)
Is a 6-frame counter that selects one of the first to sixth tables forming each gradation pattern of the pixel-unit gradation pattern generation circuit (321), and obtains gradation compensation data corresponding to a display pixel from the one table. Second designated circuit (32 line counter and 6 column counter for
3) is provided.

The dot-unit gradation pattern generation circuits (311a), (311b), (311c) and the pixel-unit gradation control circuit (3
25) can be composed of a ROM or a RAM, and in this embodiment, each is composed of a ROM.

According to the gradation signal conversion circuit (301) thus constructed, the 6-bit gradation display data inputted from the outside is converted into the 4-bit gradation display data by the gradation control circuit (331). In addition, when the 6-bit gradation display data corresponds to the gradation voltage prepared in advance in the gradation voltage generation circuit (501), the converted 4-bit gradation display data is calculated by the calculation processing circuit (351). Outputs to the X driver (101) via the LCD controller (251) without processing, and
When the bit gradation display data corresponds to the gradation corresponding to the intermediate voltage level of the gradation voltage prepared in the gradation voltage generation circuit (501) in advance, one of the ones selected by the selection circuit (341) is selected. Arithmetic processing of 4-bit gradation display data converted so that an intermediate display gradation is expressed in the arithmetic processing circuit (351) based on the gradation compensation data of the gradation pattern control circuits (315), (325). Then, the 4-bit gradation display data that has been subjected to this arithmetic processing is output to the X driver (101) via the liquid crystal controller (251).

The gradation signal conversion circuit (301) detects whether the 6-bit gradation display data input from the outside is text data and then controls the gradation of the 6-bit gradation display data. A text data detection circuit (361) for outputting to the circuit (331) is provided. When the 6-bit grayscale display data is text data, the 6-bit grayscale display data is 16 grayscale voltages (V0, V1, ... V15) prepared in advance in the grayscale voltage generation circuit (501). 4) converted by the gradation control circuit (331) regardless of whether or not
A first selector circuit (371) and a second selector circuit (381) for outputting a bit gradation display signal to the liquid crystal controller (251) without performing arithmetic processing in the arithmetic processing circuit (351)
It has and. In this embodiment, text data such as characters or graphic display data such as ruled lines are collectively referred to as text data.

A specific method for realizing the intermediate display gradation used in the liquid crystal display device (1) of this embodiment will be described below. In a liquid crystal display device in which gray scale voltages (V0, V1, ... V15) composed of 16 square wave voltages are prepared, it is possible to select 16 gray scale voltages (V0, V1, ... V15) by selecting one of the gray scale voltages. It is possible to display gradation images. Therefore, in this liquid crystal display device (1), a gray scale voltage (V0, V1, ... V15) composed of 16 square wave voltages is used, and
The following display operation is performed in order to realize the image display of four gradations.

1 / middle of one gradation voltage (Vi) (i = 0,1,2, ..., 14) and another gradation voltage (Vi + 1) adjacent thereto.
In order to realize 6 gradations, the gradation voltage (Vi) is applied for 5 frame (F) periods in the continuous 6 frame (F) periods, and the gradation voltage (Vi + 1) is applied for the remaining 1 frame (F) period. ) Control to select. One gradation voltage (Vi) (i = 0,1,2, ..., 1
4) and another gray scale voltage (Vi + 1) adjacent thereto, in order to realize an intermediate 2/6 gray scale, in 4 consecutive frames (F), 4 frames (F) are Adjusted voltage (Vi
) For the remaining 2 frame (F) periods.
) Control to select. One gradation voltage (Vi) (i =
0,1,2, ..., 14) and other gradation voltages (Vi + 1) adjacent to this
In order to realize an intermediate 3/6 gradation, the gradation voltage (Vi) is applied during the 3 frame (F) periods during the continuous 6 frame (F) periods, and the remaining 3 frame (F) periods during the 3 frame (F) periods. The gradation voltage (Vi + 1) is controlled to be selected. One gradation voltage (V
i) (i = 0,1,2, ..., 14) and another 6/6 gray scales in order to realize an intermediate 4/6 gray scale between another gray scale voltage (Vi + 1) adjacent thereto In the F) period, the grayscale voltage (Vi) is selected in the 2nd frame (F) period, and the grayscale voltage (Vi + 1) is selected in the remaining 4th frame (F) period. In order to realize an intermediate 5/6 gradation between one gradation voltage (Vi) (i = 0,1,2, ..., 14) and another gradation voltage (Vi + 1) adjacent thereto, In the continuous 6 frame (F) periods, the gray scale voltage (Vi) is selected in one frame (F) period, and the gray scale voltage (Vi + 1) is selected in the remaining 5 frame (F) periods.

As described above, the combination of the control of the frame (F) period and the 16 gradation voltages (V0, V1, ... V15) theoretically realizes 91 gradations as shown in FIG. can do. In this embodiment, 6 gray scales are selected from among 91 gray scales by selecting 64 gray scales with a particularly preferable display state.
A four-gradation image display is realized.

For example, in this embodiment, 1/91 between the gray scale voltage (V0) and the gray scale voltage (V1) is selected from 91 gray scales.
6 gradations (theoretical gradation 2 in FIG. 5) and 5/6 gradations (theoretical gradation 6 in FIG. 5), 1/6 between the gradation voltage (V1) and the gradation voltage (V2) The gradation (theoretical gradation 8 in FIG. 5) is used for display, and 1/6 gradation and 5/6 gradation between the other gradation voltage (Vi) and the gradation voltage (Vi + 1) Not used for display.
This is because only 1/6 gradation or 5/6 gradation is used only in an area where it is difficult to visually recognize gradation because flicker may be visually recognized depending on a display image.

Next, each gradation pattern used in this embodiment will be described. The selection of each gradation pattern in this embodiment is considered based on the concept of the magic circle. The magic circle is configured, for example, by assigning numbers 1 to N ² to each matrix of an N × N matrix of N rows and N columns so that the sum of the numbers in each row and each column is equal. It is something. In addition, the complete magic circle is configured by being assigned so that the total numbers are equal in each diagonal.

Each gradation pattern of this embodiment is composed of a 6 × 6 matrix, and a matrix in which a perfect magic circle does not exist [(4r + 2) × (4r + 2) matrix: r is a positive number not less than 1] Therefore, it is constructed based on the magic circle.

In FIG. 6, in the 6 × 6 matrix magic circle, 1 is assigned to the matrix to which the numbers 1 to 6 are assigned,
2 is assigned to the matrix assigned the numbers 7 to 12.
1 is assigned to the matrix assigned the numbers 3 to 18.
Assign 4 to 2 in the matrix assigned the numbers 9 to 24
3 is assigned to the matrix assigned the numbers 5 to 31.
6 shows auxiliary magic circles each having 6 assigned to a matrix to which numbers 1 to 36 are assigned.

Each gradation pattern is selected as follows by using the auxiliary magic circle constituted by the magic circle in this way. If one display pixel realizes 1/6 gray scale between the gray scale voltage (Vi) and the gray scale voltage (Vi + 1) adjacent to the gray scale voltage (Vi), 1 in 6 consecutive frame (F) periods. The gradation voltage (Vi + 1) may be selected only during the frame (F) period, and the gradation voltage (Vi) may be selected during the other five frame (F) periods. Therefore, as shown in FIG. 7A, the gradation compensation data {1} is allocated to the matrix to which the numeral 1 in FIG. 6 is allocated, and the gradation compensation data {0} is allocated to the other matrixes. The first table of the six tables for realizing 1/6 gradation of the tonal pattern is configured. Further, as shown in FIG. 7B, the gradation compensation data {1} is allocated to the matrix to which the numeral 2 in FIG. 6 is allocated, and the other gradation compensation data {0} is allocated to the first gradation. 6 to realize 1/6 gradation of pattern
In the second table in the table, gradation compensation data {1} is allocated to the matrix to which the numeral 3 is allocated, and gradation compensation data {0} is allocated to the other ones, and 1/6 gradation of the first gradation pattern The third table of the six tables for realizing the above is assigned the gradation compensation data {1} to the matrix to which the number of 4 is assigned, and the other is assigned the gradation compensation data {0} and the first gradation pattern is assigned. The fourth table out of the six tables for realizing the 1/6 gradation is assigned the gradation compensation data {1} to the matrix to which the numeral 5 is assigned, and the other is assigned the gradation compensation data {0}. The 5th table out of the 6 tables for realizing 1/6 gradation of the 1st gradation pattern, the gradation compensation data {1} is further allocated to the matrix to which the numeral of 6 is allocated, and the others are gradation. Assign compensation data {0} Sixth table in the 6 tables for implementing the 1/6 gradation of the first gradation pattern Te the constituting respectively.

By sequentially repeating the first to sixth tables configured in this way, with 6 frame (F) periods as one display period, the gray scale voltage (Vi) and the adjacent voltage are adjacent to the 6 frame (F) periods. It is possible to realize 1/6 gradation between the gradation voltage (Vi + 1) and the gradation voltage.

When one display pixel realizes 2/6 gradation between the gradation voltage (Vi) and the gradation voltage (Vi + 1) adjacent to the gradation voltage (Vi), 6 consecutive frames (F). 2 during the period
Select the gradation voltage (Vi + 1) only during the frame (F) period,
In the other four frame (F) periods, the gray scale voltage (Vi) may be controlled to be selected. Therefore, the gradation compensation data {1} is added to the matrix to which the numbers 1 and 2 shown in FIG. 6 are assigned.
, And gradation compensation data {0} for the others,
The first table of the six tables for realizing 2/6 gradation of the first gradation pattern is configured. Further, the gradation compensation data {1} is assigned to the matrix to which the numbers 3 and 4 shown in FIG. 6 are assigned, and the gradation compensation data {0} is assigned to the other matrixes, and the 2 / 6th floor of the first tone pattern is assigned. A second table among the six tables for realizing the key is constructed. Similarly, the third to sixth tables out of the six tables for realizing 2/6 gradation of the first gradation pattern are configured.

Similarly, one display pixel has a gradation voltage (Vi
) And the gradation voltage (Vi + 1) adjacent to
First to sixth tables (see FIG. 8) for realizing 6 gradations, one display pixel is on the 3 / 6th floor between the gradation voltage (Vi) and the gradation voltage (Vi + 1) adjacent thereto. First to sixth tables (see FIG. 9) for realizing the gradation, one display pixel displays 4/6 gradations between the gradation voltage (Vi) and the gradation voltage (Vi + 1) adjacent thereto. 1st to 6th tables (Fig.
0), one display pixel realizes 5/6 gradation between the gradation voltage (Vi) and the gradation voltage (Vi + 1) adjacent thereto (see FIG. 11). ) Respectively.

The gradation patterns shown in FIGS. 7 to 11 configured as described above are stored in the red (R) dot unit gradation pattern generating circuit (311a) according to this embodiment.

A gradation pattern formed based on another magic circle includes a green (G) dot unit gradation pattern generating circuit (311b) and a blue (B) dot unit gradation pattern generating circuit (311b).
11c), respectively.

Furthermore, a gradation pattern formed based on another magic circle is used in the pixel unit gradation pattern generation circuit (32
1) is also remembered. FIG. 12 shows a gradation pattern for expressing 2/6 gradation stored in the green (G) dot unit gradation pattern generating circuit (311b), and FIG. 13 shows a blue (B) dot unit gradation pattern generating circuit. 2/6 stored in (311c)
The gradation pattern for expressing the gradation is stored in the pixel unit gradation pattern generation circuit (321) in FIG.
Each gradation pattern for expressing gradation is shown.

Next, the operation of the liquid crystal display device (1) of this embodiment will be described in detail. First, a case will be described in which fine gradation control is performed based on a dot unit gradation pattern generation circuit (315) for red (R), green (G), and blue (B) suitable for displaying moving images and the like.

As shown in FIG. 1, a switching signal (SW) is input from the outside so as to control the intermediate gradation based on the dot unit gradation control circuit (315), and the gradation control is performed based on this. The circuit (331) is set to control the selection circuit (341) to selectively output the grayscale compensation data from the dot unit grayscale pattern control circuit (315).

For example, in the first frame (F) period, as shown in FIG. 15, red (R) display pixel (1, 1) is displayed.
When 6-bit gradation display data {000000} corresponding to the first gradation which is not text data is input to
The bit gradation display data {000000} is input to the gradation control circuit (331) via the text data detection circuit (361). This 6-bit gradation display data {000000}
Is controlled by the gradation control circuit (331) for 16 gradation voltages (V
4-bit gradation signal {00 corresponding to 0, V1, ... V15)
00}. Further, the input 6-bit gradation display data {000000} is not text data, and the converted 4-bit gradation signal {0000} is guided to the arithmetic processing circuit (351) by the first selector circuit (371). Get burned.

The 6-bit gradation display data {000000} for displaying the first gradation is the gradation voltage (V0) out of the 16 prepared gradation voltages (V0, V1, ... V15).
0), the converted 4-bit gradation signal {0
000} is not processed by the arithmetic processing circuit (351), the second selector circuit (381), the liquid crystal controller (251)
It is output to the X driver (101) via the. Then, by the X driver (101), this 4-bit gradation data {000
0}, the gradation voltage (V0) is selected and output.

In the first frame (F) period,
When displaying the third gradation which is not the text data on the green (G) display pixel (1, 8), the 6-bit gradation display data {000010} corresponding to the third gradation is passed through the text data detection circuit (361). Input to the gradation control circuit (331).
This 6-bit gradation display data {000010} is converted into 16 gradation voltages (V0, V1) by the gradation control circuit (331).
, ... V15) 4-bit gradation signal {0000}
Is converted to. The input 6-bit gradation display data is not text data, and the converted 4-bit gradation signal {0000} is guided to the arithmetic processing circuit (351) by the first selector circuit (371). Then, 6-bit gradation display data {00001 for displaying the third gradation
0} are 16 prepared gradation voltages (V0, V1, ... V)
Since the display gray scale does not correspond to any of (15), the converted 4-bit gray scale signal {0000} is calculated by the arithmetic processing circuit (3
In 51), the following arithmetic processing is performed.

As shown in FIG. 5, the third gradation corresponds to 2/6 gradation between the gradation voltage (V0) and the gradation voltage (V1). In addition, the dot unit gradation pattern control circuit (31
The green (G) display pixel (1, 8) corresponds to the grayscale compensation data of the first line and the third column in the green (G) dot unit grayscale pattern.

Therefore, the first designation circuit (313) is used to
2 gray scale compensation data {0} of the first line and third column of the first table shown in (a) of FIG. 2 is extracted, and the selection circuit (341)
Is output to the arithmetic processing circuit (351) via. And 4
The bit gradation signal {0000} is supplied to the green (G) dot unit gradation pattern generation circuit (311b) by the arithmetic processing circuit (351).
The gradation compensation data {0} from is added, and the 4-bit gradation data {0000} from the arithmetic processing circuit (351) is added.
Is output to the X driver (101) via the liquid crystal controller (251). Then, by the X driver (101),
Based on the bit gradation data {0000}, the gradation voltage (V
0) will be selected and output.

Similarly to the first frame, the second frame is the third frame.
If gradations are to be displayed, the gradation compensation data {1} of 1 line and 3 columns shown in FIG.
The 4-bit grayscale data {00
01}, the gradation voltage (V1) is selected and output.

Similarly in the third to sixth frame (F) periods,
If gradations are to be displayed, the gradation compensation data shown in FIGS. 12C to 12F are subjected to addition processing by the arithmetic processing circuit (351), and display is performed based on this.

As described above, if the same third gradation is displayed during the first to sixth frame (F) periods, the second and fifth frames (F) during the continuous 6 frame (F) periods. The grayscale voltage (V1) is selectively output during the period, and the grayscale voltage (V0) is selectively output during the first, third, fourth, and sixth frame (F) periods, and the grayscale voltage (V0) and the grayscale voltage (V1) are A third gray scale corresponding to 2/6 gray scale is expressed.

By the way, in a moving image or the like, 6-bit gradation display data input to each display pixel is different in each frame (F) period, for example, a blue (G) display pixel (1,
In 8), 6-bit gradation display data corresponding to a display gradation different from the third gradation may be input in the second frame (F) period.

In such a case, the display operation may be performed based on the input 6-bit gradation display data, regardless of the display operation in the previous frame (F) period. this is,
Even if there are gradations that cannot be fully expressed by 16 gradation voltages (V0, V1, ... V15), it is difficult to visually distinguish the gradations in a moving image, which is a problem. Almost never.

As described above in detail, in this embodiment, 1
It is possible to realize 64-gradation display by using 6 gradation voltages (V0, V1, ... V15). Moreover, in the liquid crystal display device (1) of this embodiment, 36 display pixels for each color are set as one gradation unit, and halftone display is controlled based on a gradation pattern composed of magic circles. Therefore, even if all display pixels represent the same gradation, flicker or the like does not occur, and particularly moving images can be displayed well.

In the above embodiment, the case where 6-bit gradation display data which is not text data is input has been described.
The case where the bit gradation display data is input is as follows.

For example, a case where 6-bit gradation display data {000011} which is text data and corresponds to the fourth gradation is input to the red (R) display pixel (1, 1) will be described.

Input 6-bit gradation display data {00
0011} is input to the gradation control circuit (331) via the text data detection circuit (361). This 6-bit gradation display data {000011} is converted into 16 gradation voltages (V0, V1,
.. is converted to a 4-bit gradation signal {0000}.

This 6-bit gradation display data {00001
1} is the prepared 16 gradation voltages (V0, V1, ...
V6) corresponds to an intermediate gray scale that does not correspond to V15), that is, 3/6 gray scale which is between the gray scale voltage (V0) and the gray scale voltage (V1), and this 6-bit gray scale display data {000011} is text data. Therefore, the text data detection circuit (36
Based on the output of 1), 4-bit gradation signal {0000}
Is directly output from the first selector circuit (371) to the liquid crystal controller (251) via the second selector circuit (381) without passing through the arithmetic processing circuit (351). And the X driver
From (101), the gradation voltage (V0) is selected and output based on the 4-bit gradation data {0000}.

As described above, the liquid crystal display device of this embodiment
In (1), whether the input 6-bit gradation display data is text data or not is determined by the arithmetic processing circuit (351). Therefore, for the display of text data such as characters in which flicker is likely to occur, the grayscale voltage corresponding to the grayscale close to the input 6-bit grayscale display data is selected based on the 4-bit grayscale signal. Therefore, even if a 6-bit gradation display data group in which text data and non-text data are mixed is input, a good display image without flicker can be obtained.

Next, in the liquid crystal display device (1) of this embodiment, a case will be described in which gradation control is performed based on the pixel unit gradation pattern control circuit (325) suitable for display in OA applications and the like.

First, a pixel unit gradation pattern control circuit
As shown in FIG. 1, a switching signal (SW) is externally applied to the gradation control circuit so that gradation control is performed based on (325).
Enter in (331). As a result, only the grayscale compensation data from the pixel unit grayscale pattern control circuit (325) is output from the selection circuit (341).

For example, in the first frame (F) period, the red (R) display pixel (1, 1) is not the third text data.
When displaying gradation, 6-bit gradation display data {000010} corresponding to the third gradation is input to the gradation control circuit (331) via the text data detection circuit (361). The 6-bit gradation display data {000010} is converted into the 4-bit gradation signal {0000} by the gradation control circuit (331) as described above. 6-bit gradation display data {000010} is an intermediate gradation that does not correspond to 16 gradation voltages (V0, V1, ... V15) prepared in advance, that is, gradation voltage (V0) and gradation voltage (V1). 2 / in the middle of
It corresponds to 6 gradations and needs to be controlled by the pixel unit gradation control circuit (325). Therefore, the pixel unit gradation pattern generation circuit (3
21) to a gradation pattern corresponding to 2/6 gradation, that is, FIG.
Among the gradation patterns shown in 4 (a), gradation compensation data {1} for one line and one column is output.

Therefore, the converted 4-bit gradation signal {0
000} is the gradation compensation data {1} in the arithmetic processing circuit (3
The addition processing is performed by 51), and the 4-bit gradation data {0001} from the arithmetic processing circuit (351) is output to the X driver (101) via the liquid crystal controller (251). Then, the gradation voltage (V1) is selected and output from the X driver (101) based on the 4-bit gradation data {0001}.

Similarly to the first frame (F) period, if the third frame is displayed in the second frame (F) period, one line in the gradation pattern shown in FIG.
The gradation compensation data {0} of the column is added to the converted 4-bit gradation signal {0000} by the arithmetic processing circuit (35), and the gradation voltage (V0) is calculated based on the 4-bit gradation data {0000}. ) Is selected and output.

Further, from the third frame (F) period to the sixth frame (F) period, a predetermined gradation voltage (V0) is similarly applied.
Alternatively, the gradation voltage (V1) is selected and output. Thus, when 6-bit grayscale display data {000010} corresponding to the third grayscale is input during the 6-frame (F) period, the continuous 6-frame (F) period is regarded as one display period, and the third A gradation display of gradation is realized.

Further, as shown in FIG. 15, when the third gradation which is not the text data is displayed on the green (G) display pixel (1, 8) in the first frame (F) period, it corresponds to the third gradation. The 6-bit gradation display data {000010} is input to the gradation control circuit (331) via the text data detection circuit (361). This 6-bit gradation display data {00001
0} is converted into a 4-bit gradation signal {0000} by the gradation control circuit (331) as described above. This 6-bit gradation display data {000010} is prepared 16
The gray scale voltage (V0, V1, ... V15) does not correspond to the intermediate gray scale, that is, 2/6 gray scale which is between the gray scale voltage (V0) and the gray scale voltage (V1). It needs to be controlled by the tone pattern control circuit (325). Therefore, according to the output from the gradation control circuit (331), the gradation pattern corresponding to 2/6 gradation of the pixel unit gradation pattern generation circuit (323), that is, 1 in the gradation pattern shown in FIG. The gradation compensation data {1} of the line and the two columns is output. Then, in the 4-bit gradation signal {0000}, the gradation compensation data {1} from the pixel unit gradation pattern generation circuit (323) is added by the arithmetic processing circuit (351),
4-bit gradation data {000 from the arithmetic processing circuit (351)
1} is the X driver (10
It is output to 1). Then, the gradation voltage (V1) is selected and output from the X driver (101) based on the 4-bit gradation data {0001}.

The halftone control in the pixel unit gradation pattern control circuit (325) has been described by taking the case where the input 6-bit gradation display data is not text data as an example. If the tone display data is text data, as in the case of the halftone control in the dot unit tone pattern control circuit (315) described above, 4-bit grayscale is performed without addition processing in the arithmetic processing circuit (351). Output the data to the LCD controller (251).

As described above, according to the liquid crystal display device (1) of this embodiment, it is possible to realize multi-gradation display of 64 gradations with a small number of gradation voltages, and to further reduce power consumption. It was possible to achieve low cost and equipment.

Moreover, according to this embodiment, since the realization of the halftone is realized by the gradation pattern formed based on the magic circle, the excellent display quality can be obtained without causing the flicker. I was able to secure it.

In addition, in the liquid crystal display device (1) of this embodiment, whether the input 6-bit gradation display data is text data or not is processed by the arithmetic processing circuit (351). Is determined. Therefore, for the display of text data such as characters in which flicker is likely to occur, the grayscale voltage corresponding to the grayscale close to the input 6-bit grayscale display data is selected based on the 4-bit grayscale signal. Therefore, even if a 6-bit gradation display data group in which text data and non-text data are mixed is input, a good display image without flicker can be obtained.

Further, according to this embodiment, the realization of the halftone is switched between the case where one control unit is constituted by each color dot unit and the control and the case where one control unit is constituted by the pixel unit are controlled. It is configured to be possible. Therefore, it is possible to realize a more optimal display state by selecting either one of the controls according to the display image. For example,
It is better to control based on the output of the dot unit gradation control circuit (315) for each color, but it is suitable for displaying moving images, but for still images and text data, it is based on the output of the pixel unit gradation pattern generation circuit. It is more suitable to control it.

By the way, in the above-described embodiment, the case where the halftone display is realized by the gradation pattern of the 6 × 6 matrix with the continuous 6 frame (F) period as one display period has been described. When (F) period is used as one display period and a 7 × 7 matrix gradation pattern is used, or when 6 continuous frame (F) periods are used as one display period and a 6 × 6 matrix gradation pattern is used. It may be realized by combining the case where it is realized by a 4 × 4 matrix gradation pattern with four continuous frame periods (F) as one display period.

For example, control of 4 frame (F) periods and 6
When used in combination with the control of the frame (F) period, a continuous 4 frame (F) period is used as one display period and is realized by a gradation pattern of a 4 × 4 matrix.
/ 4 gradation, 2/4 gradation, 3/4 gradation, and continuous 6
2/6 gray scales realized by a gray scale pattern of 6 × 6 matrix with 4 (frame) periods as one display period, 4 /
It is preferable to use 6 gradations.

This is because it is preferable to use the gradation of 1/4 gradation or more and 3/4 gradation or less in order to secure a high quality display image. In the embodiment described above, 16
Although individual gray scale voltages (V0, V1, ... V15) are prepared, the present invention is not limited to this and works effectively in combination with various gray scale voltages.

In this embodiment, the gradation patterns are arranged in a square array corresponding to the display pixels.
It does not have to be square array. Further, in this embodiment, as a concrete method for realizing the intermediate display gray scale of the gray scale voltage prepared in advance, one of the gray scale voltages adjacent to each other is selectively output in a plurality of consecutive frame (F) periods. However, it is not always necessary to select adjacent grayscale voltages in this way, and when performing grayscale display intermediate between the grayscale voltage (V1) and the grayscale voltage (V2), the grayscale is displayed. Voltage (V
0) and the gradation voltage (V2) or the gradation voltage (V0) and the gradation voltage (V3) may be selected, and two or more kinds of gradation voltages are selected in a plurality of frame (F) periods. You may control so that it may be performed. Such control can be easily realized by configuring the gradation compensation data prepared for each gradation pattern with 2 bits or more, and thus it is possible to realize even more gradations.

In this embodiment, a direct-viewing type active matrix type liquid crystal display device has been described as an example, but a projection type display device may be used. For example, in a projection-type display device including red (R), green (G), and blue (B) liquid crystal panels, each color is controlled by controlling each liquid crystal panel independently. Therefore, it is possible to perform control in units of picture elements by controlling the liquid crystal panels in association with each other. In addition, the present invention can be applied to various display devices other than the above and works effectively.

[0082]

According to the multi-gradation display device of the present invention, it is possible to realize a high-quality multi-gradation display in which flicker does not occur with a small number of voltage levels.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of an X driver in FIG.

3 is a diagram showing a gradation voltage waveform generated by the gradation voltage generating circuit in FIG.

FIG. 4 is a diagram showing a dot control unit and a pixel control unit of the liquid crystal display device of the embodiment.

FIG. 5 is a diagram for explaining the concept of gradation display of the liquid crystal display device of the embodiment.

6 is a diagram showing an auxiliary magic circle used for selection of a gradation pattern stored in a red (R) dot unit gradation pattern generating circuit in FIG.

7 is a diagram showing a gradation pattern for realizing 1/6 gradation stored in a red (R) dot unit gradation pattern generating circuit in FIG. 1;

8 is a diagram showing a gradation pattern for realizing 2/6 gradation stored in a red (R) dot unit gradation pattern generating circuit in FIG. 1;

9 is a diagram showing a gradation pattern for realizing 3/6 gradation stored in a red (R) dot unit gradation pattern generating circuit in FIG. 1;

10 is a diagram showing a gradation pattern for realizing 4/6 gradation stored in a red (R) dot unit gradation pattern generating circuit in FIG. 1;

11 is a diagram showing a gradation pattern for realizing 5/6 gradation stored in a red (R) dot unit gradation pattern generating circuit in FIG. 1;

12 is a diagram showing a gradation pattern for realizing 2/6 gradation stored in a green (G) dot unit gradation pattern generating circuit in FIG. 1;

13 is a diagram showing a gradation pattern for realizing 2/6 gradation stored in a blue (B) dot unit gradation pattern generation circuit in FIG. 1;

14 is a diagram showing a gradation pattern for realizing 2/6 gradation stored in the pixel unit gradation pattern generating circuit in FIG. 1;

FIG. 15 is a diagram showing a display state of the liquid crystal display device of the embodiment.

[Explanation of symbols]

(1) ... liquid crystal display device (11) ... liquid crystal panel (101) ... X driver (201) ... Y driver (251) ... liquid crystal controller (301) ... gradation signal conversion circuits (311a), (311b), (311c) ) Dot unit gradation pattern generation circuit (315) ... Dot unit gradation control circuit (321) ... Pixel unit gradation pattern generation circuit (325) ... Pixel unit gradation control circuit (331) ... gradation control circuit (341) ) ... Selection circuit (351) ... Operation processing circuit (371), (381) ... Selector circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuyoshi Yamamoto 50 Kamimabe, Yobu, Himeji-shi, Hyogo Prefecture Himeji Factory, Toshiba Corp. (72) Inventor, Arita 1-19-4 Kamuigusa, Suginami-ku, Tokyo (72) Inventor Hiroyoshi Murata 50, Kamimayu, Yobu, Himeji, Hyogo Prefecture, Ltd.In the Himeji Plant, Toshiba Corporation (72) Inventor, Hiroyuki Hamabe, 50, Kamimabe, Yobu, Himeji, Hyogo Prefecture, Ltd., Himeji, Toshiba Corporation (56) References Special Features Kaihei 5-73006 (JP, A) JP 5-73007 (JP, A) JP 3-20780 (JP, A) JP 5-108033 (JP, A) JP 5-241530 ( JP, A) JP-A-6-161391 (JP, A) JP-A-4-14093 (JP, A) JP-A-2-291521 (JP, A) JP-A-3-12692 (JP, A) (58 ) Fields surveyed (Int.Cl. ⁷ , DB name) G09G 3 / 00-3/38 G02F 1/133 505-580

Claims (3)

(57) [Claims] 1. In a multi-gradation display device for displaying a color image by selecting a predetermined voltage level according to input multi-gradation display data, at least display pixels corresponding to red, green and blue colors are provided. It
One display gradation can be obtained in m (m is a positive integer of 2 or more) frame period with a plurality of arrayed display panels and an array of the display pixels including each color of red, green and blue as one control unit. A first gradation pattern generating circuit for generating a first gradation pattern and a plurality of display images corresponding to any one of red, green and blue
A second gradation pattern generating circuit for generating a second gradation pattern for obtaining one display gradation in m frame periods with the array of primes as one control unit; and the first gradation pattern generating circuit or the second gradation putter
A selection circuit for selecting emission generating circuit, when the multi-gradation display data corresponding to the predetermined voltage level by selecting a predetermined voltage level to said corresponding output
However, the multi-gradation display data corresponds to the predetermined voltage level.
If not, the first circuit selected by the selection circuit
Selection control means for selecting and outputting one of the predetermined voltage levels based on the output of either the gradation pattern generating circuit or the second gradation pattern generating circuit. Multi-gradation display device. 2. The multi-gradation display data according to claim 1 is k
A multi-gradation display device, which is a digital signal of (k is a positive integer greater than 2) bits. 3. The multi-gradation display device according to claim 2, wherein
A multi-gradation display device comprising a gradation voltage generation circuit for supplying a voltage level lower than ^{k + 1} .