JPH07333582A - Device and method for displaying multi-gradation - Google Patents

Abstract

PURPOSE:To attain a multi-gradation display with no flicker with the number of less voltage levels. CONSTITUTION:This device is provided with a first gradation pattern generation circuit 311 generating a first gradation pattern and a second gradation pattern generation circuit 313 generating a second gradation pattern, and in the case where the multi-gradation display data is display gradation based on the first gradation pattern, at least one voltage level or the voltage level adjacent to one voltage level among the voltage levels is selected and outputted based on the first gradation pattern, and in the case where the multi-gradation display data are the display gradation based on the second gradation pattern, at least one voltage level or another voltage level separating at least the adjacent voltage level from one voltage level among the voltage levels is selected and outputted based on the second gradation pattern.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a liquid crystal display device and an electroluminescence (EL) display device, and more particularly to a multi-gradation display device and a multi-gradation display method useful as a projection display device.

[0002]

2. Description of the Related Art In recent years, in display devices typified by liquid crystal display devices, not only high definition but also multi-gradation display have been demanded. For each display pixel, a thin film transistor (hereinafter,
It is abbreviated as TFT. ) And the like are taken as an example of an active matrix type liquid crystal display device, each pixel electrode, a counter electrode facing the pixel electrode, and a liquid crystal held between the pixel electrode and the counter electrode. An image display is performed by holding a predetermined potential between the electrodes that are composed of the composition and that form one display pixel for one frame (F) period.

In such a liquid crystal display device, in order to prevent the deterioration of the liquid crystal composition, the voltage applied to the pixel electrode in order to realize the above-mentioned multi-gradation display, for example, 32 (2 ⁵ ) gradations. Since it is necessary to perform AC driving, the voltage level of 32 × 2 is required.

However, the provision of 32 × 2 voltage levels increases the power consumption of the IC that constitutes the drive circuit,
Alternatively, it is not a preferable method in terms of cost. Therefore, as another method for realizing multi-gradation display, the voltage level of the gradation voltage applied to each pixel electrode is not made different according to the display gradation, but the voltage application period, that is, There is known a so-called pulse width modulation method in which the pulse width is changed to realize display corresponding to each gradation. However, such a method also has a problem that a display circuit is complicated and a control is difficult in a multi-gradation display such as 32 (2 ⁵ ) gradation.

[0005]

As another method for solving the above-mentioned problems, one display period is formed by setting a plurality of consecutive frame (F) periods as one cycle, and a frame is turned on within one display period. (F) A so-called frame rate control (FRC) method is known, which realizes multi-gradation display by controlling the period. Also, for example, Japanese Patent Laid-Open No.
In addition to the above-mentioned FRC method, there are no.
There is also known a method in which a plurality of adjacent display pixels are used as one control unit and the frame (F) periods that are turned on between the adjacent display pixels are made different to prevent the occurrence of flicker.

According to such an FRC system, it is possible to eliminate the need for a plurality of gray scale voltages, and it is also possible to eliminate the disadvantages of the pulse width modulation system described above. However, it is necessary to further increase the number of frame (F) periods constituting one display period in order to realize further multi-gradation display by such an FRC method. For example, 32 (2 ⁵ )
If an attempt is made to realize multi-gradation display such as gradation, problems such as the multi-gradation display being visually unrecognized and flicker occurring due to an increase in the number of frame (F) periods occur. .

The present invention has been made in response to the above technical problems, and is capable of realizing multi-gradation display in which flicker does not occur and display quality is not impaired. It is an object of the present invention to provide a gradation display device and a multi-gradation display method.

[0008]

According to a first aspect of the present invention, there is provided a multi-gradation display device for displaying an image by selecting a predetermined voltage level according to input multi-gradation display data. And a display panel having display pixels of
Is a positive integer of 2 or more) A first gradation pattern generating circuit for generating a first gradation pattern for obtaining one display gradation in a frame period, and a second gradation pattern generating circuit for obtaining another display gradation in an m frame period. A second gradation pattern generating circuit for generating a gradation pattern; and, if the multi-gradation display data corresponds to a display gradation based on the first gradation pattern, a voltage level of the voltage level based on the first gradation pattern. If at least one voltage level or a voltage level adjacent to the one voltage level is selected and output, and the multi-gradation display data corresponds to a display gradation based on the second gradation pattern, then the second Selection control means for selecting and outputting at least one voltage level of the voltage levels or another voltage level separated from the one voltage level by at least an adjacent voltage level based on the gradation pattern. It is characterized in.

According to a second aspect of the invention, the multi-gradation display data according to the first aspect is k (k is a positive integer greater than 2).
It is characterized by being a bit digital signal.
The invention according to claim 3 is characterized in that the multi-gradation display device according to claim 2 is provided with a gradation voltage generating circuit for supplying a voltage level lower than 2 ^{k + 1} .

The invention according to claim 4 is characterized in that the multi-gradation display device according to claim 1 is provided with a light source and a condensing means for guiding the light source light from the light source to the display panel. There is.

According to a fifth aspect of the present invention, the first gradation pattern generating circuit and the second gradation pattern generating circuit according to the first aspect control the m × m display pixels as one control unit. There is.

According to a sixth aspect of the present invention, each of the first gradation pattern and the second gradation pattern according to the first aspect is
It is characterized in that one table composed of m × m gradation compensation data is composed of m sheets.

The invention according to claim 7 is characterized in that the control units according to claim 5 are arranged in a substantially square arrangement. The invention according to claim 8 is characterized in that each of the first gradation pattern and the second gradation pattern according to claim 6 is configured based on a magic circle or a complete magic circle.

According to a ninth aspect of the present invention, there is provided a multi-gradation display method in which a predetermined voltage level is selected according to input multi-gradation display data to display an image on a plurality of display pixels. If the grayscale display data corresponds to a display grayscale based on a first grayscale pattern that provides one display grayscale in m frame periods, at least one voltage level of the voltage levels based on the first grayscale pattern or A voltage level adjacent to the one voltage level is selected and output, and the multi-grayscale display data corresponds to a display grayscale based on a second grayscale pattern in which another display grayscale is obtained in m frame periods. In this case, based on the second gradation pattern, at least one voltage level of the voltage levels or another voltage level separated by at least an adjacent voltage level from the one voltage level is selected and output. It is characterized in that.

[0015]

According to the multi-gradation display device and method of the present invention, as described above, the multi-gradation display data is converted into the display gradation based on the first gradation pattern that provides one display gradation in m frame periods. When corresponding, at least one of the voltage levels or a voltage level adjacent to the one voltage level is selected and output based on the first gradation pattern, and another display gradation is obtained in the m frame period. When the display gradation based on the second gradation pattern is supported, at least one voltage level among the voltage levels or another voltage level separated by at least an adjacent voltage level from one voltage level is selected based on the second gradation pattern. And output.

As a result, since the number of frame (F) periods to be controlled is not significantly increased, it is possible to realize multi-gradation display without the occurrence of flicker or the like and without impairing the display quality. .

[0017]

EXAMPLE As an example of the present invention, 32 (2)
⁵ ) An active matrix type liquid crystal display device for displaying gradation will be described as an example with reference to the drawings. As shown in FIG. 1, this liquid crystal display device (1) has (640 × 3) rows ×
Liquid crystal panel (11) capable of color display having display pixels arranged in a matrix of 480 columns, and this liquid crystal panel
An X driver (101) and a Y driver (201) electrically connected to (11), a liquid crystal controller (251) for controlling the X driver (101) and the Y driver (201), and an external input. A gradation signal conversion circuit (301) that converts 5-bit gradation display data to 3-bit gradation display data and outputs it to the liquid crystal controller (251), and a reference for each frame (F) period as shown in FIG. The polarity is reversed with respect to the voltage 8
Grayscale voltage (V0, V1, V2 ...
V7) output to the X driver (101) gradation voltage generation circuit
(501) and. In this embodiment, the frame inversion drive is taken as an example, but in the case of combining the line inversion drive with the frame inversion drive in order to further prevent the occurrence of flicker, one frame (F) is used.
A square wave voltage whose polarity is inverted with respect to the reference voltage every period and whose polarity is also inverted with respect to the reference voltage every predetermined horizontal scanning line period is used as the gradation voltage (V0, V1, V2 ... V7). And good.

This liquid crystal panel (11) is of a so-called active matrix type and has a TF for each display pixel electrode (21).
T (31) is provided. The scanning line (13) connected to the TFT (31) has a Y driver (2
01) supplies the scan pulse (VG) for a predetermined period of time T
The FT (31) becomes conductive. This allows the X driver (1
The gradation voltage from the signal line (15) connected to (01) is applied to the TFT (3
It is written in the display pixel electrode (21) via 1), and the liquid crystal capacitance (Clc) is generated by the liquid crystal capacitance (Clc) and the auxiliary capacitance line (51).
And an auxiliary capacitance (Cs) provided in parallel with the auxiliary capacitance (Cs) are held for one frame (F) for image display.

The X driver (101), as shown in FIG.
A shift register (111) that sequentially transfers input 3-bit gradation display data based on a shift clock (CK) and a start pulse (ST), and a decoder (113) that converts the output from the shift register (111). A selection circuit (115) for selecting and outputting one of the eight gradation voltages (V0, V1, ... V7) according to the output of the decoder (113), and a latch for holding this output for a predetermined period. Circuit (117).

Next, the gradation signal conversion circuit (301) of the liquid crystal display device (1) will be described. This gradation signal conversion circuit
(301) selects the 5-bit gradation display data input from the outside from any of eight gradation voltages (V0, V1, ... V7) prepared in the gradation voltage generation circuit (501). Gradation control circuit (33
1) is equipped.

When the converted 3-bit gradation display data corresponds to the gradation voltage prepared in advance in the gradation voltage generation circuit (501), the 3-bit gradation display data is output without being processed. If the converted 3-bit gradation display data corresponds to an intermediate gradation of the gradation voltage prepared in the gradation voltage generation circuit (501) in advance, an operation for expressing the intermediate gradation. An arithmetic processing circuit (351) for outputting after processing is provided.

The gradation signal conversion circuit (301) also includes first to fifth gradation pattern generation circuits (311), (313), () for performing arithmetic processing on the converted 3-bit gradation display data. 315), (3
It is connected to 17) and (319) through the selection circuit (341).
This selection circuit (341) is used when the externally input 5-bit gradation display data corresponds to an intermediate display gradation between gradation voltages prepared in advance in the gradation voltage generation circuit (501). Output from the gradation control circuit (331) according to the display gradation, the first to fifth gradation pattern generation circuits (311), (313), (315), (317),
It functions to select one of (319).

Each gradation pattern generation circuit (311), (313), (31
5), (317), and (319) are 16 display pixels forming a display pixel area of the liquid crystal panel (11) in a quadrangular shape composed of 4 rows and 4 columns adjacent to each other, as shown in FIG. (4 × 4 matrix) is used as a control unit, and one display screen is divided into blocks of 120 rows × 480 columns to be controlled.
The frame (F) period is used as one display period to control each control unit.

For each gradation pattern, one table consisting of 16 pieces of 2-bit gradation auxiliary data for realizing one display gradation is shown in FIGS. 10A to 10D and FIG. 11.
As shown in (a) to (d), four sheets are configured to realize one display gradation, and the gradation pattern for realizing 1/4 gradation shown in FIG. 10 is the first gradation pattern generation circuit ( 311) to 2
The gradation pattern for realizing / 4 gradation is the second gradation pattern generating circuit (313), the gradation pattern for realizing 3/4 gradation is the third gradation pattern generating circuit (315), and The gradation pattern for realizing the 20th and 25th gradations shown in FIG. 11 is in the 4th gradation pattern generating circuit (317), and the gradation pattern for realizing the 28th gradation is the 5th gradation pattern. Generator circuit (3
19).

Then, each gradation pattern generation circuit (311), (3
13), (315), (317), and (319) are four-frame counters that select one of the first to fourth tables from the gradation patterns shown in FIGS. 10 and 11, and display pixels from one table. Designated circuit consisting of a 4-line counter and 4-column counter to obtain 2-bit grayscale compensation data corresponding to
1) are connected respectively.

According to the gradation signal conversion circuit (301) thus constructed, the 5-bit gradation display data inputted from the outside is converted into the 3-bit gradation display data by the gradation control circuit (331). In addition, when the converted 3-bit gradation display data corresponds to the gradation voltage prepared in advance in the gradation voltage generating circuit (501), this 3-bit gradation display data is processed by the arithmetic processing circuit (351). The 3-bit gradation display data that is output to the X driver (101) via the liquid crystal controller (251) without any arithmetic processing, and the converted 3-bit gradation display data is prepared in advance in the gradation voltage generation circuit (501). If the gray scale corresponds to the middle gray scale of the voltage, one of the gray scale pattern generation circuits (311), (313), (315), (3) selected by the selection circuit (341).
An arithmetic processing circuit (351) performs arithmetic processing based on the 2-bit gradation compensation data of 17) and (319) so that an intermediate display gradation is expressed, and this arithmetic processing is applied to a 3-bit gradation display. Data is sent to the X driver (101) via the LCD controller (251)
Output to.

The method for realizing the intermediate display gradation used in the liquid crystal display device (1) of this embodiment will be described in detail below. Grayscale voltage (V0, composed of eight square waves,
In the liquid crystal display device in which V1, ..., V7) are prepared, it is possible to display an image of 8 gradations by selecting one of the prepared gradation voltages (V0, V1, ... V7). Therefore,
This liquid crystal display device (1) uses the gradation voltage (V0, V1, ... V7) composed of eight square waves to realize the image display of 32 gradations. To do.

One gradation voltage (Vi) (i = 0, 1, 2, ..., 6),
1 / middle of other gradation voltage (Vi + 1) adjacent to this
In order to realize four gradations, the gradation voltage (Vi) is applied in three frame (F) periods and the gradation voltage (Vi + 1) is applied in the remaining one frame (F) period in four consecutive frame (F) periods. ) Control to select. In order to realize 2/4 gray scale between one gray scale voltage (Vi) and the gray scale voltage (Vi + 1) adjacent to it, 2 frames (F) in 4 consecutive frame periods (F) The gradation voltage (Vi) is controlled during the period, and the gradation voltage (Vi + 1) is controlled during the remaining two frame (F) periods. In order to realize 3/4 gradation between one gradation voltage (Vi) and the adjacent gradation voltage (Vi + 1), one frame ( The gray scale voltage (Vi) is selected during the F) period, and the gray scale voltage (Vi + 1) is selected during the remaining three frame (F) periods.

In this way, 29 gradations can be realized by combining the control of the frame (F) period and the eight gradation voltages (V0, V1, ... V7). Furthermore,
In this embodiment, in order to realize the image display of 32 gradations,
The lacking three gradations are compensated by the following method.

That is, in order to realize 20 gradations between 19 gradations and 21 gradations shown in FIG. 5, instead of using the adjacent gradation voltage (V4) and gradation voltage (V5), Adjusted voltage (V3)
And gradation voltage (V6). Similarly,
To realize 25 gradations between 24 gradations and 26 gradations, gradation voltage (V4) and gradation voltage (V7) are used, and 2
28 gradations between 7 gradations and 29 gradations are realized by using gradation voltages (V5) and gradation voltages (V7). The selection of these two gray scale voltages is performed by selecting one gray scale voltage during the 2 frame (F) periods and the other gray scale voltage during the remaining 2 frame (F) periods during the continuous 4 frame (F) periods. Control to select.

As described above, by controlling the frame (F) period and combining eight gradation voltages (V0, V1, ... V7), an image display of 32 gradations is realized as shown in FIG. .

Next, each gradation pattern used in this embodiment will be described in detail with reference to FIGS. The selection of each gradation pattern in this embodiment is considered based on the concept of a perfect magic circle.

The perfect magic circle is, for example, N × N rows and N columns.
Each matrix of the N matrix is configured such that consecutive different numbers from 1 to N ² are assigned so that the sum of the numbers is equal in each row, each column and each diagonal column. A magic circle is, for example, N in N rows and N columns.
Each matrix of the × N matrix is configured such that consecutive different numbers from 1 to N 2 are allocated so that the sum of the numbers is equal in each row and each column.

In the matrices other than the (4r + 2) × (4r + 2) matrix (r is a positive integer greater than or equal to 1), a perfect magic circle exists, so each gradation pattern in this embodiment is formed based on the perfect magic circle. Has been done. still,
(4r + 2) × (4r + 2) matrix, for example 6 × 6
When the gradation pattern is formed by a matrix or the like, it may be formed by using a magic circle.

FIG. 6 shows a complete magic circle formed by assigning different numbers 1 to 16 to each matrix of the 4 × 4 matrix. Such a complete magic circle is, for example, 4x
Numbers 1 to 4 in each matrix of 4 matrices, each row,
It can be obtained from an auxiliary magic circle that is assigned so that the numbers in each column and each diagonal are equal. That is, as shown in FIG. 7, two different types of auxiliary magic circles A and B are used to calculate [4 × (a−1) + B] (where a and b are auxiliary magic circles A and B, respectively). The numbers in the matrix at the same locations in () are shown).

Each gradation pattern is selected as follows from the complete magic circle constructed in this way. If one display pixel realizes 1/4 gray scale between the gray scale voltage (Vi) and the gray scale voltage (Vi + 1) adjacent to the gray scale voltage (Vi), 1 in 4 consecutive frame (F) periods The gradation voltage (Vi + 1) may be selected only during the frame (F) period, and the gradation voltage (Vi) may be selected during the other three frame (F) periods. Therefore, as shown in FIG.
4 tables for allocating gradation auxiliary data {01} to the matrix to which the number 4 is allocated, and gradation auxiliary data {00} for others, and realizing 1/4 gradation of the first gradation pattern The first table inside is constructed. Further, as shown in the figure, the gradation auxiliary data {01} is allocated to the matrix to which the numbers 5 to 8 are allocated, and the gradation auxiliary data {00} is allocated to the other matrix to obtain 1/1 of the first gradation pattern.
In the second table of the four tables for realizing four gradations, the gradation auxiliary data {01} is allocated to the matrix to which the numbers 9 to 12 are allocated, and the gradation auxiliary data {00} is allocated to the other tables. The third table out of the four tables for realizing 1/4 gradation of the first gradation pattern is
Gradation auxiliary data {01} is allocated to the matrix to which the numbers 3 to 16 are allocated, and the other is gradation auxiliary data {0}.
0} is allocated to form a fourth table out of four tables for realizing 1/4 gradation of the first gradation pattern.
It should be noted that FIG. 7B shows the gradation auxiliary data {0
1} shows the axes approximated to the assigned matrix.

By sequentially repeating the first to fourth tables configured as described above with four frame (F) periods as one display period, the gray scale voltage (Vi) and the adjacent voltage are adjacent to the gray scale voltage (Vi) in four frame (F) periods. It is possible to realize 1/4 gradation between the applied gradation voltage (Vi + 1). In this embodiment, the tables are rearranged so that the axes of the groups are rotated by 90 ° for each frame period, that is, the first table and the second table.
The table, the fourth table, and the third table are rearranged in this order to realize 1/4 gradation between the gradation voltage (Vi) shown in FIG. 10 and the gradation voltage (Vi + 1) adjacent thereto. To form a gradation pattern for Thus, by determining the selection order of the tables so that the axes of the tables that can be selected in the adjacent frame (F) period are different, it is possible to further prevent display gradation disturbance and display screen flicker. It can be resolved.

Further, when one display pixel realizes 2/4 gradation between the gradation voltage (Vi) and the gradation voltage (Vi + 1) adjacent thereto, four consecutive frames (F). 2 during the period
Select the gradation voltage (Vi + 1) only during the frame (F) period,
In the other two frame (F) periods, the gray scale voltage (Vi) may be controlled to be selected. Therefore, as shown in FIG.
To realize the 2/4 gradation of the first gradation pattern, the gradation auxiliary data {01} is allocated to the matrix to which the numbers of 8 are allocated, and the gradation auxiliary data {00} is allocated to the other matrixes. The first table in the table is constructed. Also,
The gradation auxiliary data {01} is assigned to the matrix to which the numbers 9 to 16 are assigned, and the other is the gradation auxiliary data {0}.
0} is assigned to form a second table out of four tables for realizing 2/4 gradation of the first gradation pattern.
Further, similarly, by constructing the third table and the fourth table of the four tables for realizing the 2/4 gradation of the first gradation pattern, the gradation voltage (Vi
) And the gradation voltage (Vi + 1) adjacent to
A gradation pattern for realizing four gradations is configured.
In this way, 4 frames (F) period is set to 1
By sequentially repeating the first to fourth tables as the display period, the 2 / 4th floor between the gray scale voltage (Vi) and the gray scale voltage (Vi + 1) adjacent to the gray scale voltage (Vi) in the 4 frame (F) period. Key can be realized.

Further, if one display pixel realizes 3/4 gradation between the gradation voltage (Vi) and the gradation voltage (Vi + 1) adjacent thereto, four consecutive frames (F It is sufficient to select (Vi + 1) only for the three frame (F) periods in the period) and to select the gradation voltage (Vi) for the other one frame (F) period. Therefore, the gradation pattern is formed by the inversion pattern of the gradation auxiliary data of the four tables for realizing the 1/4 gradation shown in FIG. With the configuration as described above, a 4-frame (F) period is defined as one display period,
By sequentially repeating the first to fourth tables, it is possible to realize 3/4 gradation between the gradation voltage (Vi) and the gradation voltage (Vi + 1) adjacent to the gradation voltage (Vi) in the period of four frames (F). .

When 20 gradations between 19 gradations and 21 gradations are realized, gradation voltage (V3) and gradation voltage (V6)
), To realize 25 gradations between 24 gradations and 26 gradations, gradation voltage (V4) and gradation voltage (V7), and 28 gradations between 27 gradations and 29 gradations are realized. To realize the gradation voltage (V5)
And the gradation voltage (V7), one of the gradation voltages is selected for two frame (F) periods in four consecutive frame (F) periods,
It was confirmed that the control should be performed so that the other gray scale voltage is selected in the other two frame (F) periods.

Therefore, in order to realize 20 gradations and 24 gradations, the gradation auxiliary data {11} is allocated to the matrix to which the numbers 1 to 8 shown in FIG. 9 are allocated, and the other gradation auxiliary data {00. } To configure the first table of the four tables for realizing the fourth gradation pattern. Further, the gradation auxiliary data {11} is allocated to the matrix to which the numbers 9 to 16 are allocated, and the gradation auxiliary data {00} is allocated to the other matrix, and the second table among the four tables of the fourth gradation pattern is assigned. Constitute. Similarly, the third table and the fourth table are respectively configured.

To realize 28 gradations, 1 shown in FIG. 9 is used.
The first table of the four tables for realizing the fourth gradation pattern by allocating the gradation auxiliary data {10} to the matrix to which the numbers of 8 are allocated and the gradation auxiliary data {00} to the other matrixes. Make up. Further, the gradation auxiliary data {1
0} is allocated, and the other gradation data {00} is allocated to configure the second table among the four tables of the fourth gradation pattern. Similarly, the third table and the fourth table are respectively configured.

As described above, by using the gradation pattern of the 4 × 4 matrix formed based on the complete magic circle, for example, the gradation voltage (Vi
) And the same gray scale voltage between the gray scale voltages (Vi + 1) are displayed, the frame (F) period in which the same gray scale voltage is selected between adjacent display pixels is well balanced. Since they are different, flicker does not occur.

Each gradation pattern configured in this way is composed of a gradation pattern generation circuit (311) composed of a RAM,
Pre-stored in (313), (315), (317), (319). In this embodiment, each gradation pattern generating circuit (313), (315), (31
Although 7) and (319) are composed of RAM, they may be composed of ROM.

FIG. 12 shows one display state of the liquid crystal panel (11), and a concrete operation for realizing such display will be described. First, when displaying the first gradation on the display pixel (1, 1), the 5-bit gradation display data {00000} corresponding to the first gradation is converted into the gradation signal conversion circuit (301) of the liquid crystal display device (1). ). The 5-bit gradation display data {00000} is converted into eight gradation voltages (V0, V1, V0, V1 by the gradation control circuit (331) of the gradation signal conversion circuit (301).
... 3-bit gradation display data {000} corresponding to V7)
Is converted to. The 5-bit gray scale display data {00000} for displaying the first gray scale is the gray scale voltage (V0) of the eight gray scale voltages (V0, V1, ... V7) prepared in advance.
Therefore, the 3-bit gradation display data {000} is output to the X driver (101) via the liquid crystal controller (251) without being processed by the arithmetic processing circuit (351). Then, by the X driver (101), based on the 3-bit gradation display data {000}, the gradation voltage (V0)
Is selected and output, and the first gradation is displayed on the display pixel (1, 1).

When displaying the sixth gradation on the display pixel (1, 2), 5-bit gradation display data {00101} corresponding to the sixth gradation is input to the gradation signal conversion circuit (301). This 5-bit gradation display data {00101} is converted by the gradation control circuit (331) into 8 gradation voltages (V0, V1,
... 3-bit gradation display data {001} corresponding to V7)
Is converted to. The 5-bit gradation display data {00101} for displaying the sixth gradation is an intermediate gradation which does not correspond to the prepared gradation voltages of 8 (V0, V1, ... V7), that is, the gradation voltage. (1) corresponds to 1/4 gradation (see FIG. 5) between the gradation voltage (V2) adjacent to (V1),
Since it needs to be controlled by the first gradation pattern generation circuit (311), the selection circuit (341) selects the first gradation pattern generation circuit (311) according to the output from the gradation control circuit (331). Then, the designating circuit (321) receives the 2nd pixel corresponding to the display pixel (1, 2) from the first gradation pattern generating circuit (311).
Bit gradation compensation data is represented by 1 line and 2 column gradation compensation data of the first table, that is, 12 in FIG.
The gradation compensation data {00} is extracted from the first table of / 4 gradation and output. As a result, the 3-bit gradation display data {001} is added to the gradation compensation data {00} from the first gradation pattern generating circuit (311) by the arithmetic processing circuit (351).
Is added, and the 3-bit gradation display data {001} from the arithmetic processing circuit (351) is added to the liquid crystal controller (251).
It is output to the X driver (101) via the. Then, the 3-bit gradation display data {0
01}, the gradation voltage (V1) is selected and output.

If the sixth gray scale is displayed in the second frame (F) period as in the first frame (F) period,
Grayscale compensation data {00} is extracted from the second table of 1/4 grayscale in FIG.
The gradation compensation data {00} is added to 1} by the arithmetic processing circuit (351), and the 3-bit gradation display data {001} is added.
Based on the above, the gradation voltage (V1) is output from the X driver (101).

If the sixth gray scale is displayed in the third frame (F) period as well as the first frame (F) period,
Grayscale compensation data {01} is extracted from the third table of ¼ grayscale in FIG.
The gradation compensation data {01} is added to 1} by the arithmetic processing circuit (351), and the 3-bit gradation display data {001} is added.
Based on the above, the gradation voltage (V2) is output from the X driver (101).

Further, if the sixth gray scale is displayed in the fourth frame (F) period as in the first frame (F) period, the gray scale is calculated from the fourth table of the 1/4 gray scale in FIG. Compensation data {00} is extracted and 3-bit gradation display data {0
01} in the arithmetic processing circuit (351) for gradation compensation data {00}
Is added, and the gradation voltage (V1) is output from the X driver (101) based on the added 3-bit gradation display data {001}.

In this way, when the 5-bit gray scale display data {00101} for displaying the sixth gray scale is input, the continuous four frame (F) period is set as one display period and the sixth gray scale is displayed. The display is realized.

Even in the case of displaying the fourth gradation in the display pixel (1, 3) adjacent to the display pixel (1, 2), the display pixel (2, 2) is also used in this embodiment.
1) and adjacent display pixels such as display pixel (1, 3)
Since the gradation pattern is selected so that the frame (F) period in which the gradation voltage (V1) and the gradation voltage (V2) are selected is well balanced, the occurrence of flicker does not occur.

By the way, in the above case, since the 5-bit gradation display data input corresponding to the display pixel (1, 2) displays the sixth gradation in any period of 4 frames (F). 5-bit gradation display data {00101}
Although the case has been shown, the 5-bit gradation display data input for each frame (F) period may be different in, for example, a moving image.

Therefore, the case where 5-bit grayscale display data {10011} for displaying the 20th grayscale in the second frame (F) period is input to the display pixel (1, 2) will be described. This 5-bit gradation display data {1001
1} is converted into 3-bit gradation display data {011} corresponding to eight gradation voltages (V0, V1, ... V7) by the gradation control circuit (331) as described above. And
The 5-bit gradation display data {10011} for displaying the twentieth gradation is the prepared 8 gradation voltages (V0
, V1, ... V7) which is a halftone that does not correspond to
It needs to be controlled by the gradation pattern generation circuit (317). Therefore, the converted 3-bit gradation display data {0
11} extracts the grayscale compensation data {11} from the second table of the 20th grayscale in FIG. 11} is added, and the X driver (101) is based on the added 3-bit gradation display data {110}.
Will output the gradation voltage (V6).

In a moving image or the like, the 5-bit gradation display data input corresponding to one display pixel is displayed in each frame period (F).
It will be different for each. However, since it is difficult to visually distinguish the gradation in a moving image or the like, display is performed for each frame (F) period based on the input 5-bit gradation display data as described above. I'm fine.

Next, as shown in FIG. 12, a case where the 11th gradation is displayed on the display pixel (1, 5) will be described. Similarly to the above, the 5-bit gradation display data {01010} corresponding to the 11th gradation is converted into the 3-bit gradation display data {010}. Then, since it is a halftone that does not correspond to the prepared eight grayscale voltages (V0, V1, ... V7) and needs to be controlled by the second grayscale pattern generation circuit (313), these 3 bits are used. The gradation display data {010} is the data of one line and one column of the first table forming the gradation pattern of 2/4 gradation shown in FIG. 10, that is, the gradation compensation data {01} is the arithmetic processing circuit ( 351)
The 3-bit gradation display data {011} that has been subjected to the addition processing and the arithmetic processing is output to the X driver (101) via the liquid crystal controller (251). Then, the gradation voltage (V3) is selected and output from the X driver (101) based on the 3-bit gradation display data {011}.

When displaying the 12th gradation on the display pixel (1, 5) in the second frame (F) period, the second table of the 3/4 gradation pattern shown in FIG. 10 is formed. Data of 1 line, 5 columns, that is, gradation compensation data {0
1} is subjected to addition processing by the arithmetic processing circuit (351), and the gradation voltage (V3) is selected and output based on the 3-bit gradation display data {011}.

As described above, according to the liquid crystal display device (1) of this embodiment, the gradation voltages (V0, V1, ... V7) consisting of eight square wave voltages having 16 voltage levels are provided. 32 gradation display can be realized by using. Moreover,
In this embodiment, 2-bit gradation compensation data is allocated to each matrix of each table that constitutes each gradation pattern based on the concept of a perfect magic circle, so that no flicker occurs and display quality is improved. It is possible to realize a high gradation multi-tone image display.

In the above embodiment, eight gradation voltages (V0, V1, ... V7) are prepared, but the present invention is not limited to this, and various gradation voltages can be combined. It works effectively.

In this embodiment, eight gradation voltages (V0, V1, ... V7) are used in combination for control in four consecutive frame periods (F), but the present invention is not limited to this. Instead, one control unit composed of a 5 × 5 matrix may be controlled in five consecutive frame (F) periods, or one control unit composed of a 7 × 7 matrix may be controlled in seven consecutive frame (F) periods. . In addition, 4 consecutive
The control in the frame (F) period may be used in combination with the control in the continuous 5 frame (F) period or the 7 frame (F) period described above. The display can be realized. For example, by combining the above-described method with a method of controlling one control unit consisting of a 5 × 5 matrix in five consecutive frame (F) periods, one gradation voltage (Vi) and the gradation voltage ( Vi + 1) and 2/5 gradation, 3/5
The gradation and the like can also be realized.

In this embodiment, the liquid crystal panel (11) in which the display pixels are squarely arranged has been described as an example, but it goes without saying that a delta arrangement or the like is also possible. Further, in this embodiment, as a specific method for realizing a display gradation intermediate between voltage levels prepared in advance, one of two gradation voltages is selectively output in a plurality of consecutive frame (F) periods. Configured to be continuous, but multiple consecutive frames (F)
It goes without saying that it may be configured to select and output three or more gradation voltages in a period. For example, four frames (F) in which one control unit composed of a 4 × 4 matrix is continuous.
In controlling by the period, the grayscale voltage (V0) in the first frame (F) period and the fourth frame (F) period, the grayscale voltage (V1) in the second frame (F) period, and the third frame ( By controlling to select the gradation voltage (V2) during the period F), a display gradation corresponding to another intermediate gradation voltage between the gradation voltage (V0) and the gradation voltage (V1) is displayed. Can be realized.

Further, each gradation pattern generating circuit (311), (313), (315), (317), (319) in this embodiment shows the display pixel area of the liquid crystal panel (11) in FIG. As described above, 16 display pixels (4 × 4 matrix) having a quadrangular shape are used as control units and are divided into a plurality of blocks for control. However, these control units do not necessarily have to be in a substantially square array pattern. Instead, various arrangements such as the arrangement shown in FIG. 13 can be selected.

By the way, in this embodiment, the 5-bit gradation display data inputted from the outside is converted into the gradation signal conversion circuit (3
After being converted to 3-bit gradation display data via 01),
Although the liquid crystal controller (251) is configured to be input, gradation display data input from the outside is directly input to the liquid crystal controller (25) as shown in FIGS.
It is preferable to provide selector circuits (601) and (603) so that the connection form such as input to (1) or input via the gradation signal conversion circuit (301) can be selected.

By doing so, it becomes unnecessary to design a plurality of types of liquid crystal display devices according to the number of bits of gradation display data input from the outside. For example, in FIG.
With the configuration shown in (a), when the gradation display data input from the outside is 3 bits, the selector circuit (6
By switching between 01) and (603), the gradation signal conversion circuit (301)
It is possible to output 3-bit gradation display data via the liquid crystal controller (251) without passing through. That is,
Whether the gradation display data input from the outside is 3 bits or 5 bits, gradation display can be realized by the common liquid crystal display device (1).

In this embodiment, the active matrix type liquid crystal display device has been described as an example, but it can be applied to various display devices other than this and works effectively.
By the way, the above-described embodiment has been described by taking the direct-viewing type active matrix type liquid crystal display device as an example.
Alternatively, a front projection type liquid crystal display device (701) shown in FIG.
Alternatively, it works more effectively in the rear projection type liquid crystal display device (801).

The front projection type liquid crystal display device (701) includes a light source (7
03), a condenser lens (711) for condensing the light from the light source, an active matrix type liquid crystal display device (1) for modulating the light transmitted through the condenser lens (711), and a liquid crystal display device (1) A projection lens (7) that projects the modulated light onto the screen (731).
21) and consist of. In the case where the liquid crystal display device (1) controls the transmission / scattering of light by the polymer dispersed liquid crystal or the like, the configuration is slightly different from that described above.

The rear projection type liquid crystal display device (801) is
Light source (803), condensing lens (811) that condenses light from the light source, active matrix liquid crystal display device (1) that modulates the light that has passed through the condensing lens (811), modulated by the liquid crystal display device (1) First reflector that guides the modulated light that has been generated to the projection lens (821)
(813), the second reflecting mirror (815) and the second reflecting mirror (81) for guiding the modulated light transmitted through the projection lens (821) to the screen (831).
7), and a housing (841) for housing the liquid crystal display device (1), etc.
It is composed of and.

The reason why the above-mentioned liquid crystal display device (1) works effectively in the projection type liquid crystal display devices (701) and (801) will be described. In the above liquid crystal display device (1), in the vicinity of ± 10 ° with respect to the normal direction of the display surface, the display gradation and the transmittance correspond to each other according to the characteristics of the liquid crystal as shown by the curve (a) in FIG. However, in the vicinity of ± 20 °,
7 As shown by the medium curve (b), the phenomenon that the transmittance at the 25th gradation does not correspond to the display gradation occurs. However, according to this projection type liquid crystal display device (701), (801), the condensing lens (7
Since the light that has passed through (11) is transmitted, the light source light is prevented from entering at an angle exceeding ± 15 ° with respect to the normal direction in the first place, so that gradation display failure is less likely to occur. As described above, according to the liquid crystal display device of the present invention,
In particular, it works effectively in a projection type liquid crystal display device.

[0068]

According to the present invention, when the input multi-gradation display data is different from the display gradation corresponding to the prepared voltage level, the floor selected based on the multi-gradation display data is selected. Since the selection control means controls to select and output a predetermined voltage level according to the output of the tone pattern generation circuit, it is possible to realize multi-gradation display with a small number of voltage levels. This makes it possible to achieve low cost or downsizing of the device.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of an X driver in FIG.

3 is a diagram showing a gradation voltage waveform generated by the gradation voltage generating circuit in FIG.

FIG. 4 is a diagram showing a control unit controlled by a gradation pattern generation circuit of the liquid crystal display device of this embodiment.

FIG. 5 is a diagram for explaining the concept of multi-gradation display of the liquid crystal display device of this embodiment.

FIG. 6 is a diagram for explaining a complete magic circle of a 4 × 4 matrix.

FIG. 7 is a diagram for explaining a method of creating a complete magic circle of the 4 × 4 matrix shown in FIG. 6;

FIG. 8 is a diagram for explaining the creation of a one-tone pattern based on the complete magic circle in FIG. 6;

9 is a diagram for explaining the creation of another gradation pattern based on the complete magic circle of FIG. 6;

10 is a diagram showing a 4 × 4 matrix gradation pattern created based on the complete magic circle of FIG. 6 and stored in the first to third gradation pattern generating circuits of FIG. 1; .

11 is a diagram showing a 4 × 4 matrix gradation pattern created based on the complete magic circle shown in FIG. 6 and stored in the fourth and fifth gradation pattern generating circuits shown in FIG. 1; .

FIG. 12 is a diagram showing a display example of the liquid crystal display device of this embodiment.

FIG. 13 is a diagram showing another control unit of the liquid crystal display device of this embodiment.

FIG. 14 is a partial schematic configuration diagram of a liquid crystal display device according to another embodiment of the present invention.

FIG. 15 is a schematic configuration diagram of a projection type liquid crystal display device of an embodiment using the liquid crystal display device of the embodiment of the invention.

FIG. 16 is a schematic configuration diagram of a projection type liquid crystal display device of another embodiment using the liquid crystal display device of another embodiment of the present invention.

FIG. 17 is a diagram showing the viewing angle dependence of liquid crystal, in which the vertical axis represents the transmittance and the horizontal axis represents the display gradation.

[Explanation of symbols]

 (1) ... liquid crystal display device (11) ... liquid crystal panel (101) ... X driver (201) ... Y driver (251) ... liquid crystal controller (301) ... gradation signal conversion circuit (311) ... first gradation pattern generation Circuit (313) ... Second gradation pattern generating circuit (315) ... Third gradation pattern generating circuit (317) ... Fourth gradation pattern generating circuit (319) ... Fifth gradation pattern generating circuit (601), ( 603) ... Selector circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuyoshi Yamamoto 50 Kamimabe, Yobu, Himeji City, Hyogo Prefecture, Ltd. Inside the Himeji Plant, Toshiba Corporation (72) Inventor, Arita 1-19-4, Kamuigusa, Suginami-ku, Tokyo (72) ) Inventor Hirofumi Kato 50, Kamimayu, Yobu, Himeji City, Hyogo Prefecture, Ltd.In the Himeji Plant, Toshiba Corporation (72) Inventor, Hiroyoshi Murata, 50, Kamimayu, Himeji City, Himeji, Hyogo Prefecture (72) Invention, Himeji Plant, Toshiba Corporation Person Hiroyuki Hamabe 50 Kamamibe, Yobu-ku, Himeji-shi, Hyogo Prefecture Stock Company Toshiba Himeji Factory

Claims (9)

[Claims] 1. A multi-gradation display device for displaying an image by selecting a predetermined voltage level according to input multi-gradation display data, comprising: a display panel having a plurality of display pixels; (A positive integer of 2 or more) A first gradation pattern generation circuit for generating a first gradation pattern for obtaining one display gradation in a frame period, and a second floor for obtaining another display gradation in an m frame period. A second gradation pattern generating circuit for generating a gradation pattern; and, if the multi-gradation display data corresponds to a display gradation based on the first gradation pattern, a voltage level based on the first gradation pattern At least one voltage level or a voltage level adjacent to the one voltage level is selected and output, and if the multi-gradation display data corresponds to a display gradation based on the second gradation pattern, the second floor Based on the tone pattern Multi-gradation display, comprising: selection control means for selecting and outputting at least one voltage level among the voltage levels or another voltage level separated from the one voltage level by at least an adjacent voltage level. apparatus. 2. The multi-gradation display data according to claim 1 is k
A multi-gradation display device, which is a digital signal of (k is a positive integer greater than 2) bits. 3. The multi-gradation display device according to claim 2, wherein
A multi-gradation display device comprising a gradation voltage generation circuit for supplying a voltage level lower than ^{k + 1} . 4. The multi-gradation display device according to claim 1, further comprising a light source and a light condensing unit for guiding the light source light from the light source to the display panel. . 5. The multi-gradation display device according to claim 1, wherein the first gradation pattern generation circuit and the second gradation pattern generation circuit control m × m display pixels as one control unit. . 6. The first gradation pattern and the second gradation pattern according to claim 1, wherein one table composed of m × m pieces of gradation compensation data is composed of m sheets. Multi-gradation display device. 7. A multi-gradation display device according to claim 5, wherein the control units are arranged in a substantially square arrangement. 8. A multi-gradation display device, wherein each of the first gradation pattern and the second gradation pattern according to claim 6 is configured based on a magic circle or a complete magic circle. 9. A multi-gradation display method for displaying an image on a plurality of display pixels by selecting a predetermined voltage level according to input multi-gradation display data, wherein the multi-gradation display data is m frame periods. In the case where it corresponds to the display gradation based on the first gradation pattern for which one display gradation is obtained, at least one voltage level of the voltage levels or a voltage adjacent to the one voltage level based on the first gradation pattern. The second gradation pattern when the multi-gradation display data corresponds to a display gradation based on a second gradation pattern for obtaining another display gradation in m frame periods. On the basis of the above, at least one voltage level among the voltage levels or another voltage level separated by at least an adjacent voltage level from the one voltage level is selected and output. Method.