JP3347628B2 - Display panel and display device capable of resolution conversion - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display of an information processing system such as a computer, a word processor, a TV receiver, and a car navigation system, a viewfinder of a video camera, and a display panel used for a light valve of a projector. It belongs to the technical field, and particularly to the technical field of display panels and display devices capable of resolution conversion.

[0002]

2. Description of the Related Art In a dot matrix display panel having a fixed resolution, that is, a fixed number of pixels, when displaying an image having a resolution lower than the resolution of the display panel, a part of the display area of the display panel is displayed. Display is performed, and the remaining area is set as a non-display area.

Conversely, when displaying an image having a higher resolution than the resolution of the panel, a part of the image to be displayed is cut out and displayed in the entire display area of the display panel (virtual screen). . In this case, it is impossible to simultaneously display the entire image on the display panel (first method).

Therefore, there is a method of enlarging and displaying four dots as one pixel when the resolution is low. For example, resolution 12
If four dots are displayed as one pixel using an 80 × 1024 display panel, the display becomes 640 × 512, and a low-resolution 640 × 480 display can be performed with almost the same area as the display area (screen). However, this method cannot enlarge and display the entire 640 × 480 image on a display panel having a resolution of 1024 × 768 (second method).

In order to solve this problem, the present inventor thinned out a part of the image data and then enlarged the image data to the size of the display panel as much as possible (third method).
Method). (Japanese Patent Application Laid-Open No. H5-111934 and European Patent Publication No. 0540294) However, in order to reduce the image data, further improvement is required to prevent blurring of the displayed image and to eliminate unnaturalness. is necessary.

Japanese Patent Application Laid-Open No. 6-295338 describes a method (fourth method) of performing image data processing without thinning out image data.

[0007]

However, as described above, the first method cannot simultaneously display the entire image on the display panel.

Further, in the second method, only an enlarged display of a power of 2 can be performed, and in the third method, part of image data before processing is lost due to thinning.

In the fourth method, data processing such as calculation is complicated, and the image information processing circuit is complicated and large-scale, which hinders cost reduction of the apparatus.

[0010]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a display panel which can easily process image information and can be a low-cost display device.

Another object of the present invention is to provide a display panel and a display device which prevent blur of a display image and which do not change the thickness of characters and lines.

Another object of the present invention is to provide a display panel and a display device which are hardly affected by noise (jitter) of an input signal.

As a result of repeating many experiments and thinking and error, the present inventor overturns the conventional wisdom that the image information processing circuit plays a role of resolution conversion such as enlargement or reduction other than the power of two. The idea was to give the panel its role. The above object was achieved by providing a unique dot pattern on the panel.

According to the present invention, in a display panel comprising a plurality of dot patterns arranged in a horizontal direction and a vertical direction, the dot pattern comprises 16 dots constituted by a matrix of 4 rows and 4 columns. The width of the first and fourth rows in the 16 dots is greater than the width of the second and third rows, and the width of the first
The width of the row and the fourth row has a shape larger than the width of the second row and the third row, and the dot pattern can be evenly divided into at least two kinds of pixels by different combinations of the 16 dots; The at least two types of pixels have different areas from each other.

According to the present invention, a dot pattern composed of a plurality of dots, of which at least three dots have mutually different areas, is repeatedly arranged in a horizontal direction and a vertical direction, and is constituted by a combination of the dots. In a display panel in which display is performed with a pixel as a display unit, the dot pattern repeatedly arranged is
It consists of a first combination of the dots, can be evenly divided into m first pixels having an effective area S1, and consists of a second combination of the dots,
2 can be equally divided into n second pixels, and S1 <S2, m> n, and m / n ≠ 2a, (a
Is a natural number).

The present invention comprises a plurality of dots. If at least three of the dots have different areas, the dot patterns are repeatedly arranged in a horizontal direction and a vertical direction, and are constituted by a combination of the dots. In a display panel in which display is performed with a pixel as a display unit, the dot pattern repeatedly arranged is
It consists of a first combination of the dots, can be evenly divided into p first pixels having an effective area S1, and consists of a second combination of the dots, the effective area S
2 can be equally divided into q second pixels, and can be further divided into r third pixels having an effective area S3, which are composed of a third combination of the dots. , S1 <S2 <S3, and p>q> r, and p
/ Q ≠ 2a and p / r = 2a, where a is a natural number.

[0017]

A display panel having a pixel region composed of two or more types of dots having different areas,
The pixel area comprises a first combination of the dots;
It can be evenly divided into the first pixel having the effective area S1, and at the same time, can be equally divided into the second pixel having the effective area S2 , which is composed of the second combination of the dots , and S1 <S2, and √S2 / √S1 ≠ b: meeting the (b natural number), and wherein the.

[0019]

[0020]

(Operation) According to the present invention, a pixel serving as a display unit can be formed by appropriately selecting a combination necessary for obtaining a desired resolution from a plurality of dots having different effective areas. Therefore, the effective area of the pixel is not limited to a power of 2 and can be enlarged or reduced, so that a desired resolution can be obtained. As described above, since the display panel itself has the dot pattern that can be converted in resolution, the image information processing circuit does not need to perform complicated processing such as arithmetic. Therefore, it is not necessary to perform resolution conversion by conventional digital interpolation processing or signal processing such as oversampling, thereby preventing blurring of a displayed image, keeping the thickness of characters and lines unchanged, and reducing noise (jitter). This has the effect of eliminating the influence of.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a part of a pixel array of a display panel according to a preferred embodiment of the present invention.

[Dot Pattern] The display panel used in the present invention has a dot pattern (also referred to as a pixel pattern) as described below.

The minimum units of the dot pattern are three types of dots, a dot having the smallest area (sometimes called a sub-pixel) px1, a dot px2 having a larger area, and a dot px3 having the largest area. Independently takes either a bright or dark state. Here, in order to facilitate understanding, the ratio of the area of each dot is set to 1: 2: 4 in ascending order.
It will be described as.

When these dot patterns are appropriately combined, a pixel having a predetermined effective area is obtained.

The minimum unit pixel viewed from the display information is
There are three types as shown in FIGS.

The first pixel is one side y of dot px3.
The second pixel is a part of one side y2 composed of a dot px3, two dots px2, and one dot px1, and the third pixel is one dot px3, four dots px2, and four dots One side y3 composed of dot px1
Part. The ratio of one side of each pixel is 2: 3: 4 in ascending order, and the area ratio is 4: 9: 16.

In addition, the first pixel can be constituted by two adjacent dots px2 and also by four adjacent dots px1. Thus, the first pixel can be represented by a combination of three different types of dots (see DF1 in FIG. 2).

In this display panel, the second pixel can be represented only by the above-mentioned unique combination of dots (see DF2 in FIG. 2).

The third pixel can be expressed by a combination of two adjacent dots px1 and four dots px2 in addition to the combination of the dots described above (see FIG. 3).

As shown in FIG. 2, when a combination pattern of dots on one side y4 consisting of four dots px3, eight dots px2, and four dots px1 is considered as a basic pattern, the basic pattern is nine first ones. It is equally divided into pixels, and equally divided into four second pixels.

On the other hand, when a pattern having four sides adjacent to each other and having a side of 2y4 is considered as a basic pattern, this basic pattern is equally divided into 36 first pixels and 16 second pixels. Not only can it be divided equally into pixels, but also equally into nine third pixels, as shown in FIG.

The ratio of one side of each pixel used in the present invention is:
It is appropriately determined according to the required resolution. In addition to the above-described 2: 3 and 2: 3: 4, 3: 4, 3: 5,.
・ 2: 5, 4: 5, 4: 6, 5: 6, 5: 7, ...
And the like. In terms of area ratio, 4: 9, 4: 9:
16, 9:16, 9:25, ..., 4:25, 16:
25, 16:36, 25:49,... To increase versatility, VGA, SVGA, XGA, S
The XGA may be set so as to be suitable for the required resolution.

That is, in a display panel having a pixel region composed of two or more types of dots having mutually different areas, the pixel region can be equally divided into the first pixels having the effective area S1, and at the same time, the effective area S1 can be divided. It can be divided into second pixels having an area S2, S1> S2, and the ratio of their square roots is not a natural number, that is, √S1 /
It is preferable to satisfy {S2} b (b: natural number).

[Resolution Conversion] First, in order to facilitate understanding, a high resolution first display mode in which the first pixel PL1 is a display unit pixel and a low resolution first display mode in which the second pixel PL2 is a display unit pixel. Switching between the second display mode and the second display mode will be described with reference to FIG.

It is assumed that the display panel has 320 basic patterns each having a side of y4 arranged in the horizontal direction and 240 in the vertical direction. Then, the first pixel PL1 becomes 9 in the horizontal direction.
60, and 720 in the vertical direction. Similarly, 640 second pixels PL2 are arranged in the horizontal direction and 480 are arranged in the vertical direction.

Therefore, if display is performed using the second pixel PL2 as a display unit pixel, a so-called VGA (640 × 48)
0) A display image of the corresponding display data can be formed. (FIG. 4
On the other hand, if the first pixel PL1 is a display unit pixel, the resolution is 960 × 720, which is larger than the resolution of SVGA (800 × 600).
The display image can be formed by making the most effective use of the GA image in the display area (screen) (see DT2 in FIG. 4). Of course, in the case of a color display device, the same number of display unit pixels are red,
It exists for each color of blue and green.

On the other hand, all the pixels are the pixels PL2
If the display panel is a VGA-compatible display panel composed of only a single dot having the same area as that of the above, the display of SVGA is insufficient for 160 dots in the horizontal direction and 120 dots in the vertical direction. It cannot support SVGA, and in any case, it is not possible to simultaneously display all the images of SVGA (see DTP in FIG. 4).

Next, a first display mode of high resolution using the first pixel PL1 as a display unit pixel, a second display mode of intermediate resolution using the second pixel PL2 as a display unit pixel, and a third pixel The case where three are switched between the low resolution third display mode in which is a display unit pixel will be described.

One side of the display panel is 2y4 (= 3y3).
There are 214 basic patterns in the horizontal direction and 16 basic patterns in the vertical direction.
It is assumed that 0 are arranged. Then, the first pixel PL1
Are arranged in 1284 × 960. Similarly, 856 × 640 second pixels PL2 are arranged. Further, the third pixel PL3 is 642 × 480.
Will be arranged. Therefore, the third pixel PL
If 3 is a display unit pixel, display with a resolution corresponding to a so-called VGA can be performed. On the other hand, if the second pixel PL2 is used as a display unit pixel, an SVGA image can be displayed, and the first pixel can display an image with a resolution corresponding to XGA (1024 × 768).

On the other hand, a resolution of 1280 × 9 composed of only a single dot having the same area as the first pixel PL1.
The 60 panel can display XGA if one dot is one pixel, and can display VGA if four dots are one pixel. However, if one dot is one pixel and SVGA is displayed, 480 pixels are displayed in the horizontal direction. In this case, a pixel of 600 minutes in the vertical direction becomes a non-display area. On the other hand, in the present invention, if SVGA display is performed using the second pixel PL2, the horizontal direction 56,
Only pixels for 40 minutes in the vertical direction are non-display areas.

In the specific example of the conversion method described above, the display mode of the lowest resolution is selected so as to be suitable for the resolution of the VGA, but the display mode of the high resolution is XGA or SXGA (1
280 × 1024) can be determined as appropriate.

For example, the basic pattern shown in FIG.
If six pixels are arranged, the resolution becomes 1026 × 768 in the display mode using the first pixels, which is almost equal to the resolution of XGA. On the other hand, if the second pixel is used, the resolution in the second display mode becomes 684 × 512, and a VGA image can be displayed.

On the other hand, a resolution of 1024 × 7 composed of only a single dot having the same area as the first pixel PL1.
The panel 68 can perform XGA display with one dot as one pixel, but when performing VGA display, the 38
4. There is no choice but to hide the pixels in the vertical direction 288 or use a virtual screen with four dots as one pixel.

Further, according to the present invention, the resolution of the first pixel PL1 is 2400 × 1800 (135 DPI) and the second pixel PL
2 can be switched at 1600 × 1200 (90 DPI).

As described above, in the present invention, the dot pattern itself of the display panel is designed in accordance with the resolution selected by the information processing device such as a computer.
The number of pixels (or the area of the pixels) in one display mode is not a multiple of 2 in the other, and even if a plurality of display modes are adopted, the non-display area becomes large or the entire image can be displayed. No worries.

[Display Panel] The display panel to which the present invention can be applied is an electrochromic display panel, a liquid crystal display panel, a plasma display panel, or an FED having an electron emission source.
(Field Emission Display) panel, DMD (Digital Micromirror Device) panel with micro mirror, L
Examples include a panel having a light emitting element array such as an ED.

In particular, the liquid crystal display panel is effective because it consumes relatively little power and is easy to reduce in size and weight and has a large area, and includes a simple matrix type, a TFT active matrix type, and an MIM type. In particular, the present invention can be preferably applied to a simple matrix type panel using a chiral smectic liquid crystal, which is a ferroelectric liquid crystal or an antiferroelectric liquid crystal, because it is easy to increase the screen size and the definition. In the present invention,
U.S. Pat. Nos. 4,655,561 and 5,091,72
A structure similar to the structure of the ferroelectric liquid crystal display panel described in detail in Japanese Patent No. 3,189,536 or the like can be adopted.

Also, Proceedings of the 15th Internat
ional Display Research Conference, Oct. 1995, pp259-2
The present invention can also be preferably applied to a liquid crystal display panel using a bistable twisted nematic (BTN) liquid crystal described in 62. The BTN liquid crystal exhibits two meta-stable states, which perform display by corresponding to light and dark.

The effective area of the dot used in the present invention is:
In the case of a simple matrix type liquid crystal display panel, the area is defined by the area where the scanning electrode and the signal electrode face each other. In the case of an active matrix panel, the area is defined by the area where the common electrode and the pixel electrode (drain electrode) face each other. Is done. The present invention is not limited to these panels, and the effective area of the dots of the present invention may be the area of a portion defined by a light shielding member such as a black matrix. In the case of a plasma display or FED, the area is defined by the area of a portion where a light-emitting body such as a phosphor is arranged.

[Gradation Display] The display panel of the present invention can display a halftone image by processing an image information signal containing gradation information. This can be achieved by modulating at least one of the voltage applied to the optical modulation element (liquid crystal, electron source, mirror, etc.) and the pulse width of the pixel in accordance with the gradation information. Specifically, in the case of a display panel using a TN liquid crystal, the voltage applied to the liquid crystal of the pixel may be modulated according to the gradation information.

On the other hand, in the display panel of the present invention, a predetermined dot is further divided into a plurality of dots (sub dots).
Area gradation display in which bright dots and dark dots are formed in pixels to modulate luminance is more preferable. Such an area gradation display is suitable for a display panel having a property of selectively exhibiting two optical states (bright and dark), in particular, a display panel having a memory property, and more specifically, a ferroelectric liquid crystal display. Panel or BTN liquid crystal display panel.

In the area gradation display used in the present invention, it is preferable to select a plurality of resolutions so that the number of gradations is the largest in the main resolution pixel. Further, it is desirable that the dot dividing method is to divide the dot into dot patterns in which the center of gravity of the brightness is hardly changed when the gradation level changes. Such a dividing method is described in EP-A-06716.
No. 48 publication.

In the present invention, the area ratio of the sub dots is adjusted so that such a dividing method can be applied to a case of a certain resolution. For example, the dots are divided such that the number of gradation levels is 4 in the case of display by the first pixel and 16 in the case of display by the second pixel.

The second pixel of low resolution is divided so that the division ratio is a power of 2, and the first pixel of high resolution is divided so that the division ratio does not have to be a power of 2. You can also.

More specifically, the number of display gradations by the first pixel PL1 is 2, the number of display gradations by the second pixel PL2 is 16, and the number of display gradations by the third pixel PL3 is 3. You can also.

[Color Display] In the present invention, in the self-luminous display panel, the color of the color forming body is made a plurality of colors,
In a display panel that controls light transmittance and reflectance,
By providing a color filter, color display can be performed. The color of the color former and the filter may be three primary colors of red (R), green (G), and blue (B), or may be complementary colors of yellow (Y), magenta (M), and cyan (C). In the case of a special use for reproducing a specific color, other colors may be used. Further, a pixel without coloring may be further provided in order to increase white luminance. In particular, the present invention is suitable for a display panel using a color filter, and the plane shape and effective area of each dot are defined by each color element of the color filter and a light shielding member such as a black matrix.

FIG. 5 is a plan view showing a part (basic pattern) of the display screen of the color display panel. As can be seen from comparison with FIG. 1, each dot is divided into three color dots of different colors. The state of the resolution conversion is the same as that shown in FIGS. Here, the image is divided into three colors. However, as described above, the image may be divided into two or four or more colors for special purposes.

[Driving] FIG. 6 is a block diagram showing a driving control device of a display device used in the present invention. Reference numeral 30 denotes a display panel having the above-described configuration, and IDVR denotes a display panel 30.
Information line driving means for supplying a signal to the information line
Denotes scanning line driving means for supplying signals to the scanning lines of the display panel 30. These drive means are drive control means D
A signal controlled by the CNT and corresponding to the image information to be displayed is received from the signal processing means SPCR.

The image information input from the input terminal IN is subjected to detection of the display resolution and conversion into a signal corresponding to each dot of the display panel by the signal processing means SPCR. These converted signals are input to the driving means IDVR and SDVR. The driving means IDVR and SDVR generate voltage pulses suitable for driving the display panel in accordance with an input signal, and supply them to the scanning lines and the information lines.

The driving means IDVR desirably has a shift register function, a memory function, a switch function for determining a pulse width, and the like.

The driving means SDVR desirably has a decoder and a switch function for determining a pulse width. If necessary, a memory and an address detection circuit may be added.

The signal processing means SPCR only needs to have a function of detecting the resolution and have a function of associating the original information with the dots of the display panel according to the detection result. If the resolution information is input together with the image information in advance, the association may be made according to the information.

[0065]

Hereinafter, embodiments of the present invention will be described.
The present invention is not limited to each of these embodiments, and those in which each component is replaced with an alternative or equivalent thereof are within the scope of the present invention as long as the object of the present invention is achieved. included.

(Embodiment 1) The display device according to Embodiment 1 is
A resolution detection circuit that detects the vertical and horizontal resolution of an input image signal, an image conversion circuit that converts input data into image information corresponding to writing of pixels on a scanning line and is capable of switching a plurality of conversion methods, and a scanning line that scans Make a selection and
A scanning line selection circuit capable of switching a plurality of selection methods, when the resolution detection circuit detects a first resolution mode,
One pixel is composed of a plurality of sub-pixels, and has a ratio of electrode widths so that a plurality of gradations can be expressed by a combination of lighting of the sub-pixels, and a part of the sub-pixels is used in the second resolution mode. A matrix electrode having an electrode width ratio such that a pixel having a size different from that of the first resolution mode is formed by using or a combination of the pixel and a sub-pixel of an adjacent pixel; By providing control means for controlling the conversion method of the image conversion circuit and the selection method of the scanning line selection circuit according to the resolution mode detected by the circuit, the display of the matrix display device can be adjusted in accordance with the resolution mode of the image output from the personal computer. The resolution itself changes, and multiple resolution modes that are not integral multiples or Also it is intended to enable the entire screen, or display it in the near size.

FIG. 7 is a block diagram showing the entire system of the display device of this embodiment. In the figure, reference numeral 10 denotes an input of an image signal from a computer, a work station, or the like, a digital RGB signal, a horizontal synchronization signal (HSYNC), a vertical synchronization signal (VSYNC), and a pixel clock (PCLK).
An image processing circuit for converting digital RGB signals into image information corresponding to writing to pixels on scanning lines of a display panel, which will be described later;
Reference numeral 3 denotes a motion detecting circuit for detecting which line of the image has been rewritten and transmitting the line to the display controller 17, and 14 determines the vertical and horizontal resolution of the image signal and determines the display mode (DMOD).
E) a display mode detection circuit that transmits the data to the display controller 17 and the drive control circuit 20. The display mode detection circuit 15 stores data output from the image processing circuit 11 in the frame memory 16, and reads one line of data from the frame memory.
A line output control circuit which outputs image information (PD0-15), and 17 is a display controller formed by a microcomputer.

Reference numeral 20 denotes a drive control circuit formed by a one-chip microcomputer, reference numeral 21 denotes a delay circuit for delaying transfer of image information corresponding to writing to pixels on a scanning line, and reference numeral 22 denotes serial-parallel conversion of image information. A shift register; 23, a line memory for storing image information corresponding to writing to pixels on one scanning line; 24, an information signal generating circuit for generating a drive waveform voltage based on the image information;
Reference numeral 5 denotes an address detection circuit for detecting address information for specifying a scanning line, 26 denotes a decoder for decoding the scanning line address information detected by the address detection circuit 25 and specifies a scanning line to be selected, and 27 denotes a designation from the decoder. A memory for storing scanning line information; 28, a decoder 26 and a memory 27;
A scanning signal generating circuit for generating a driving waveform voltage so that each of the designated scanning lines is driven based on the designated scanning line information from the matrix electrode; a matrix electrode formed of the scanning lines and the information lines; It is a display panel provided with a liquid crystal.

FIG. 8 is a diagram showing the configuration of the display panel 30 according to the first embodiment. 31a-r are information line electrodes, and 32a-i are scanning line electrodes. The numbers shown above the information line electrodes and to the left of the scanning line electrodes represent the width ratios of the respective electrodes. The information line electrode is 10: 10: 10: 5: 5: 5: 5: 5: 5: 10: 1 from the left end.
The width of each electrode is determined so that the ratio of 0:10 is continuous, and the width of each scanning line electrode is set so that the ratio of 21: 9: 15: 15: 9: 21 is continuous from the upper end. Is determined.

FIG. 9 is a diagram showing a state in which RGB color filters are formed on the display panel of FIG. The striped color filters are formed on the information line electrodes, respectively, and are arranged in the order of RGBRGBRGBRGBRGB from the left end. The numbers in the figure indicate the area ratio of each information line electrode and the area where each scanning line electrode overlaps, and this area is hereinafter referred to as "dot" for convenience.

The dots are shielded between the dots by a light shielding member as necessary.

The operation of the display device of the present invention will be described below with reference to FIG.

The image signal input circuit 10 to which RGB video data is input from a computer or a workstation receives an RGB digital signal and a timing signal (horizontal synchronization signal = HSYNC, vertical synchronization signal = VSYNC, pixel clock = CLK) by an image processing circuit 11. , Motion detection circuit 1
3. Output to the display mode detection circuit 14.

(Motion Detection Circuit) The motion detection circuit 13 reads the image of the previous frame stored in the frame memory 12 at the same time as inputting the RGB digital image in accordance with the timing signal, and performs a comparison for each pixel. If there is a pixel in one horizontal line in which the difference between the previous frame and the current frame is larger than a predetermined “threshold”, the number of that line is used as a motion detection signal (MD) and the scanning controller Output to

(Display Mode Detection Circuit) The display mode detection circuit detects vertical and horizontal resolutions from the timing signals (horizontal synchronization signal, vertical synchronization signal, pixel clock).
It is transmitted to the display controller 17 and the drive control circuit 20 as display mode information (DMODE).

(Image Processing Circuit) The image processing circuit 11 as a signal processing means in the present invention inputs an RGB digital image in 4 bits for each of RGB in accordance with the above-mentioned timing signal, and also supports writing to pixels on a scanning line of a display panel. To the converted image information.

FIGS. 10 and 11 are diagrams showing the conversion performed by the image processing circuit 11 and the state of the line data generated. The image processing circuit 11 receives an instruction (I
MODE), three types of conversion are performed.

When IMODE = 0, as shown in FIG. 10, two lines of data LD are obtained from one line of input data.
(2n) and LD (2n + 1) are generated. And RGB
, The upper two bits are LD (2n) and the lower two bits are L
The conversion is performed so as to be assigned to the D (2n + 1) line (P1R3 in the figure indicates bit 3 of R (red) of the first pixel, and P2G1 indicates bit 1 of G (green) of the second pixel. .).

When IMODE = 1, output data (LD) for one line is generated from input data for one line using only the upper one bit of each data of RGB. From the first (left end) pixel data, the upper 1 bit of RGB is set to 1
And the next pixel data is assigned two upper 1 bits of RGB data. Further, an output line is generated from the next pixel data such that one upper bit is assigned one by one. Assignment for each pixel is as follows: first pixel = RGB second pixel = RGB × 2 third pixel = RGB fourth pixel = RGB fifth pixel = RGB × 2 sixth pixel = RGB.

When IMODE = 2, one line of output data (LD) is generated from one line of input data using all four bits of RGB data. R of each pixel
Each data of GB (values of 0 to 15) is converted by a table to generate an output line. The input of FIG. 12 is the value of each color of each pixel (for example, P1R in FIG. 11), and a and b
Are, for example, P1Ra and P1R when the value of P1R is input.
corresponds to the value of b.

(Line Output Control Circuit) The line output control circuit 15 stores in the frame memory 16 image information output from the image processing circuit 11 and corresponding to writing to pixels on the scanning lines of the display panel. Further, in response to the FHSYNC signal input from the drive control circuit 20, one line of data is read from the frame memory, and the image information (PD0
-15) and the scanning line address information (= line number) of the image information. At this time, which line of image data to output is determined by an instruction from the display controller.

(Operation of Display Control Controller) The display controller 17 determines a scan line of “refresh scanning = interlace scanning” of the display panel which is always performed, and responds to a motion detection signal (MD) from the motion detection circuit 13. The scanning line of “partial rewriting = non-interlace scanning” for displaying the changed line preferentially on the display panel is determined, and an instruction to the line output control circuit 15 is given.

FIG. 13 shows a flag memory included in the display controller. The flag memory has a bit amount corresponding to the number of scanning lines of the display panel, and there is one bit corresponding to each line.

The display controller determines the line to be output according to the processing shown in FIG. 14 and instructs the line output control circuit 15. The operation will be described below with reference to FIG. First, the display controller sets the flag bit for one field of refresh scan to 1 in the flag memory as shown in FIG. These flag bits in which 1 is set correspond to all lines to be output in the next one-field refresh scan. For example, if the refresh scan is a three-field interface scan, the first field = 0, 3, 6,. 9, 12, 15, 18
... Second field = 1, 4, 7, 10, 13, 16, 19
..... 3rd field = 2, 5, 8, 11, 14, 17, 20
・ ・ ・ ・ ・ Since scanning is performed in the order of, for example,
If field scanning is to be performed, 1 is set to the bits corresponding to the lines 0, 3, 6, 9, 12, 15,... In the flag memory. When the scan controller 17 finishes setting the bit in the flag memory, it looks at the contents of the flag memory in order from the top line (line 0) and finds a bit in which 1 has been set, and when the bit corresponding to the bit is set, It instructs the line output control circuit 15 to output data.

When the display controller 17 receives the motion detection signal from the motion detection circuit 13, the display controller 17 sets the bit indicating the corresponding line of the flag held therein to 1 by interrupt processing as shown in FIG. Therefore, in the process shown in FIG. 14, for example, when a motion is detected from line 10 to line 15, 0, 3, 6, 9, 10, 1
Scanning is performed in the order of 1, 12, 13, 14, 15, and 18. Lines 10 to 15 are displayed in a non-interlaced manner instead of a three-field interlaced scanning.

(Delay circuit, drive control circuit) The drive control circuit 20 sets the FHSYNC signal to "L" during the period T1 in FIG.
Level to inform the line output control circuit that data can be accepted. The line output control circuit detects the fall and transfers the AH / DL signal in synchronization with the PD0-PD15 (image information and scanning line address information) and the FCLK signal. Since the AH / DL signal transfers image information and scanning line address information on the same transmission line, it is also used as its identification signal. PD0-PD15 transferred during the period in which the AH / DL signal is at the "H" level indicate scanning line address information, and the period at the "L" level indicates image information. The drive control circuit 20 uses the AH / DL as a delay enable trigger signal (DE) to the delay circuit 21 so that the image information (L) of the image information and the scanning line address information transferred from the line output control circuit 15 can be used.
Only D) is transferred to the delay circuit 21 in synchronization with FCLK. Conversely, the address detection circuit 25 detects only the scanning line address information.

Then, the drive control circuit 20 outputs a drive start signal (ST) and latches the contents of the shift register 22 in the line memory 23. At the same time, the scanning line address information is transferred from the address detection circuit to the decoder 26 at this timing, the address information is decoded, and the erase line is designated.

FIG. 17 is a timing chart of the application of the driving voltage, and FIG. 18 shows the voltage waveform of each signal.

This period T1 corresponds to 1H (time to rewrite one line). In the period T2, the driving is started by the driving start signal output from the driving control circuit. The scanning line erased at this time is a line designated by the decoder 26 (corresponding to L1 in this case), and the scanning line on which image information is simultaneously written is a line set in the memory 27 (corresponding to L0 in this case). is there. The set lines L0 and L1 are simultaneously driven by the scanning signal generation circuit 28, respectively.

At this time, the driving voltage applied to the scanning line L1 corresponds to the "erase phase portion" shown in FIG. 17, and the driving voltage applied to the scanning line L0 corresponds to the "writing phase portion" shown in FIG. ". FIG. 17 shows a scanning selection signal having voltage peak values V1, V2 and V3 and a voltage 0
Are shown.

On the other hand, the drive control circuit 20 outputs the next information PD0
-FHSYNC is set to "L" to receive the PD15, and information from the line output control circuit is received. Image information (corresponding to L2) is transferred to the delay circuit 21 in the same manner as described above.
At the same time, the previous image information (corresponding to L1) is transferred to the shift register 22. Then, the address detection circuit 25 detects the scanning line address information (corresponding to L2). And
The drive control circuit outputs a drive start signal (ST) and latches the image information (equivalent to L1) of the shift register 22 in the line memory. At the same time, the scanning line address information (corresponding to L2) is transferred to the decoder 26 at this timing, and the designation of the scanning line L1 is set in the memory 27. Similarly, during the period T3, the pixels of the scanning line L2 are erased and the scanning line L
The pixel on the line 1 is rewritten to black or white according to the value of the image information L1 stored in the line memory 23. Scanning of the display panel is performed in such a procedure.

(Decoder) FIG. 19 is a diagram showing the decoder 26. The decoder converts the scanning line address information designated by the address detection circuit 25 into a selection signal (S0-11) for activating a circuit corresponding to the scanning line actually driven by the scanning signal generation circuit. The decoder performs different conversions according to SMODE from the drive control circuit. FIGS. 20 and 21 show the contents of conversion when SMODE = 0-2. The left column shows the scanning line address input by the decoder, and the right column shows which scanning line is selected at that time. In the figure, 1 = selection, 0
= Not selected. For example, when address = 0 is input when SMODE = 0, S0 and S2 become "1", indicating that the 0th and 2nd scanning lines are selected simultaneously. This corresponds to 32a and 32c in FIG.

The scanning signal generation circuit 28 receives scanning line selection signals from both the decoder 26 and the memory 27. The erasing phase portion of the scanning selection signal is output to the scanning line that has been "selected" by the decoder, and the output from the memory 27, that is, the scanning line that has been "selected" 1H (a period during which one line is rewritten) by the decoder. , A waveform corresponding to the writing phase portion of the scanning option is output. Further, a non-selection signal is output to a scanning line in which the outputs from the decoder and the memory are both “non-selected”.

The information signal generating circuit outputs two waveforms corresponding to the image information input from the line memory 23. For example, if the bit corresponding to a certain information line is 1, a bright waveform is output for the information line and “bright” is displayed on the display panel.
Becomes On the other hand, if the value is 0, a dark waveform is output to the information line, and it becomes "dark" on the display panel.

The following is a description of the DM output from the display mode detection circuit.
An OMODE signal, an IMODE signal output from the display controller to the image processing circuit, an SMODE signal output from the drive control circuit to the decoder 26, and OFFS output from the display controller to the line output control circuit.
The relationship between ET signals is shown.

[0096]

[Outside 1]

In the following, the resolution of the host computer is H =
A display operation of the display device of the present invention when a signal having a resolution of 1024 and V = 768 is output will be described. The display mode detection circuit outputs a signal of DMODE = 0 from the timing of the input signal. In response,
The display controller sends an IMOD to the image processing circuit.
E = 0 is output. The image processing circuit converts image data as shown in FIGS. 10 and 11, and two lines of data are generated for one line input. On the other hand, the drive control circuit outputs SMODE = 0 to the decoder 26, and the decoder outputs a scan selection signal. FIG. 22 shows a size corresponding to one pixel on the display panel at this time.
One pixel is a pixel capable of expressing 16 gradations (= 4096 colors) of RGB colors R0 to R15 as shown in FIG. Hereinafter, the manner in which the gradation expression is performed using the case of red (R) as an example will be described.

First, when the data of the left end pixel of line 0 input by the image processing circuit 11 is R = 1, G = 0, B = 0 (each value is 0 to 15), the content of pixel1 is P1
Only R0 is "1", and all others are "0". (1
Therefore, the two lines of data output from the image processing circuit are LD (0): 000000... LD (1): 000100... From the left end, and are stored in the frame memory 16.

On the other hand, when these lines are output by the line output control circuit, the line addresses 0 and 1 are detected by the address detection circuit and input to the decoder. When address 0 is input to the decoder, S0,
S2 is selected, which means that scanning line 0 and scanning line 2 are selected at the same time. (Corresponding to 32a and 32c). At the same time as the output of this decoder is set in the memory 27, the image data (corresponding to the LD (0)) is set in the line memory, and the information lines (31a, 31b, 31c, 31) are set.
d, 31e, 31f ...) from the left end to 000000
A waveform corresponding to the data of... Is output. On the other hand, when address 1 is input to the decoder, S1 is selected, which means that scanning line 1 is selected (32).
b)). When the output of this decoder is set in the memory 27, the image data (the LD
(Corresponding to (1)) is set and the information line is 000 from the left end
A waveform corresponding to the data 100... Is output. When these two writing scans (2 lines + 1 line) are completed, only one dot becomes “bright” and the other dots become “dark” as shown at R = 1. This portion has an area ratio of “1” and has a brightness of “1” in 16 gradations from 0 to 15.

If the data of the left end pixel of line 0 input by the image processing circuit 11 is R = 12, G = 0, B = 0 (each value is 0 to 15), the contents of pixel1 are P
1R3 and P1R2 are "1", and all others are "0". (12 = 1100 in binary) Therefore, two lines of data output by the image processing circuit are LD (0): 100100... LD (1): 000000.

When these lines are output by the line output control circuit, the line addresses 0 and 1 are detected by the address detection circuit and input to the decoder.
When address 0 is input to the decoder, S0 and S2 are selected, which means that scanning line 0 and scanning line 2 are selected at the same time. (Corresponding to 32a and 32c). At the same time as the output of this decoder is set in the memory 27, the image data (corresponding to LD (0)) is set in the line memory, and the information lines (31a, 31b, 31c, 31d, 31) are set.
e, 31f ...) are 100100 ... from the left end
Is output. On the other hand, when address 1 is input to the decoder, S1 is selected, which means that scanning line 1 is selected (corresponding to 32b). At the same time as the output of this decoder is set in the memory 27, the image data (corresponding to the above LD (1)) is set in the line memory, and the information line is 000000
A waveform corresponding to the data of... Is output.

When these writing scans are completed, as shown at R = 12, four dots become “bright” and the other dots become “dark”. This part has an area ratio of “4.66”
+ 3.33 + 2.33 + 1.66 = approximately 12 ”becomes“ bright ”and“ 1 ”in 16 gradations from 0 to 15
2 "brightness.

Similarly, according to the input data, 0 to 15
Are displayed.

When the resolution of the host computer is H =
When a signal having a resolution of 1536 and V = 1152 is being output, the display mode detection circuit outputs a signal of DMODE = 2 from the timing of the input signal. In response, the display controller outputs IMODE = 1 to the image processing circuit. The image processing circuit is shown in FIG.
The image data is converted as shown in (1), and data for one line is generated for one line input. On the other hand, the drive control circuit outputs SMODE = 2 to the decoder 26, and the decoder outputs a scan selection signal. FIG. 24 shows a size corresponding to one pixel on the display panel at this time, and one pixel is a pixel having two gradations (= 8 colors) of RGB colors as shown in FIG. Hereinafter, a state in which the gradation expression is performed using blue (B) as an example will be described.

First, the data of the left end pixel of line 0 input by the image processing circuit 11 and the data of the pixel to the right thereof are both R =
0, G = 0, B = 3 (each value is 0 to 15),
As for the contents of pixel1, P1B1 and P1B0 are "1", and all others are "0". pixel2 is also P2B1 and P2B
0 becomes “1”, and all others become “0”. IMODE
When = 1, only the most significant bit of the 4-bit data is used. Therefore, one line of data output by the image processing circuit is LD (0) = 00000000000... And is stored in the frame memory 16.

When this line is output by the line output control circuit, line address 0 is detected by the address detection circuit and input to the decoder. When address 0 is input to the decoder, S0 and S1 are selected,
This means that scanning line 0 and scanning line 1 are selected.
(Corresponding to 32a and 32b). At the same time when the output of this decoder is set in the memory 27, the image data (corresponding to LD (0)) is set in the line memory, and the information line (3
1a, 31b, 31c, 31d, 31e, 31f ...
..), a waveform corresponding to data of 000000000... From the left end is output. The writing scan of these two lines is performed simultaneously during one line scanning period.
= 0, all dots are "dark". This is the brightness of "0" among the two gradations of 0-1.

The data of the left end pixel of line 0 and the data of the pixel on the right side of the line 0 input by the image processing circuit 11 are both R =
If 0, G = 0, B = 14 (each value is 0 to 15), the contents of pixel1 are P1B3, P1B2, P1B
1 becomes “1” and the others become “0”. As for the contents of pixel2, P2B3, P2B2, and P2B1 are "1", and the others are "0". As shown, when IMODE = 1, only the most significant bit of the 4-bit data is used. Therefore, one line of data output by the image processing circuit is LD (0): 00100100100... And is stored in the frame memory 16. You.

When this line is output by the line output control circuit, it is detected by the line address detection circuit and input to the decoder. When address 0 is input to the decoder, S0 and S1 are selected, which means that scanning line 0 and scanning line 1 are selected (32a, 32).
b)). The output of this decoder is set in the memory 27, and the image data (corresponding to the above LD (0)) is set in the line memory at the same time as the writing scan is performed, and the information lines (31a, 31b, 31c, 31d, 31e, 31f
・ ・) Is 00100100100
A waveform corresponding to the data (corresponding to LD (0)) is output. These two lines are simultaneously written and scanned during one line scanning period. As a result, as shown in B = 1, all blue (B) dots become “bright”. This is 0
The brightness is “1” in the two gradations of “1”.

If the resolution of the host computer is H =
When a signal having a resolution of 768 and V = 576 is output, the display mode detection circuit outputs a signal of DMODE = 1 from the timing of the input signal. In response to this, the display controller sends an I
MODE = 2 is output. The image processing circuit converts the image data as shown in FIG. 11 and generates one line of data for one line input. On the other hand, the drive control circuit outputs SMODE = 1 to the decoder 26, and the decoder outputs a scan selection signal. FIG. 26 shows a size corresponding to one pixel on the display panel at this time.
As shown in FIG. 27, one pixel has three gradations of RGB (= 2).
(7 colors). Hereinafter, a state in which the gradation expression is performed by taking the case of green (G) as an example will be described.

First, when the data of the left end pixel of line 0 input by the image processing circuit 11 is R = 0, G = 5, B = 0 (each value is 0 to 15), the content of pixel1 is P1
The a of G becomes “0”, the b of P1G becomes “1”, and all others become “0”. Therefore, one line of data output from the image processing circuit is LD (0): 000010010... And is stored in the frame memory 16.

When this line is output by the line output control circuit, line address 0 is detected by the address detection circuit and input to the decoder. When address 0 is input to the decoder, S0, S1, S2, S3
Is selected, and the scanning lines 0 to 3 are selected. (Corresponding to 32a to 32d). At the same time when the output of this decoder is set in the memory 27, the image data (corresponding to LD (0)) is set in the line memory, and the information lines (31a, 31b, 31c, 31d, 31e, 31f) are set.
.., A waveform corresponding to the data 0000001010... (Corresponding to LD (0)) is output from the left end. The writing scan of these four lines is performed simultaneously during one line scanning period, and as a result, as shown in G = 1, 8
One dot becomes “bright”. 0, 13 according to the area ratio.
The area of 13.33 out of 33, 26.66 is “bright”, that is, the brightness of “1” among the three gradations of 0, 1, and 2.

When the data of the left end pixel of line 0 input by the image processing circuit 11 is R = 0, G = 13, B = 0 (each value is 0 to 15), the contents of pixel1 are P
Both a and b of 1G are “1”, and all others are “0”. Therefore, one line of data output from the image processing circuit is expressed as LD (0): 01010010..., And is stored in the frame memory 16.

When this line is output by the line output control circuit, the line address 0 is detected by the address detection circuit and is input to the decoder. When address 0 is input to the decoder, S0, S1, S2, S3
Is selected, and the scanning lines 0 to 3 are selected. (Corresponding to 32a to 32d). At the same time when the output of this decoder is set in the memory 27, the image data (corresponding to LD (0)) is set in the line memory, and the information lines (31a, 31b, 31c, 31d, 31e, 31f) are set.
..) Are output from the left end. These four lines are simultaneously written and scanned during one line scanning period. As a result, as shown in G = 2, all green (G) dots are “bright”.
Becomes According to the area ratio, 0, 13.33, 26.66,
Of 26.66 in "." Is "bright", that is, the brightness of "2" in the three gradations of 0, 1, and 2.

When the resolution of the host computer is H =
Similarly, when a signal having a resolution of 640 and V = 480 is output, DMODE = 1, IMODE = 2, and SMO
DE = 1. In this case, the image is not displayed on the entire display panel, but when the line output control circuit stores the image data in the frame memory, X = 64 and Y = 48 on the frame memory are stored as the upper left corner in response to the OFFSET signal. Therefore, an image is displayed at the center on the display panel.

The contents described above are only examples of the present invention, and do not depend on the number of colors of the display panel in the essence of the present invention.

Hereinafter, an example in which the dot pattern of the display panel is changed in this embodiment will be described.

(Embodiment 2) FIG. 28 is a schematic plan view showing a part of a display panel according to Embodiment 2 of the present invention.

The difference from the first embodiment is that this display panel is for monochrome display, so that each pixel is composed of R, G, and B pixels.
Are not separated into the respective color pixels.

[0119] However, the gradation display is likewise performed so as Example 1, dots Px3 of both sides y ₁ 2 two pairs 4.66
One of the sub-dot, one side y ₁ other side y ₂ -y ₁ dot Px
2 is divided into 1: 2.33 subdots.

The numbers in the figures indicate the ratio of the effective area.

In FIG. 28, the first pixel of the first resolution is the first dot P composed of two subdots having an area ratio of 2: 4.66.
x3, and another first pixel is composed of two subdots having an area of 2.33 and two subdots having an area of 1, that is, a total of four subdots. Yet another first pixel consists of two subdots with an area of 3.33, and yet another first pixel consists of four subdots with an area of 1.66. The second pixel of the second resolution is a first dot, a second dot Px2 and a subdot Px1, which are composed of two subdots having an area ratio of 1: 2.33, and an area of 3.
It consists of a total of six sub-dots including three sub-dots.

Similarly, a total of 12 third pixels having the third resolution are obtained by adding three subdots having an area of 1, 2.33 and 3.33 and three subdots having an area of 1.66 to the second pixel. Of sub-dots.

The first pixel enables the scanning lines 32a and 32b to be independently selected, and supplies information lines 31a and 31b with sub-dots on the scanning line 32a or information signals corresponding to sub-dots on the scanning line 32b, respectively. By applying this, four-level gradation display can be performed.

At this time, dots Px having an area ratio of 1: 2.33
Two sub-dots having an area of 2.33 in the first pixel composed of a total of four sub-dots, each of which consists of two, have the same display state (bright and dark) for the same image information.
Similarly, the two sub-dots having the area 1 have the same display state for the same image information.

A case where display at the second resolution is performed using the second pixels will be described.

A sub-dot of area 4.66 and an area of 3.33
Have the same display state for the same image information. Similarly, a sub-dot of area 2.33 and an area of 1.6
The sub-dot 6 also has the same display state. Thus 1
6-level gradation display can be performed. As a specific driving method at this time, first, two scanning lines 32a and 32c are selected at the same time, and an information signal for brightening or darkening the sub dots of the areas 4.66 and 3.33 is transmitted. An information signal is supplied to the line 31a, and an information signal for lightening or darkening the sub dots of the areas 2.33 and 1.66 is supplied to the information line 31b.

Next, the scanning line 32b is selected, and similarly, an information signal is supplied to the information lines 31a and 31b, and the display state of the sub-dots of areas 1 and 2 is determined.

As a scanning method for all the scanning lines, a line-sequential scanning method for selecting at least one scanning line and supplying an information signal to all the information lines may be used. At this time, the order of selecting the scanning lines is 32 in the first field.
a and 32c, 32d and 32f, 32g and 32i..., two scanning lines are sequentially selected, and in the second field, 32b, 32e, and 32h scanning lines are sequentially selected one by one. A method of ending one frame scanning for selecting a scanning line is preferable.

In the case of performing display at the third resolution using the third pixel, for example, the scanning lines 32a and 32b are simultaneously selected, and the scanning lines 32c and 32d are simultaneously selected to form a square pixel ( _1st side) of y1. Brightness and darkness can be determined for each pixel, and a five-level gradation display can be performed. In addition, four scanning lines are simultaneously selected for one third pixel, and one third
It is also possible to divide three or two information lines per pixel into two sets and independently supply information signals to perform three-level gradation display.

Simultaneous selection means that a scanning selection signal is supplied to a plurality of scanning lines at the same time.

One of the characteristics of this embodiment is that three scanning lines (for example, 32 lines) in the second pixel of the second resolution are used.
a, 32b, 32c) is that the area ratio between the pixel on the scanning line 32a and the pixel on the scanning line 32c is not 1: 1 but unequal. Thus, when the scanning lines 32a and 32c are simultaneously selected to perform 16-level gradation display, a difference in brightness between the gradation levels hardly occurs.

For this purpose, three different sub dots (areas 2, 3.3) corresponding to the three scanning lines of the second pixel are used.
3, 4.66 three subdots or area 1, 1.6
6, 2.33), the sum (7.99 or 3.99) of the effective area of the other two subdots to the subdot of the smallest effective area is almost four times, for example, 3.9.
To 4.1. In this example, it is specifically set to 3.995 times or 3.990 times so as to approach 4 times.

Then, 3 corresponding to one information line 31b
The sum of the effective areas of one dot (4.99) is approximately twice the sum of the effective areas of three subdots corresponding to another information line 31a (9.99), for example, 1.9 to 2. It is set to 1 time. In this example, it is specifically set to 2.002 times so as to approach twice.

That is, in this example, a certain first pixel, for example, Px3, is divided into 2: 4.66, and a sub-dot having a large effective area, and an effective area of another adjacent first pixel of 3.x. The effective area is 2 with the sum of 33 sub dots.
Is about four times as large as that of the sub-dot.

Similarly, the first pixel effective area 2.33 2
Effective area of one sub-dot and another first pixel 1.66 2
The sum of the effective areas of the four sub-dots with the one sub-dot is about four times the sum of the effective areas of the two sub-dots of the effective area 1 of the certain first pixel.

The subdots of adjacent second pixels have substantially the same area. That is, FIG.
Medium, subdots d1 and d2, 3 and d4, d5 and d6, d
7 and d8,... D15d and d16, and d17 and d18 are all dots having the same effective area.

Thus, in the case of display at the second resolution using the second pixels, multi-levels of 16 levels can be displayed, and the center of gravity of the brightness in the vertical direction in the drawing, that is, in the scanning line arrangement direction. Fluctuations are suppressed.

If each sub-dot in FIG. 29 is further divided into color dots for each color, a color display panel is obtained. For example,
If the image is divided into R, G, and B colors, the result becomes the same as that in FIG.

(Embodiment 3) FIG. 29 is a schematic plan view showing a part of a display panel according to Embodiment 3 of the present invention.

The difference from the second embodiment is that the vertical length y
The division pattern of _one dot Px2, Px3 is that a sub-dot with a small area is arranged above and a sub-dot with a large area is arranged below.

Of course, these sub-dots may be further divided into color dots to enable color display.

(Embodiment 4) FIG. 30 is a schematic plan view showing a part of a display panel according to Embodiment 4 of the present invention.

The difference from the second embodiment is that the vertical axis is y ₁₁
+ Dots y ₁₂ is a point which is divided into upper and lower two sub-dot.

Of course, these sub-dots may be further divided into respective color dots so that color display can be performed.

(Embodiment 5) FIG. 31 is a schematic plan view showing a part of a display panel according to Embodiment 5 of the present invention.

The difference from the second embodiment is the division ratio into sub dots.

The numbers in the figure indicate the ratio of the effective area.

FIGS. 31 to 34 show the state of 16 gradation display in the standard mode, and FIGS. 35 to 38 show the state of 16 gradation display in the low resolution mode.

[0149]

As described above, according to the present invention, even when image signals of a plurality of resolutions are input to the same matrix display device, the size of one pixel changes in accordance with the resolution. A clear image in which 1 pixel on the image and 1 pixel on the panel correspond to each other, that is, a small display area, blurring or unnaturalness due to interpolation / thinning processing, which has conventionally been a problem. Instead, it is possible to always display the entire display panel or a size close to the size of the display panel.

[Brief description of the drawings]

FIG. 1 is a diagram showing a part of a pixel array of a display panel according to a preferred embodiment of the present invention.

FIG. 2 is a schematic diagram showing how pixel area conversion is performed by the display panel of the present invention.

FIG. 3 is a schematic diagram showing a state of pixel area conversion by the display panel of the present invention.

FIG. 4 is a schematic diagram showing how resolution conversion is performed by the display panel of the present invention.

FIG. 5 shows a part of a pixel array of a color display panel according to a preferred embodiment of the present invention.

FIG. 6 is a block diagram of a drive control device for a display panel according to a preferred embodiment of the present invention.

FIG. 7 is a block diagram of a display panel drive control device according to the first embodiment of the present invention.

FIG. 8 is a schematic diagram illustrating a configuration of a display panel according to the first embodiment.

FIG. 9 is a schematic diagram illustrating a part of a pixel array of the display panel according to the first embodiment.

FIG. 10 is a diagram for explaining a display information resolution conversion process according to the first embodiment.

FIG. 11 is a diagram illustrating a resolution conversion process of display information according to the first embodiment.

FIG. 12 is a diagram showing a logical table used for resolution conversion processing of the display information in FIG. 11;

FIG. 13 is a diagram illustrating a relationship between a flag memory and a scanning line used in the first embodiment.

FIG. 14 is a diagram illustrating a processing procedure of the display controller according to the first embodiment.

FIG. 15 is a diagram illustrating a processing procedure of the display controller according to the first embodiment.

FIG. 16 is a liming chart showing a series of operation timings from a line output control circuit to driving of a display panel according to the first embodiment.

FIG. 17 is a timing chart illustrating the application timing of the drive voltage of the display panel according to the first embodiment.

FIG. 18 is a diagram illustrating drive voltage waveforms of the display panel according to the first embodiment.

FIG. 19 is a diagram illustrating a configuration of a decoder used in the first embodiment.

FIG. 20 is a diagram illustrating a logical table illustrating an operation of a decoder used in the first embodiment.

FIG. 21 is a diagram illustrating a logical table illustrating an operation of the decoder used in the first embodiment.

FIG. 22 is a schematic diagram illustrating a pixel unit when displaying a certain resolution of the display panel according to the first embodiment.

FIG. 23 is a schematic diagram showing a state of gradation display at the resolution shown in FIG. 22;

FIG. 24 is a schematic diagram illustrating a pixel unit when another resolution is displayed on the display panel according to the first embodiment.

FIG. 25 is a schematic diagram showing a state of gradation display at the resolution shown in FIG. 24;

FIG. 26 is a schematic diagram illustrating a pixel unit when displaying still another resolution of the display panel according to the first embodiment.

FIG. 27 is a schematic diagram showing a state of gradation display at the resolution shown in FIG.

FIG. 28 is a diagram illustrating a part of a pixel array of a display panel according to a second embodiment.

FIG. 29 is a diagram illustrating a part of a pixel array of a display panel according to a third embodiment.

FIG. 30 is a diagram illustrating a part of a pixel array of a display panel according to a fourth embodiment.

FIG. 31 is a diagram illustrating a part of a pixel array of a display panel according to a fifth embodiment.

FIG. 32 is a diagram showing an example of gray scale display using the display panel according to the fourth embodiment.

FIG. 33 is a diagram showing an example of gradation display using the display panel according to the fourth embodiment.

FIG. 34 is a diagram showing an example of gradation display using the display panel according to the fourth embodiment.

FIG. 35 is a diagram showing an example of gradation display using the display panel according to the fourth embodiment.

FIG. 36 is a diagram showing an example of gradation display using the display panel according to the fourth embodiment.

FIG. 37 is a diagram showing an example of gray scale display using the display panel according to the fourth embodiment.

FIG. 38 is a diagram showing an example of gray scale display using the display panel according to the fourth embodiment.

FIG. 39 is a diagram showing an example of gradation display using the display panel according to the fourth embodiment.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-3-123386 (JP, A) JP-A-4-147212 (JP, A) JP-A-3-135522 (JP, A) JP-A-6-135 295338 (JP, A) JP-A-3-75688 (JP, A) JP-A-3-36520 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 3/00-3 / 38 G09F 9/00-9/46 G02F 1/133 505-580 G02F 1/1343

Claims (8)

(57) [Claims] 1. A display panel comprising a plurality of dot patterns arranged in a horizontal direction and a vertical direction, wherein the dot pattern comprises 16 dots formed by a matrix of 4 rows and 4 columns. In the dot, the width of the first line and the fourth line is
The width of the first and fourth columns is larger than the width of the second and third rows and the width of the first and fourth columns in the 16 dots is greater than the width of the second and third columns. A display panel that can be divided evenly into at least two types of pixels by different combinations of the 16 dots, and wherein the at least two types of pixels have different areas from each other. 2. A pixel pattern comprising a plurality of dots, of which at least three dots are different from each other in a dot pattern, are repeatedly arranged in a horizontal direction and a vertical direction, and formed by a combination of the dots. In the display panel in which the display is performed using the as a display unit, the dot pattern that is repeatedly arranged includes a first combination of the dots, and can be equally divided into m first pixels having an effective area S1. And a second combination of the dots, which can be evenly divided into n second pixels having an effective area S2, where S1 <S2 and m> n, and m / n ≠ 2a, (A is a natural number). 3. A pixel composed of a plurality of dots, and if at least three of the dots have different areas, the dot pattern is repeatedly arranged in a horizontal direction and a vertical direction, and is formed by a combination of the dots. In the display panel in which the display is performed by using as a display unit, the dot pattern that is repeatedly arranged includes a first combination of the dots, and can be equally divided into p first pixels having an effective area S1. And a second combination of the dots, which can be evenly divided into q second pixels having an effective area S2, and a third combination of the dots having an effective area S3 It can be divided into r third pixels, and S1 <S2 <S3, and p>q> r, and p / q ≠ 2
a, and p / r = 2a, where a is a natural number. 4. A display panel having a pixel region including two or more types of dots having different areas, wherein the pixel region includes a first combination of the dots,
S1 <S2, which can be equally divided into a first pixel having an effective area S1 and at the same time, can be equally divided into a second pixel having an effective area S2, which is composed of a second combination of the dots. And a display panel satisfying {S2 / {S1} b (b: natural number). 5. A configuration in which the first pixel includes only some of the dots that form the second pixel;
5. A configuration comprising a combination of another dot forming the second pixel and another dot forming the second pixel adjacent thereto. Display panel described in. 6. The display panel according to claim 1, wherein the dots comprise three color dots having different colors. 7. The display panel according to claim 1, wherein the display panel has a different number of display gradations from the first pixel and a number of display gradations from the second pixel. 8. A display panel according to claim 1, further comprising: signal processing means for assigning display information to predetermined dots of the display panel according to resolution. Display device.