JPH02709B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a display device that displays signals having halftones, such as image signals, using a dot matrix display element such as a fluorescent display tube.

[Prior Art] A dot matrix type display element generally has the configuration shown in FIG. The signal lines consist of two sets, a column electrode group It is done like this.

FIG. 2 shows a typical example of a conventional display device using this display element. In the figure, 1 is a matrix display panel, 2 is a driver that controls the display of pixels arranged at the intersection of electrode groups X and Y of the display panel, and 3 and 4 are column electrode control circuits that obtain drive signals for column electrodes. and a shift register, 5 is a row electrode control circuit that also obtains drive signals for the row electrodes, 6 is a conversion unit that converts data in the memory 7 that stores image signals into pixel on/off signals, and shift register 4 is a timing generator. Based on the shift clock signal from the circuit 8, on/off signals are arranged on the corresponding column electrodes, and the column electrode control circuit 3 latches the output of the shift register 4 for a predetermined period based on the latch clock signal from the timing generation circuit 8. controlled to do so.

9 is a display controller device equipped with a microprocessor to provide display data;
A data signal is sent to the memory 7, an address signal is sent to the selector 10, and a read/write control (hereinafter referred to as R/
(referred to as W control) 11 respectively. 12
1 is a clock generation circuit, and 13 is a read address counter.

In the above configuration, the display panel 1 has a memory 7
The contents of the pixel are read out periodically, converted into on/off signals for each pixel, and displayed. The timing of the display data sent from the display control device 9 is adjusted by the R/W control 11 so as not to interfere with the readout timing of the memory 7 for display.
Written to memory 7. In order to simplify the explanation below, the display panel will be explained using a 4×4 pixel element. There is a one-to-one correspondence between the pixel position of the display element and the memory address, and the relationship is as shown in FIG. 3. That is, a indicates the pixel arrangement, b indicates the memory address corresponding to the position of each pixel, c indicates the data written to each address corresponding to the memory pixel, and the address is the X address and Y address as shown in d. It can be divided into addresses. Such a display device performs display by sequentially and periodically driving the electrodes Y and switching the signal applied to the electrodes X in synchronization with the driving.

A control time chart of this display device is shown in FIG. Now, if an address is given to the memory 7 at the timing shown, the corresponding data will be output. The conversion unit 6 that performs on/off determination sets "1".
ON, determines “0” as off data, and sends the data to shift register 4. This data is arranged in the shift register 4 by the shift clock S, latched by the latch clock L and held for a certain period of time, and becomes a signal for driving the X electrode. For example, T ₁
The period T holds data ordered in ₄ periods,
The data is used to drive the X electrode. On the other hand, Y
The electrode Y ₁ is driven, and the display during the period T ₁ is as shown in Figure 5 a, and the displays a to d are performed during the periods T ₁ to _{T 4} , respectively, and there is no afterimage to the human eye. Due to this effect, the displays a to d appear consecutively as shown in e, and the data in FIG. 3 is displayed. Note that f indicates a corresponding address in the memory 7.

Such display elements can only express binary values, such as whether a pixel is on or off, but when displaying an image signal with halftones, the data in the memory is read out the required number of times to control the on/off of the corresponding pixel. It is possible to display shades of light and darkness depending on the length of the cumulative time period in which each pixel is turned on.

The display of data having halftones will be described below. To simplify the explanation, let us assume that each pixel has 2 bits of data and that it is possible to display four gradations of light and shade. In this case, the memory 7 is read four times, and each pixel is determined to be on or off according to the data and displayed, and an intermediate tone is displayed based on the accumulated time width of on and off of each pixel. The converter 6 that performs on/off determination has a concrete configuration shown in FIG. 6. Here, the count is used to count the number of times the memory 7 is read, and the display data is read out four times and compared with the counter outputs 0 to 3 sequentially by a comparator. When the display data A is larger than the counter output B, it is turned on, and if they are equal or When it is small, it is converted to an off signal.

Now, a case will be described in which data as shown in FIG. 7B is written to the address of the memory 7 shown in FIG. 7A corresponding to each pixel of the display element. According to the driving method shown in Fig. 4, the drive signal for the X electrode is switched at the timing of the latch, and the signal for the Y electrode is also switched at the same time, but here, the cycle from T ₁ to T ₄ is used to determine whether the pixel is on or off. Comparison data B for
Iterate sequentially for cases where is 0, 1, 2, 3,
A one-field screen is formed, which is shown in FIG. 8 using a time chart. In this case, when each pixel has n bits of data, it is possible to display an image with 2 ⁿ gradations, but it is necessary to read the memory 2 ⁿ times.
In the above example, since the data is 2 bits, the memory is read four times, and one field screen is formed by four screens indicated by _t1 to _t4 . 8 in Figure 9
Each of the display forms a to d at times t ₁ to _{t 4} in the figure and an image e visible to the human eye as the cumulative value thereof are shown. a ₀
~ _d3 corresponds to the display at _a0 ~ _d3 in Fig. 8, _a0 ~ _d0 is when the counter output B in Figure 6 is B=0, and _a1 ~ _d1 is B=1. , a ₂ ~ d ₂ is B=
2, a ₃ to d ₃ indicate the case where B=3.

However, in the dynamic drive in this case, the Y electrode drive signal is switched at the same time as the X electrode drive signal is switched, and in order to prevent erroneous display that occurs when the signal is switched due to disturbance in the drive signal waveform, blanking is performed. A time Tb (see FIG. 8) must be provided, which leads to a reduction in brightness due to the significant sacrifice of the effective light emission period. Furthermore, when displaying high-gradation data, the number of memory reads per field increases, the number of screens to configure one field increases, and the response speed of the display element cannot keep up with the high-speed scanning.
There are drawbacks such as a decrease in contrast.

[Summary of the Invention] The present invention has been made in view of the above points, and provides a display device that can reduce the reduction in luminous efficiency due to blanking time.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described based on FIG. 10, in which the same parts as in FIG. 2 are denoted by the same reference numerals.
Address counter 1 that sequentially reads out each pixel signal of
3 is divided into a column address counter 14 corresponding to the column pixel group designation of the display panel 1 and a row address counter 15 corresponding to the row pixel group designation, and there is a space between these two address counters corresponding to FIG. A counter 16 is installed and configured, and the image signal of each column pixel is repeatedly read out the number of times set by the counter during the drive period of the corresponding row electrode from the memory specified by the row address generation section, and the pixel is turned on and off. is controlled, and each pixel is driven with a time width corresponding to the image signal. Others are the same as before.

Now, assume that each pixel has n bits of display data.
2 It is possible to display ⁿ gradation gradations, but counter 1
6 is a 2 ^n- ary counter, and to simplify the explanation, we will consider the case where each pixel has 2 bits of data. In this case, counter 16 is a quaternary counter. The relationship between the addresses of the memory 7 and the data written to each address is shown in FIG. 7 for comparison with the above explanation. The on/off signal of each pixel is compared with the data A of the memory 7 and the output B of the counter 16 corresponding to each pixel, and is converted into an on signal when A>B and an off signal when A≦B. The Y electrode drive signal switches as the Y address counter advances, but since a quaternary counter is provided between the X address counter and the Y address counter, data at the X address corresponding to the Y electrode drive period is repeatedly read out four times. The electrode drive signal switches four times.
The time chart is as shown in FIG. As shown in this time chart, the display shown in FIG. 12 is produced by drive control.

That is, the composition a to d of the display for the period t ₁ ′ to t ₄ ′
Thus, one field of screen e is formed. In the figure, a ₀ to d ₃ indicate the period indicated by a ₀ to d ₃ in FIG. 11, which is the same as the display for a ₀ to d ₃ in FIG. 8. Comparing FIGS. 8 and 9 of the conventional example with FIGS. 11 and 12 of this embodiment,
Although the screen displayed in one field is exactly the same, as can be seen by comparing the time charts, according to this embodiment, the blanking time required when switching the drive signal is reduced, and the reduction in brightness can be reduced. Furthermore, drive signals a ₀ ~ d ₀ , a ₁ ~ d ₁ , a ₂ ~
d ₂ , a ₃ to _{d 3} are calculated by comparing pixel data A with counter output data B values 0, 1, 2, and 3, respectively.
It is a signal obtained by converting into a signal that is on when A>B and off when A≦B.Here, _a3 to _d3 are drive signals when comparison data B=3, but the memory Since signal A is 2 bits, A>3 does not hold. Therefore, pixels a ₃ , b ₃ , c ₃ , and d ₃ are all off (see FIGS. 9 and 12). Therefore, by shifting the phase of the drive signal waveform of the Y electrode, a ₃ , b ₃ , c ₃ ,
Switching the Y electrode drive signal during the period _d3 ( _Y1 ' to _Y4 ') eliminates the need to insert blanking time into the Y electrode drive signal, allowing efficient display. Furthermore, the display of each pixel is performed by repeatedly reading out the data from the memory, and successively outputting a counter output of 0,
1, 2, and 3 to determine whether it is on or off, each signal is modulated to a time width corresponding to the data.

FIG. 13 shows part of the drive timing when displaying n-bit data using an l-by-m-column matrix display element. This figure 13 shows the Y electrode Yj
It shows the timing of each part when the is being driven. Data a ₁ to m columns each corresponding to row j
am is repeatedly read out 2 ⁿ times at timing A. These are compared with the signals indicated by B to determine whether they are on or off, arranged in a shift register at timing S, latched at timing L, and drive the corresponding X electrodes. To explain a specific pixel, if the data A of that pixel is x (0≦x≦2 ^n-1 ), the data (x) is read out 2 ⁿ times at the timing of T ₀ to _{T 2} ^n-1 , and is read out sequentially. The data is compared with 0 to 2 ^n-1 , converted to on/off data, and arranged in a shift register at the corresponding pixel position to become a display signal. This display signal rises at T ₁ and Tx
The pulse falls at +1, and each pixel is driven with a pulse width according to the data. Moreover, T ₀ in the figure
During the period indicated by , the pixel is always off. Therefore, by switching the row electrode signals during this period, there is no need to provide a blanking time to reduce the row electrode signals, and efficient display becomes possible. In addition,
By inserting a cutting pulse into each row electrode drive signal at the switching timing of the column electrode drive signal, the brightness of the entire screen can be adjusted.

[Effects of the Invention] As described above, according to the display device of the present invention, the address counter that sequentially reads out each image signal in the memory is configured such that the column address counter corresponding to the column pixel group designation of the display section and the row pixel group designation correspond to the row pixel group designation. A counter is provided between both address counters, and the image signal of each column pixel is set by the counter during the driving period of the corresponding row electrode from the memory specified by the row address generator. By repeatedly reading out the pixels and controlling the on/off of each pixel, each pixel is driven with a time width corresponding to the image signal, so the number of screens constituting one field can be set to one regardless of the gradation of the data. Since the scanning speed is constant, it is possible to significantly reduce the reduction in brightness due to insufficient response speed of the display element or the reduction in brightness due to blanking time.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a general dot matrix display element, Figure 2 is a configuration diagram showing a conventional display device, and Figures 3a to 3d are pixel positions of the display element and corresponding memory addresses and data. 4 is an operation time chart of FIG. 2, FIG. 5 is an explanatory diagram showing a display example, FIG. 6 is a partial detailed view of FIG. 2, and FIG. 7 a and b are each address. Fig. 3 shows the relationship between memory addresses and data when 2-bit data is present (4-gradation gradation display); Fig. 8 is a time chart for 4-gradation gradation display; The figure is a display form diagram corresponding to Fig. 8.
0 to 13 illustrate one embodiment of the present invention, and FIG. 10 is a configuration diagram corresponding to FIG. 2, and FIG.
FIG. 1 is a time chart, FIG. 12 is a diagram corresponding to FIG. 9, and FIG. 13 is a driving team chart when an l-row, m-column matrix display element is used. 1... Matrix display panel, 3... Column electrode control circuit, 4... Shift register, 5...
Row electrode control circuit, 6...On/off signal converter, 7...Memory, 14...Column address counter, 15...Row address counter, 16...Counter.

Claims (1)

[Scope of Claims] 1. A matrix display panel having a row electrode group and a column electrode group and controlling the display of pixels arranged at the intersection of both electrode groups by a combination of driving of both electrode groups, and storing image signals. a converter that converts the memory data into pixel on/off signals, a shift register that arranges the on/off signals to the corresponding column electrodes, and a shift register that holds and latches the shift register output for a required period of time and outputs the latch. The image signal of each pixel is read out from the memory a required number of times at each required time interval, and the corresponding pixel is In a display device that displays an image with an intermediate width by controlling the on/off of each pixel, the cumulative ON time width of each pixel is made proportional to the amplitude of the image signal of the corresponding pixel. The address counter for sequentially reading out each image signal is divided into a column address counter corresponding to the column pixel group designation of the display section and a row address counter corresponding to the row pixel group designation, and a counter provided between both address counters, During the driving period of the corresponding row electrode from the memory specified by the row address generation section, the image signal of each column pixel is repeatedly read out the number of times set by the above counter, and the on/off of the pixel is controlled to generate the image signal of each pixel. A display device characterized in that it is driven with a time width corresponding to. 2. The display device according to claim 1, wherein when the counter advances, a cutting pulse is inserted into the row electrode drive signal to adjust the brightness of the entire screen.