JPH10171441A - Character display control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the adjustment work of monitor reduced in cost and high in efficiency by generating various test pattern signals only by an LSI for OSD. SOLUTION: In a test mode, a microcomputer sends out with a command a mode change-over data presenting a test mode and a pattern designation data designating which test pattern of a plurality of test patterns is desired to be displayed. The mode change-over data MD and the pattern designation data are set to a test pattern signal generation circuit 18 and a mode control register 17 via latch and command decoder 2, respectively, and the signal generation circuit 18 generates test pattern RGB signals designated according to horizontal and vertical synchronizing signals HD, VD inputted thereto. Moreover, in order for the mode change-over data to present the test mode, a selector 160 selects the test pattern RGB signals outputted from the test pattern signal generation circuit 18, and the signals are sent from output terminals 19-21 to a monitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a character display control circuit for an OSD which realizes an OSD (ON SCREEN DISPLAY) function for displaying a character on a monitor or the like, and more particularly to a circuit capable of supporting a test mode.

[0002]

2. Description of the Related Art Generally, an O for displaying characters on a monitor or the like is used.
In order to realize the SD function, character data to be displayed is transferred from a microcomputer to an LSI as an OSD control circuit, and the LSI transfers the character data transferred to an address corresponding to a display position of a connected video memory. Write. In the LSI, character data is sequentially read from the video memory at a predetermined timing for display, the read character data is converted into a character display signal by a character generator, and supplied to an external monitor.

In a monitor for displaying a character display signal obtained in this way, it is necessary to check the display characteristics.
An expensive signal generator for generating various test pattern signals such as 0% and color bars is separately prepared, and the test pattern signal is input to the monitor from this device to perform various adjustments.

[0004]

Conventionally, an expensive signal generator must be provided separately from the OSD control circuit (LSI) for adjusting the monitor, which leads to an increase in cost and an adjustment work. There was a problem that was troublesome. In recent years, multi-scan type monitors corresponding to multiple different frequencies have been increasing,
In order to adjust such a monitor, test pattern signals having a plurality of different frequencies must be generated, and the signal generator for adjustment tends to be more expensive.

[0005]

According to the present invention, there is provided a write / read circuit for writing / reading character data to / from a video memory, a conversion circuit for converting the character data read from the video memory into a character display signal, A test pattern signal generating circuit for generating a test pattern signal, and a selecting circuit for selecting and outputting one of the character display signal and the test pattern signal according to mode switching data are provided.

The test pattern signal generation circuit has horizontal and vertical counters capable of setting frequency data and generating counter outputs of a cycle corresponding to the set frequency data. The test pattern signal is generated. Furthermore,
The test pattern signal generation circuit includes a plurality of generation circuits that generate a plurality of types of test pattern signals from the counter output, and an output signal of any one of the plurality of generation circuits according to pattern designation data indicating a type of a test pattern. And a switching circuit for switching and outputting.

Further, the plurality of generating circuits include at least an OR gate for inputting both counter outputs of the horizontal and vertical counters, and a 3-bit counter for counting the output of the horizontal counter, and the switching circuit includes at least The first and second input terminals and the only output terminal are provided for each of RGB, the output of the OR gate is commonly supplied to each of the first input terminals of RGB, and the three bits are supplied to each of the second input terminals of RGB. Each bit output of the counter is supplied.

[0008]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Serial character data and various control data, a horizontal synchronizing signal HSYNC and a vertical synchronizing signal VSYNC are inputted from the outside. 1 illustrates an OSD LSI that outputs RGB display signals. This LS for OSD
I is a serial / parallel converter 1 for converting character data and various control data serially input from a microcomputer into parallel data, latching the parallel-converted data, and decoding the data when the data is a command. A latch & command decoder 2 for outputting control data included in a command, and an external horizontal synchronizing signal HS
Input terminals 3 and 4 for inputting YNC and vertical synchronization signal VSYNC, PLL circuit 5 for generating dot clock DCLK synchronized with horizontal synchronization signal HSYNC, and horizontal and vertical heads indicating write positions from latch & command decoder 2 H control register 6 and V where the address is set
The contents of the control register 7, the H control register 6 and the V control register 7 are each preset, and each of the write H counter 8 and the write V counter 9 for generating horizontal and vertical addresses for writing, and the read A read H counter 10 and a read V counter 11 for generating horizontal and vertical addresses, a write / read control circuit 12 for controlling writing and reading,
An address circuit 13 for switching and outputting a write address and a read address at a predetermined cycle in accordance with a control signal from the write / read control circuit, and an address having a storage capacity for one screen and designated by the address control circuit 13 Memory VRA for storing character data and attribute data from latch & command decoder 2
M14, a ROM 15 as a character generator for converting a character code read from the VRAM 14 into character font data, and an RGB character display signal having a display attribute specified by the character font data from the ROM 15 and the attribute data read from the VRAM 14 and designated by the attribute data. And an output control circuit 16 for generating the same.

Further, test pattern designation data is set from a mode control register 17 in which mode switching data MD for designating a normal mode or a test mode is set, and a test pattern signal designated by RGB is set from the latch & command decoder 2. And a test pattern signal generating circuit 18 for outputting the RGB character pattern display signal based on the character font data from the ROM 15 and the RGB test pattern signal from the test pattern signal generating circuit 18. It has a selector 160 for selecting and outputting according to the switching data MD.

Therefore, in the case of the normal mode, first, the microcomputer sends out mode switching data indicating the normal mode and H and V head addresses indicating the write position along with the command, and these data are converted into the serial-parallel converter 1 and The data is set in the mode control register 17, the H control register 6, and the V control register 7 via the latch & command decoder 2, respectively.

Next, the microcomputer sends a character code and an attribute code to be displayed, and these are sent to the VRA according to the addresses from the H and V counters 8 and 9 for writing.
Written to M14. The written character code and attribute code are read H and V counters 10,
11 are sequentially read according to the address from
After being converted into character font data in step 5, the output control circuit 16 adds display attributes to generate RGB character display signals.

Here, the selector 1 in the output control circuit 16
60 selects an RGB character display signal generated based on character font data from the ROM 15 when the mode switching data set in the mode control register 17 indicates the normal mode. A display signal is sent from the output terminals 19, 20, 21 to the monitor.

On the other hand, in the test mode, the microcomputer switches the mode switching data indicating the test mode to the cross hatch,
Pattern designating data PD for designating which test pattern of a plurality of test patterns, such as white 100% and color bar, to display is transmitted together with the command.
Then, the mode switching data MD and the pattern designation data P
D receives the test pattern signal generation circuit 18 and the mode control register 17 via the latch & command decoder 2, respectively.
And the signal generation circuit 18 generates an RGB signal of a test pattern designated according to the input horizontal and vertical synchronization signals HD and VD. The selector 160 selects the test pattern RGB signal output from the test pattern signal generation circuit 18 because the set mode switching data MD indicates the test mode, and this signal is output from the output terminals 19, 20, and 21 to the monitor. Sent out.

As described above, even if a special signal generator for generating a test pattern signal is not prepared, the OSD L
Various test pattern signals can be generated only by the SI, and adjustment of the connected monitor can be easily performed. next,
A specific configuration of the test pattern signal generation circuit 18 will be described with reference to FIG.

As shown, the test pattern signal generation circuit 18 includes an H counter 180 reset by the horizontal synchronization signal HD and counting the dot clock DCLK, and a V counter 181 reset by the vertical synchronization signal VD and counting the horizontal synchronization signal. , Output HSI of each counter
OR gate 182 for inputting G and VSIG, and 3-bit counter 18 for counting output HSIG of H counter
3, a voltage line 184 for generating an H level signal,
H for setting the control data for horizontal and vertical sent from the switching circuit 185 and the latch & command decoder 2
A control register 186, a V control register 187, and a pattern designation control register 188 in which the pattern designation data PD sent from the latch & command decoder 2 is set.
It is composed of Here, OR gates 182, 3
The bit counter 183 and the voltage line 184 are configured to generate test patterns of cross hatch, color bar, and white 100%, respectively.

Incidentally, the OSD LSI is capable of arbitrarily setting the frequency of a test pattern so as to be compatible with a multi-scan type monitor. That is, in the test mode, the microcomputer sends out the horizontal and vertical frequency data HFD and VFD for designating the frequency of the test pattern together with the mode switching data MD and the pattern designation data PD, and the frequency data HFD and VFD are respectively The H control register 186 and the V control register 187 are set. Then, the content of the H control register 186 is preset in the H counter 180 every time the H counter output HSIG is generated, and the V control register 1
87 every time the V counter output VSIG occurs.
The counter 181 is preset. Therefore, counter outputs HSIG and VSIG of frequencies corresponding to the set frequency data HFD and VFD are output from H counter 180 and V counter 181.

The switching circuit 185 has first to third input terminals and only one output terminal for each of R, G, and B, and the pattern designation data PD from the pattern designation control register 188 is crossed. The signal of the first input terminal is used to specify the hatch, the signal of the second input terminal is used to specify the color bar, and the third signal is used to specify 100% white.
The signal of the input terminal is switched to be output to the output terminal. The output signals of the OR gate 182 are commonly supplied to the first input terminals of R, G and B, and the respective bit outputs of the 3-bit counter 183 are respectively supplied to the second input terminals of R, G and B. The H level signal from the voltage line 184 is commonly supplied to the third input terminals of R, G, and B.

Therefore, when the cross hatch is designated by the pattern designation data PD from the switching circuit 185, the counter outputs HSIG and VS are output as shown in FIG.
During the period when the IG is at the H level, an output signal is output in which all the signals of R, G, and B are at the H level at the same time. As a result, a white cross hatch as shown in FIG. Become. Here, the H control register 186, V
The frequency data HFD set in the control register 187,
Since the VFD is data corresponding to the periods T1 and T2 shown in FIG. 3A, it is possible to arbitrarily change the cross hatch interval shown in FIG. 4A by changing its value. When the H counter 180 and the V counter 181 are down counters, the count values themselves corresponding to the periods T1 and T2 are set in the respective control registers 186 and 187. When the H counter 180 and the V counter 181 are up counters, the count values corresponding to the periods T1 and T2 are set. May be set in the control registers 186 and 187.

When the color bar is designated by the pattern designation data PD, the output of the 3-bit counter 183 changes every time the H counter output HSIG is generated. As shown in FIG. 3B, an output signal in which R, G, and B sequentially change every one cycle of the output HSIG is generated, and as a result, the color bar display shown in FIG. 4B is performed on the monitor. In this case, since the frequency data HFD set in the H control register 186 is data corresponding to the cycle T3 shown in FIG. 3B, by changing its value, the interval between the color bars shown in FIG. can do.

White 1 is determined by the pattern designation data PD.
When 00% is designated, the switching circuit 185 outputs the H level voltage from the voltage line 184 as R, G, B output signals, so that all the signals of R, G, B are always at H level.
Level, and a white display is displayed on the monitor.

[0021]

According to the present invention, it is not necessary to use an expensive special signal generator for generating a test pattern.
The cost and efficiency of monitor adjustment work can be reduced.
Also, a plurality of patterns can be displayed as test patterns, and their frequencies can be set arbitrarily, so that it is possible to support a monitor for multi-scan.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a specific configuration of a test pattern signal generation circuit according to the embodiment.

FIG. 3 is a timing chart showing signals in the embodiment.

FIG. 4 is an explanatory diagram showing a display example in the embodiment.

[Explanation of symbols]

 2 Latch & Command Decoder 12 Write / Read Control Circuit 14 VRAM 15 ROM 16 Output Control Circuit 17 Mode Control Register 18 Test Pattern Signal Generator 160 Selector 180 H Counter 181 V Counter 182 OR Gate 183 3 Bit Counter 185 Switching Circuit 186 H Control Register 187 V control register 188 Pattern designation control register

Claims (4)

[Claims] 1. A writing and reading circuit for writing and reading character data to and from a video memory, a conversion circuit for converting character data read from the video memory into a character display signal, and a test pattern for generating a test pattern signal A character display control circuit comprising: a signal generation circuit; and a selection circuit that selects and outputs one of the character display signal and the test pattern signal according to mode switching data. 2. The test pattern signal generation circuit according to claim 1, wherein said test pattern signal generation circuit has horizontal and vertical counters capable of setting frequency data and generating counter outputs of a cycle corresponding to the set frequency data. 2. The character display control circuit according to claim 1, wherein the test pattern signal is generated. 3. The test pattern signal generation circuit includes: a plurality of generation circuits for generating a plurality of types of test pattern signals from the counter output; and a plurality of the generation circuits according to pattern designation data indicating a type of a test pattern. 3. The character display control circuit according to claim 2, further comprising a switching circuit for switching and outputting one of the output signals. 4. The plurality of generation circuits have at least an OR gate for inputting both counter outputs of the horizontal and vertical counters, and a 3-bit counter for counting the horizontal counter output. The first and second input terminals and the only output terminal are provided for each of RGB, the output of the OR gate is commonly supplied to each of the first input terminals of RGB, and the three bits are supplied to each of the second input terminals of RGB. 4. The character display control circuit according to claim 3, wherein each bit output of the counter is supplied.