JPS644194B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an image data receiving device that temporarily stores image data transmitted as a digital signal in a memory device, reads it out and displays it on a display device, and particularly relates to The present invention relates to an image data reading device for reading image data from a memory device in order to scroll display, that is, to move and display the display contents on the screen.

2. Description of the Related Art Image signals such as text or image information are transmitted, for example, from a data center via a telephone line and stored in a memory device on the receiving side. When displaying this image signal, the image data is displayed on the cathode ray tube while being refreshed and read out. Generally, this address designation for refresh reading is performed based on the output of a refresh counter provided in synchronization with vertical and horizontal synchronizing signals for deflection scanning in a cathode ray tube display device.

Problems to be Solved by the Invention Conventional refresh counters are configured so that their output shows a fixed relationship with the synchronization signal, and therefore output a fixed output with respect to the synchronization signal. Therefore, the memory readout always matches the screen display position, in other words, the address for memory readout and the scanning beam position are one-to-one.
It corresponds to For this reason, when scrolling display is performed using a cathode ray tube, it is essential to rewrite the stored contents of the refresh memory device for each scanning line address. The process of rewriting the memory contents of this refresh memory device takes a predetermined time, that is, the (read/write cycle) of the device.
(address capacity of the display memory), so when trying to scroll display image data in a high-speed data transmission system, the data for the next scanning line will be input before the rewriting is completed, and the desired data will not be displayed. A problem arises in that scrolling cannot be performed.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an image data reading device that does not require rewriting the stored contents of a memory device in order to enable suitable scroll display in a display device that displays image data.

Means for Solving the Problems The present invention includes an initial signal that includes a mode signal that specifies fixed display or scroll display, and indicates that the data is at the beginning, and which scanning line corresponds to the display. A data signal composed of a code signal to indicate and display image data as one unit is transmitted for each scanning line, and after receiving this display image data and storing it in a data memory device, it is read out and displayed on a cathode ray tube. In an image data reading device in a raster scanning display system such as a device, a processing device generates a load signal upon receiving the data signal, and also generates an address signal obtained by decoding the code signal. , an address register that inputs and presets the new decoded address signal each time the load signal is received; and in response to the address signal preset in the address register and a synchronization signal that synchronizes with the raster scanning, an address counter that generates an address signal for reading out the display image data from the data memory device; the processing device determines from the mode signal included in the initial signal that the scroll display is specified; , the address register is controlled so that an address signal generated by adding a predetermined value to an address signal obtained by decoding the code signal is supplied to the address register.

Function The reading device of the present invention receives an initial signal indicating that the data is at the beginning (including a mode signal that specifies fixed display or scroll display) and the number of scanning line to which the data corresponds. A data signal consisting of a code signal indicating the display and display image data as one unit is transmitted for each scanning line,
In addition, in an image data readout device in a system that stores this image data in a data memory device and then reads it out and displays it on a cathode ray tube display device, when the data signal is received, the code signal is extracted and decoded to a predetermined address. By providing an address register that generates a signal and presets this address signal as a new address signal every time the load signal is received, the preset value of this address register and the synchronization signal that synchronizes with the raster scanning can be set. Scroll display is enabled by responsively changing the count value of an address counter that generates an address signal for reading the image data from the data memory device.

EXAMPLES Next, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block circuit diagram showing one embodiment of the present invention.

In the figure, an image data input terminal 2 is supplied with a digitized data signal from a data center (not shown) via a telephone line.

In this embodiment, as shown in FIG. 6, this data signal includes a mode signal specifying fixed display or scroll display, an initial signal indicating the beginning of the data, and the number of the scanning line. A code signal indicating a line number indicating whether the data corresponds to the display image data and the display image data constitute one structural unit. Furthermore, the data signal of one constituent unit in this embodiment is input to the input terminal 2 periodically or aperiodically.

The input/output interface 4 includes a demodulation circuit 6, which removes the carrier wave signal component from the signal supplied to the input terminal and extracts only the digitized data signal. The input/output interface 4 also includes a serial-in-parallel-out (hereinafter referred to as S/P) converter 8.
In this embodiment, the P converter 8 uses an 8-bit microprocessor as the central processing unit 10, so that signal processing is performed in units of 8 bits.

Therefore, each time the input/output interface 4 receives a signal having a data structure as shown in FIG. 6 in which the initial signal, code signal, and display image data are one constituent unit, the input/output interface 4 takes in the signal as new received data. By performing the above-described demodulation and S/P conversion processing, this one constituent unit of received data is sequentially subjected to signal processing in 8-bit units as described above and is output.

The central processing unit (hereinafter referred to as CPU) 10 is
From input/output interface 4 above to 8 like this
When a bit-by-bit data signal is taken in, first, it is determined whether it is a fixed display or a scroll display based on a mode signal included in the initial signal.

Next, the CPU 10 extracts the code signal and decodes it to determine the line number, that is, the position of the scanning line.As will be described in detail later, if the above judgment is for scroll display, the CPU 10 adds +1 to the decoded value. In the case of fixed display, a preset fixed value set by a program is set in the Y address register 34 according to each determination. The timing to set this is
10 is performed every time the above-mentioned value is calculated, that is, every time one constituent unit of data signal is newly received.
This set command is issued by a load signal S2 output from the CPU 10. In this embodiment, this load signal uses a so-called write pulse that is generally output whenever the CPU writes data on a data bus to a register or the like.

Then, in the next step, the CPU 10 extracts the display image data and writes it to a predetermined location (described later) in the data memory device (hereinafter referred to as a memory device) 12 via the data bus D1. At this time, the CPU 10 stops outputting the load signal S2 described above, issues a write command to the memory device 12, and outputs a control signal S1 described later.

The write command issued to the memory device 12 causes display image data to be applied to the memory device 12 via the data bus D1 only when the write command is given to the memory device 12. Further, the control signal S1 is given to data selectors 18 and 20, respectively.

This control signal S1 is configured to selectively output either one of the X address buses X1 and X2 supplied to the data selector 18 in accordance with the relationship described below.
In addition, each of the two data buses is selectively switched and controlled so that either one of the Y address buses Y1 and Y2 supplied to the data selector 20 is selectively outputted with the relationship described later.

In this embodiment, the control signal S1 is generated only when the CPU 10 stops outputting the load signal S2 and is receiving a data signal, that is, when writing is performed.

Further, the control signal S1 is applied to each data selector 18, 2 in such a manner that the address given from the CPU 10, that is, the data on the X address bus X1 side and the Y address bus Y1 side is output to the memory device 12.
Controls 0.

By the way, as already mentioned, the above CPU10
separates and decodes the code signal from the data signal, and instructs from which address to which address in the memory device 12 the display image data of the data signal should be written by specifying the X address and Y address. .

When writing this, it is sufficient to maintain a constant relationship between the display screen position and the address, so when writing certain display image data, after first specifying the X address and Y address, In addition to fixing the address (display scanning line position),
It is sufficient to issue a write command while updating the X address every 8 bits of display image data.

For example, here, assuming that the display image data in the data signal shown in FIG. 6 is a unit displayed in one line corresponding to pixels arranged along the horizontal scanning direction of the display device 35, is serial-in/parallel-out converted into parallel data every 8 bits, which is supplied from the input/output interface 4 to the CPU 10. The counter value corresponding to this is output to the address bus X1 as an X address.

Further, a value obtained by decoding the code signal already mentioned is outputted to the address bus Y1 as the Y address. At this time, load signal S2
Since its output has already been stopped, the value already set in the Y address register 34 is not affected and is output to the address bus Y1 as a write Y address.

Since the addresses X1 and Y1 output from the CPU 10 have already switched and controlled the data selectors 18 and 20 by the control signal S1, they serve as memory address signals for writing received data into the memory device 12.

For example, if the memory area is a 64K-bit memory device 12 with 256 bits in the vertical direction and 25 bits in the horizontal direction, 64K = 2 ¹⁶ = 2 ⁸ × 2 ⁸ , and the XI address = 8 bits and the Y1 address = 8 bits are the memory address signals. becomes.

As a result, for example, if the screen of the display device 35 is composed of n scanning lines and the display image data corresponding to the i-th scanning line is written to the memory device 12, then the Y address Yi (i-th Addresses (predetermined in correspondence with scanning lines) or new information are written, and other Y addresses, ie, Y ₁ , Y ₂ , etc., are written.
Previously written information is stored as is at each address Y _i-1 , Y _i+1 , . . . , Yn address.

Here, the Y addresses of the memory device 12 corresponding to a display screen composed of n scanning lines are 1, 2, . . .
It is set as address n. And the memory device 12 has one
This is the capacity that stores data for a screen. Further, this 8-bit display image data is written to one address in the memory device 12.

The data thus stored in the memory device 12 is again processed by the CPU 10 as 8-bit parallel display image data from the predetermined location in the memory device 12 at a predetermined timing using X and Y address counters 28 and 32, which will be described later. read out,
This is parallel in - serial out (hereinafter P/
S) via the converter 14, the display device 35
The image data is output to the image data output terminal 16 connected to the image data output terminal 16.

Now, display image data is read out from the memory device 12 as follows.

First, as described above, when the CPU 10 is receiving a data signal, it is controlled in write mode, but when it is not receiving a data signal, it is controlled in read mode. In other words, this time is the same as the initial setting when the power is turned on, and the above-mentioned control signal S
1. Neither the load signal S2 nor the write command to the memory device 12 is output.

Therefore, both data selectors 18 and 20 select the data buses Y2 and X2.

On the other hand, as described above, in order to perform reading appropriately, it is necessary to specify the address for reading while timing the reading. In this embodiment, this address specification is performed as follows.

First, the bit clock signal from the bit clock signal generator 22 is sent to the synchronization signal generator 24, the X position counter 26 and the X address counter 2.
8. This synchronization signal generator 24 divides the bit clock signal to generate a horizontal synchronization (hereinafter referred to as HD) signal and a vertical signal (hereinafter referred to as VD) signal. X position counter 2
6 and Y position counter 30 receive the bit clock signal, HD signal, HD signal and VD signal, respectively, and the scanning beam of the cathode ray tube is
It generates a signal indicating where it is in the direction and the Y direction.

When the scanning beam is within the display area in the X direction, the X position counter 26 outputs a signal indicating this to the X address counter 28. Similarly, when the scanning beam is within the display area in the Y direction, the Y position counter 30 outputs a signal indicating this to the Y address counter 32. In this way, the gate of the Y address counter 28 is opened and the gate of the X address counter 28 is opened to a predetermined address, for example 0.
Starting from the address, the address is updated one by one for every 8 bits of the bit clock signal, and is reset upon receiving the HD signal. Although the method for specifying the X address described above is similar to the conventional method, the method for specifying the Y address is a feature of the present invention. This is because, as already mentioned, there are two types: fixed display and scroll display.

In any case, first, the load signal S2 is transmitted every time a data signal is given to the CPU 10 from the terminal 2.
It is applied to the Y address register 34.

As already mentioned, the CPU 10 extracts the code signal and decodes it to determine the line number, that is, the position of the scanning line, determines whether it is fixed display or scroll display based on the mode signal included in the initial signal, and determines whether the display is fixed or not. In the case of display, a preset fixed value set by a program is set in the Y address register 34.

This setting timing is performed every time the CPU 10 calculates the above-mentioned value, that is, every time a data signal of one constituent unit is newly received. As a result, the Y address signal here is preset in this manner.

The Y address counter 32 inputs this preset value in response to a start signal S3 indicating the start of the display area from the Y position counter 30, and also inputs the preset value to the ED.
This value is updated sequentially each time a signal is received.

For example, now, when the load signal S2 is supplied from the CPU 10 to the Y address register 34,
Assume that an address signal indicating an address is supplied. In this case, when the Y address counter 32 receives a start signal S3 indicating the start of the display area from the Y position counter 30, it inputs an address signal indicating address 1 from the Y address counter 34, and each time an HD signal is input. Increase the address by 4 addresses, n
After increasing to the address, the start signal S of the next display area
3 and shows the number 1 again.

If this operation is repeated for each display area, the display in this case becomes a fixed display of a normal refresh operation as shown in FIG.

FIG. 7 is a time chart showing the timing of these series of operations, and the signals shown in FIG. 7 1 and 2 show the VD and HD signals output from the synchronization signal generator 24. Further, FIG. 7 3 shows the vertical display area for these signals, and 4 indicates Y.
The output value (decoded value) of the address counter 32 is shown, and FIG. 7 shows the start signal S3, which is always generated at the start position of the display area. These timings are managed by a Y position counter 30. Therefore, the display on the display device 35 is performed by applying this output value to the memory as address data, and by inputting the display image data stored at this address via the S/P converter 14. as displayed in the display area.

The above refresh operation is always repeated until the CPU 10 is in the write mode, thereby producing a fixed screen display.

In this time chart, after receiving a certain data signal that is received periodically or aperiodically, the load signal S2 shown in FIG.
10. As already mentioned, at this time, the CPU 10 automatically sets address 1, for example, as a preset fixed value programmed in the Y address register 34 as an address signal. Therefore, the 1 address counter 32 is set to 1 by the start signal S3 at the time point .
The address is set. This counter 32 will be
Every time the HD is input, the count is sequentially increased up to the n address.The HD becomes input prohibited outside the display area, and the next start signal S3, that is,
This state continues until . At the time of , the load signal S2 is not newly output, so
The same address 1 as at the time remains set in the Y address counter 32. By repeating this, a fixed display is made.

On the other hand, as described above, when the CPU 10 determines scroll display based on the mode signal included in the initial signal, it sets the decoded value plus 1 in the Y address register 34. Thereafter, the Y address counter 32 operates in the same manner as the fixed display described above.

This scroll display will be explained below with reference to FIGS. 3 to 5 and FIG. 8.

Now, for example, as shown in FIG. 8, 1 is connected to terminal 2.
Assume that a data signal corresponding to the first line, that is, the first Y address, is input. At this time, the CPU
10 decodes from the code signal of the received data that the received data is the data at address 1, and gives the 2nd address, which is 1 added to the 1st address, to the Y address register 34 via the address bus Y1; A load signal S2 is applied to.
As a result, address 2 of Y address register 34 is preset in response to load signal S2.
Then, in the same manner as described above, the Y address counter 32
As shown in FIG. 8, 2 and 5, address data indicating address 2 stored in the Y address register 34 is first set in response to the start signal S3, and thereafter, as shown in FIG. Address counter 32 responds to the HD signal 2, 3, 4, . . .
Count n, address 1, and so on.

When the 8 bits of the display image data portion of the received data are supplied to the CPU 10 before (or even during) the counting starts,
The CPU 10 supplies address 1, which is the address to be changed in the input data, to the address bus Y1, and also supplies a control signal S1 to the data selector 20. At the same time, the CPU 10 outputs these 8 bits to the data bus D1 and issues a write command to the memory device 12. As a result, the selector 20 selects the address bus Y1 side in response to the control signal S1. As a result, new data input from terminal 2 is written to address 1 of memory device 12. In this way, the data at address 1 is rewritten. After the rewriting is completed, the output of the control signal S1 and the write command to the memory device 12 is stopped, and the selector 20 again selects the output side of the Y address counter 32, that is, the data bus Y2 side. At this time, since address 2 is set in the Y address register 34 as described above, the display image data stored in the memory device 12 as shown in FIG. 3 is displayed on both sides.

This operation means that the new third line data is
This continues until address 3 is set in the Y address register 34 by the CPU 10 as shown in FIG. When address 3 is set in the Y address register 34, the Y address counter 3
2 receives the start signal S3 and inputs the Y address register 3.
The address data indicating the address 3 from 4 is set, and the address data indicating the address 3, 4,
5,...n, 1, 2 addresses and so on.

In this way, every time data corresponding to the i-th line, that is, the i-th Y address is input, i+1
By setting the address in the address register 34, a scroll display as shown in FIG. 5 is performed.

In this way, each time new data is received, scroll display processing for one line is performed. In other words, when new data is received and written into the memory device 12, the contents of the Y address register 34 are first rewritten. Next, the contents of this Y address register 34 are set in the Y address counter 32 by the VD signal. This shifts the display by one line, and by repeating this process, the display screen is scrolled. As a result, the same function can be realized without the need for special rewriting of the memory contents for scrolling display.

In the embodiment described above, the display screen is scrolled vertically from the bottom to the top, but based on the technical idea of the present invention, it is also possible to perform vertical scrolling from the top to the bottom or horizontally scroll the display screen. It is clear that this is also possible.

Effects of the Invention According to the present invention, data reading when scrolling and displaying image data on a display device such as a cathode ray tube can be realized without rewriting the stored contents of the data memory device, and is useful in high-speed data transmission systems. Additionally, there is an advantage that scrolling display can be performed in various modes.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a device according to an embodiment of the present invention, FIGS. 2 to 5 are diagrams showing the relationship between a memory map and a display screen in the device according to the embodiment shown in FIG. 1, and FIG. 6 is a diagram showing a received signal. FIG. 7 is a timing chart in the case of fixed display, and FIG. 8 is a timing chart in the case of scroll display. 10...Central processing unit, 12...Memory device,
22... Bit clock signal generator, 24... Synchronization signal generator, 28, 3... Address counter,
34...Address register.

Claims (1)

[Scope of Claims] 1. An initial signal that includes a mode signal that specifies fixed display or scroll display and indicates that the data is at the beginning of the data, and a code signal that indicates which scanning line it corresponds to; A data signal composed of display image data as one unit is transmitted for each scanning line, and after receiving this display image data and storing it in a data memory device, it is read out and used for raster scan of a cathode ray tube display device, etc. In an image data readout device in a system for displaying data using a coding method, the processing device generates a load signal upon receiving the data signal and generates an address signal obtained by decoding the code signal; an address register that inputs and presets a new decoded address signal each time a new decoded address signal is received; an address counter that generates an address signal for reading out the display image data, and the processing device determines from a mode signal included in the initial signal that the scroll display is specified, and reads the code signal. An image data reading device characterized in that an address signal generated by adding a predetermined value to an address signal obtained by decoding is controlled to be supplied to the address register.