JPS60205590A - Linear raster address generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Valve Ijf) The present invention relates to a linear rask address generation circuit in an LCD controller.

(Prior Art) As the number of pixels of an LCD panel approaches the display resolution of a CRT, the ink face of an LCD display device is
There is a tendency to become a T convertible.

As the LCD panel becomes larger, the number of scanning side electrodes increases, the scanning duty ratio decreases, and the contrast deteriorates.
Image quality deteriorates. As a measure to prevent this, LCD
The panel is divided into upper and lower halves, doubling the scanning duty ratio. On the other hand, the LCD controller generates refresh memory addresses for displaying data on the LCD panel, but in the conventional technology, in character mode (
If the character pattern data is stored in the character generator ROM and the character code is used as the ROM address input), when displaying an odd number of lines, the character will straddle the upper and lower boundaries in the middle line, so A column address that could not be specified was created, and characters could not be displayed correctly. Also, considering the system of CRT display device and LCD display device,
I can't use the CRT controller's application software, and I have to build separate software. Also, CR
The memory accessed by the T-controllers ci- and 7 cannot be shared, and a separate memory for the LCD display is required.

(Object of the Invention) This invention was made in view of the above points, and its purpose is to enable continuous addresses to be sent to the refresh memory even when the LCD controller divides odd-numbered lines into upper and lower halves for character display. The object of the present invention is to configure a raster address counter circuit to solve the above problems.

(Summary of the Invention) The main point of this invention is that two types of counters are provided, a raster address counter for the upper surface and a raster address counter for the lower surface, so that the upper surface raster address and the lower surface raster address can be switched and transmitted in a continuous state. That's true.

(Example) Examples of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram of a first embodiment of the present invention, in which an input terminal 1 is an input terminal for a clock (address clock) generated every l raster, a raster address counter 2 for the upper surface, and a raster address counter 2 for the lower surface. Connected to the clock input of counter 6. The output pass line 3 is an output pass line of the upper raster address counter 2 and is connected to the input of the half adder circuit 4. The output path line 3 is also connected to one input of a switching circuit 10 that switches between the raster address on the upper surface and the raster address on the lower surface.

5 is a half adder circuit, and the output thereof is connected to the load data input of the raster address counter 6 for the lower surface. The output pass line 7 is an output pass line of the raster address counter 6 for the lower surface, and is connected to the other side input of the raster address switching circuit 10. The input terminal 8 is an input terminal for a load blind signal generated at the end of the 1 frame, and is connected to the load signal input of the raster address counter 6 for the lower surface. Also,
The input terminal 8 is also connected to a reset signal input of the upper raster address counter 2. The input terminal 9 is an input terminal for a switching signal that switches between the output of the upper raster address counter 2 and the output of the lower raster address counter 6, and is connected to the switching circuit IO. The switching circuit 10 sends the output of the raster address counter 2 for the upper surface to the output 11 when the switching signal is %H", and outputs the output of the raster address counter 6 for the lower surface when the switching signal is 1L".
The output of is sent to output 11.

FIG. 2 is a diagram showing the relationship between the LCD panel P and raster addresses in order to explain the first operation. The operation of FIG. 1 will be explained below using FIG. 2. However, for convenience of explanation, the screen size is 80 characters horizontally and 7 lines! l; 5 lines, 1 font configuration is 8x
8.

The upper surface raster address counter 2 is an octal counter that is reset every frame by a signal from an input terminal 8 at the end of one frame. This top surface raster address counter 2 starts from 6" at [OOO, counts up by the address clock of input terminal IJ:!!11, repeats the octal operation for each row, and becomes [011J at the final line. It is reset by a signal from the input terminal 8 after the final address in FIG. Output to 3.

The top surface raster address (contents of the top surface raster address counter 20 digits) outputted to the output path line 3 is supplied to the switching circuit 10, and at the same time, the half adder circuit 4
When it is "011", that is, the final raster, the adder circuit 4 sets "1" to the least significant bit.
are added and output as 100J to the output of the half adder circuit 4.

After the final memory address is output, this data is input into the lower surface raster address counter 6 by a load signal from the input terminal 8. Therefore, the raster address counter 6 for the lower surface starts from [100J], counts up by the address clock from the input terminal 1, and repeats the operation shown in FIG. 2 every 7 frames. That is, the lower surface raster address determined by the lower surface raster address counter 6 is continuous with the upper surface raster address.

Then, when addressing data on the upper surface, the upper raster address on the output bus line 3 is derived to output 11, and when addressing data on the lower surface, the lower raster address on the output bus line 7 is output. A switching circuit 10 is controlled by a signal from input terminal 9 such that the address is derived at output 11 .

FIG. 3 is a block diagram showing a second embodiment of the invention. In this second embodiment, the half adder circuit is omitted and the output pass line 3 is directly connected to the load data input of the raster address counter 6 for the lower surface. Similarly to the first embodiment, the upper surface raster address counter 2 starts from 000J and counts up by the address clock from the input terminal 1, and counts up 800J for each row.
It repeats without any forwarding action and becomes "011J" on the final line, but in this embodiment, after the final memory address is output, it is counted up to "Ir00J" at a timing that does not affect the display, and then from input terminal 8. It is reset by the signal and returns without any further operation.

Then, the final data "100" of the upper surface raster address counter 2 is input into the lower surface raster address counter 6 by the load signal from the input terminal 8. Therefore, also in this second embodiment, the raster address counter 6 for the lower surface starts from l'-100J, and the raster address for the lower surface by the raster address counter 6 for the lower surface is continuous with the raster address for the upper surface. .

(Effects of the Invention) As explained above, in the circuit of the present invention, two types of raster address counters, a raster address counter for the upper surface and a raster address counter for the lower surface, are provided and the raster addresses are output by switching between them. Even if odd rows are divided into upper and lower rows, the raster addresses are continuous. In addition to being able to use odd rows in character mode, this also means that the CRT controller system and CD
There is an advantage that the display RAM and character generator ROM can be used in common when displaying. Furthermore, it also meets the requirements for using application software that operates a CRT controller.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the linear raster address generation circuit of the present invention, and FIG. 2 is a diagram showing the relationship between the LCD panel and raster addresses to explain the operation of the first embodiment. , FIG. 3 is a block diagram showing a second embodiment of the present invention. 2...Raster address counter for the top surface, 6...Raster address counter for the bottom surface, 0...Switching circuit. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] LC that divides the LCD screen into two and scans the LCD screen.
In the raster address generation circuit of the D7 controller, an upper raster address counter that generates an upper rask address, a lower raster address counter that generates a lower rask address that is continuous with the upper rask address;
A linear rask address generation circuit comprising a switching circuit that switches and outputs two-star addresses from these two two-star address counters.