JPH0725828Y2 - Liquid crystal display information processing device - Google Patents

Description

[Detailed Description of the Invention] <Industrial field of application> The present invention uses a liquid crystal display element composed of R, G, B color dots (hereinafter referred to as "pixels") as a display section to drive this display section. In particular, in regard to the liquid crystal display information processing apparatus for the above, in particular, each pixel is set as an independent minimum drawing unit (hereinafter referred to as “one pixel”), and a large number of these one pixels are arranged to improve display quality and hardware ( The present invention relates to an improvement in a liquid crystal display information processing device for reducing memory.

<Prior Art> An outline of a conventional technology will be described below with reference to the drawings.

FIG. 5 is a block diagram of a conventional liquid crystal display information processing device.

In FIG. 5, 1 is a display unit. This display unit 1
It has a driver circuit 1a composed of a row driver 1a ₁ and a column driver 1a _2, and a liquid crystal display element 1b which regularly arranges R and GB pixels and is sequentially driven by the driver circuit 1a to display a predetermined image. . 2 is a graphic controller (hereinafter abbreviated as "TC") 2a and a frame memory 2b
It is a CRT controller circuit (hereinafter referred to as "CRTC circuit") consisting of and. Here, the G · C 2a starts its operation by the CPU 3 and outputs a control signal for display timing, for example, a horizontal synchronizing signal H _s and a vertical synchronizing signal Vs. or,
The frame memory 2b stores the display data composed of the three primary colors R, G, B, and in order to display a predetermined image on the liquid crystal display element 1b, the corresponding data of R, G, B is read by the G / C 2a. Then, the pixel data G _d, which is composed of parallel data for 4 pixels and 12 bits, is output. 4 is a shift of 12-bit configuration that processes the pixel data G _d into data suitable for display and outputs the serial drive signal S _d to the row driver 1a ₁ , for example, processing the image data G _d for the four pixels. Register 4a
It is a display data processing unit consisting of. At this time, the R, G, B data of the frame memory 2b correspond to the respective R, G, B pixels on the liquid crystal display element 1b, and the address number is, for example, address O (the upper left corner of the liquid crystal display element 1b. When the initial position (starting from R in the figure) is set and the addresses are sequentially sorted to the right side, 1,2, ..., If the end of the first line is 511, from the left of the second line again 512, 513, ... Address, and so on. still. Each pixel of R, G and B is collectively represented as one minimum color drawing unit (hereinafter referred to as "one color pixel").

The row driver 1a ₁ and the column driver 1a ₂ are vertical sync signals.
It is initialized by Vs and outputs a signal indicating the address O to the liquid crystal display element 1b. The horizontal synchronization signal H _s is the drive signal S _d
The row switching operation is performed in synchronization with. Therefore low driver
The contents of 1a ₁ and the display of the row selected by the column driver 1a ₂ are formed on the liquid crystal display element 1b.

In such a configuration, the 12-bit configuration shift register 4a sequentially converts the pixel data G _d for four pixels from the CRTC circuit 2 into the drive signal S _d in one horizontal row according to the color arrangement of the liquid crystal display element 1. Transfer to row driver 1a ₁ . As a result, in the liquid crystal display element 1b, one row is written by the row driver 1a ₁ in such a manner that it is divided into four pixels based on the drive signal S _d . This way, the one row transfer is completed, row driver 1a ₁ becomes the initial state while being shifted to the next row by the column driver 1a ₂ on the basis of the horizontal synchronizing signal H _s, 2 rows from the shift register 4a The pixel data G _{d for} the four pixels of the eye is transferred. In this way, the pixel data is sequentially transferred for every four pixels, so that a predetermined image is finally displayed on the liquid crystal display element 1b.

By the way, since the liquid crystal display element 1b for color display has a mosaic type color arrangement structure with the highest apparent resolution with the same number of pixels, the pitch of each pixel is large, and it is used for viewing from a close range. In many cases, one color pixel is conspicuous.

For example, in a display form in which each pixel is a diagonal mosaic array and the driving method is a modified triangular array by displaying one color pixel over two lines of color lines, a linear pattern such as a meter display is displayed. When the intended use is limited to a large number of items, as shown in FIG. 6 for explaining the problems of the conventional technique, when a straight line is formed vertically, the straight line portion becomes jagged. There is. Further, in view of the application of instrument display, it is currently insufficient in terms of display resolution.

In view of this problem of the conventional technique, the applicant of the present invention has applied for a liquid crystal display information processing device which makes it possible to improve the display quality and draw at high speed by setting each pixel of the liquid crystal display element as one pixel.
Proposed as 0956 (hereinafter referred to as "prior art").

FIG. 7 is a block diagram of a prior art liquid crystal display information processing device.

In FIG. 7, reference numeral 40 denotes a drive signal S _da capable of displaying an arbitrary figure, in which any one pixel of R, G and B of the liquid crystal display element 1b blinks as one independent pixel. The display data processing unit includes a selection circuit 40b and a shift register 40a. Here, the selection circuit 40b is G · C2a.
The pixel data G _d from the frame memory 2b derived by the above, the address signal Ad which is the control signal, and the horizontal synchronization signal H _s
And the vertical synchronizing signal Vs are input, and one of R, G, and B is respectively selected from the pixel data G _d for four pixels corresponding to the address of one pixel forming one pixel of the liquid crystal display element 1b. Selection (basically, one of the pixel data corresponding to the address of one pixel of the liquid crystal display element is selected). Shift register
40a outputs a drive signal S _da based on the pixel data G _d of four pixels selected by the selection circuit 40b (4 pixels) to row driver 1a _1.

Here, the vertical synchronizing signal Vs is the selection circuit 40b, row driver 1
Initialize a ₁ and column driver 1a ₂ . As a result, the column driver 1a ₂ outputs a signal indicating the O address of the liquid crystal display element 1b. The horizontal synchronizing signal H _s performs the row switching operation in synchronization with the drive signal S _d (first row is selected first). Therefore, in the row selected by the column driver 1a ₂ , the contents of the first 4 pixels are displayed on the liquid crystal display element 1b by the signal from the row driver 1a ₁ by the drive signal Sd _a .

The selection circuit 40b receives the address signal Ad from G · C2a,
One of R _i , G _i , and B _i of the pixel data G _d for 4 pixels corresponding to the color of 4 pixels for the corresponding 4 pixels is selected and transferred to the shift register 40a. For example, consider the first pixel (upper left R) in the first row of the liquid crystal display element 1b, which is the first pixel. The corresponding R _i is selected from the R _i , G _i , and B _i of the pixel data G _d by the address signal A _d , and this R _i is led to the row address 1a ₁ via the shift register 40a. The memory of the row address 1a ₁ , for example, outputs this after storing this signal. Therefore, the liquid crystal display element 1b outputs the data R on the upper left.
Lighted or non-lit according to the data of R _i . At this time,
The other data G _i and B _i are left alone. Thereafter, the second pixel, the third pixel, ... Are similarly output.

In this way, when one row is written and the transfer of this row is completed, the column driver 1a _{2 is driven} by the horizontal synchronization signal H _s.
Is operated to shift to the next row and the row driver 1a ₁ is in the initial state, and the same operation is performed for four pixels B, R, ... In the figure. In this way, the display operation for the following rows is sequentially performed, and finally a predetermined image is displayed on the liquid crystal display element 1b.

A specific example of the display at this time is shown in the drawing for explaining the prior art corresponding to FIG. 6 in FIG.

In Fig. 8, the display in which the straight line part is jagged has been improved, resulting in a very neat and natural display form.
It can be seen that the shape can be easily reduced (it can be increased in size). That is, the display resolution in the vertical and horizontal directions is increased, and the liquid crystal display quality is improved.

<Problems to be Solved by the Invention> In the prior art, the product price is high because it is necessary to use a frame memory capacity three times as large as the frame memory capacity actually used for display. There is a problem that

The present invention has been made in view of the problems of this conventional technique, and is configured so that only the required amount is mounted by eliminating the disadvantage that the frame memory has three times the amount required for display. And an inexpensive liquid crystal display information processing device.

<Means for Solving Problems> In the liquid crystal display information processing device of the present invention for achieving the above-mentioned object, each color dot of R, G, B is regularly arranged and driven by a driver circuit. A display unit for displaying a liquid crystal, a CRT controller circuit that starts operation by the CPU and outputs pixel data and a control signal for displaying the liquid crystal, and the driver circuit by processing the pixel data into data suitable for display In a liquid crystal display information processing device comprising a display data processing unit which outputs a drive signal, the CRT controller circuit includes a graphic controller having a drawing function controlled by the CPU, and a color register controlled by the CPU. And a color information selection circuit that selects and outputs color information that is actually displayed by the address signal from the graphic controller. When a pixel is drawn, the drawing signal output from the graphic controller is input to AND the color information from the color information selection circuit and the color information from the color register to obtain an actual value. It is characterized by comprising a color information generating circuit for generating color information to be displayed and a frame memory for storing the color information generated by the color information generating circuit.

<Embodiment> The present invention will be described below with reference to the drawings. In the following drawings, the same parts as those in FIGS. 5 to 8 are designated by the same reference numerals and the description thereof will be omitted.

FIG. 1 is a block diagram of a liquid crystal display information processing apparatus showing a specific embodiment of the present invention.

In FIG. 1, reference numeral 20 denotes a CRTC circuit that starts operation by the CPU 3 and outputs pixel data Gd ₁₀ consisting of R, G, and B for displaying a predetermined image on the display unit 1 and a control signal. this
The CRTC circuit 20 includes a G / C 20a, a frame memory 20b that stores pixels that correspond to the pixels of the display unit 1 in a one-to-one correspondence, a color information generation circuit 20c described in detail below, and special fonts and symbols. It is provided with a reference memory 20d for storing (not necessary if there are no special fonts or symbols), a display output I / F (interface) 20e, and a control output I / F 20f.
Here, the G / C 20a has a drawing function that operates by a drawing command signal α ₁ from the CPU 3 to perform drawing, and outputs data including, for example, 1-bit on / off monochrome information to the data bus D _b1 . In addition, the color information generation circuit 20c is
Controlled by (the drawing color is set) by register information R _c ,
Color information (display color) selection signal (hereinafter referred to as “color information”) R _p that is actually displayed on the display unit 1 by the color register 20b ₁ that outputs G _c and B _c and the address information Ad from the G / C 20a ，
It has a color information selection circuit 20b ₂ for outputting G _p and B _p, and when performing drawing on a certain pixel, monochrome information from G / C 20a, color information R _p , G _p and B _p, and a register Information R _c , G _c , B _c
AND circuits 20b _3a , 20b _3b , 20b _{3c are} ANDed to form an OR
Control signal W from G / C 20a via circuit 20b ₄
Tri-state buffer 2 controlled by _D (write signal)
Via 0b _5, via the tri-state buffer 20b ₆ which is controlled by the control signal R _D from G · C20a (read signal) and outputs actually in the frame memory 20b and generates color information displayed frame It has a function of outputting the color information stored in the memory 20b.

FIGS. 2 and 3 are views for explaining the color information selecting circuit 20b _2, in particular FIG. 2 color information selecting circuit, Figure 3 is to illustrate the circuit of the arithmetic unit f. Further, FIG. 4 is a diagram for explaining the operation of the present invention, showing the operation when the square area is painted in red (R), and the data arrangement is the same as that of the display unit 1, At this time, (A) is the output of the data bus,
(B) shows the contents of the color register, (C) shows the output of the color information selection circuit, (D) shows the frame memory output, and (E) shows the display state.

With reference to these FIGS. 2 to 4, the color information selection circuit 20b ₂
Will be described in more detail.

2 to 4, the color information selection circuit 20b ₂ changes from the address information Ad to the color information as shown in FIG. 4 (C).
This is a circuit that outputs R _p , G _p , and B _p . For the allocation of the display unit 1 and the frame memory 20b, the logical expression of the color information selection circuit 20b ₂ is R _p = [(Addr MOD 3) = 0] G _p = [(Addr MOD 3) = 1] B _p = [(Addr MOD 3) = 2] It can be expressed as (1). The meaning of the expression (1) is, for example, for R _p , when the surplus when the address Addr is divided by 3 becomes 0, R _p becomes true, and for G _p , the surplus when the address Addr is divided by 3. When _p becomes 1, G _p becomes true, and when B _p becomes the surplus when the address Addr is divided by 3, it becomes 2.
It makes B _p true. Since this formula (1) is a special decoder, it can be realized by a combination of AND, OR, and NOT. For example, if the address is 16 bits (A ₀ ~
A concrete example of A ₁₅ ) is as follows.

Addr = 2 ⁰ · A ₀ +2 ¹ · A ₁ +2 ² · A ₂ +… + 2 ¹⁵ · A ₁₅ (2) (However, A _i = 0 or 1) Addr MOD 3 = (2 ⁰ · A ₀ ＋2 ¹・ A ₁ ＋2 ²・ A ₂ ＋… ＋ 2 ¹⁵・ A ₁₅ ) MOD 3 = {(2 ⁰・ A ₀ MOD 3) + (2 ¹・ A ₁ MOD 3) + (2 ²・ A ₂ MOD
3) +… (2 ¹⁵ · A ₁₅ MOD 3)} MOD 3 = (A ₀ +2 · A ₁ + A ₂ +2 · A ₃ +… +2 · A ₁₅ ) MOD 3…
(3) In order to perform this operation by hardware, it is assumed that there is an operator f that obtains a 2-bit output Y (here, Y ₀ , Y ₁ ) for 4-bit inputs X ₀ , X ₁ , X ₂ , X _3. . That is, Y = Y ₀ + 2 · Y ₁ ≡f (X ₀ , X ₁ , X ₂ , X ₃ ) = (X ₀ + 2 · X ₁ + 4 · X ₂ + 8 · X ₃ ) MOD 3 = (X ₀ + 2 · X ₁ + X ₂ + 2 · X ₃ ) MOD 3 (4) Take. Then, the expression (3) becomes Addr MOD 3 = {f (A ₀ , A ₁ , A ₂ , A ₃ ) + f (A ₄ , A ₅ , A ₆ , A ₇ ) + f (A ₈ , A ₉ , A ₁₀ , A ₁₁ ) + f (A ₁₂ , A ₁₃ , A ₁₄ , A ₁₅ )} MOD 3 (5). Here, the output of f (A ₀ , A ₁ , A ₂ , A ₃ ) is B ₀ , B ₁
And then, if similarly defined below, (5) _{formula, Addr MOD 3 = (B 0} + 2B 1 + B 2 + 2B 3 + B 4 + 2B 5 + B 6 + 2B 7) MOD 3 = {f (B 0, B 1, B _{2, B 3) + f (} B 4, B 5, B 6, B 7)} MO
It becomes D 3 (6). Here, the output of f (B ₀ , B ₁ , B ₂ , B ₃ ) is changed to C ₀ , C ₁
Then, if defined in the same way, the formula (6) is given by Addr MOD 3 = (C ₀ + 2C ₁ + C ₂ + 2C ₃ ) MOD 3 = {f (C ₀ , C ₁ , C ₂ , C ₃ )} = D ₀ + 2 · D ₁ (7) and the final 2-bit result D ₀ · D ₁ is obtained. With this, To get Therefore, if the arithmetic unit f is used, the color information selection circuit
20b ₂ can be configured as in FIG.

By the way, since the arithmetic unit f has a truth table as shown in Table 1, it is understood that the circuit configuration as shown in FIG. 3 is sufficient. The circuit of the calculator f in FIG. 3 is PLD (
It can be realized by using an element such as (4) and can be mounted at a low cost and in a small size as compared with the prior art having a large capacity frame memory.

The operation of FIG. 1 configured in this way is as follows.

: The CPU3 uses the signal γ to set the drawing color to the color register 20b.
₁ shows register information R _c , G _c , B _c as shown in FIG. 4 (B).
After setting the contents of, the drawing command signal α ₁ is output to the G / C 20a.

: G ・ C20a is based on the drawing command signal α ₁ and is shown in Fig. 4 (A).
Drawing was carried out like, and outputs the address information Ad to the color information selecting circuit 20b ₂ outputs the monochrome information to the data bus D _b1.

: The color information selection circuit 20b ₂ performs the color information selection as described above, and outputs the color information R _p , G _p , B _{p as} shown in (i) to (iii) of FIG. . At this time, as described above, the pixels of the frame memory 20b and the pixels of the display unit 1 have a one-to-one correspondence, and when the address of the frame memory 20b is determined, the contents of the address are the location of the display unit 1, that is, the specific Of the color information R _{p of} the color information selection circuit 20b ₂ ,
Only one bit of G _p and B _p is valid.

: Register information R _c , G _c , B _c , and color information R _p , G _p , B _p ,
Monochrome information is ANDed in AND circuits 20b _3a , 20b _3b , 20b _{3c respectively}
Color information D _out = R _c · R _p generated by the D state, further integrated by the OR circuit 20b ₄ and controlled by the control signal W _D output from the graphic controller 20a via the tri-state buffer 20b _5. + G _c · G _p + B _c · B _p is output to the frame memory 20b.

: As a result, the information of the color display contents as shown in FIG. 4D is stored in the frame memory 20b.

: The stored color display content is read by the read signal of G / C 20a and output to G / C 20a via the tri-state buffer 20b ₆ controlled by the control signal R _D and via the data bus Db ₂ . Display output I / F20
The data is output from e to the display data processing unit 40. In addition, G ・ C20a
The output signal output from the control output I / F 20f is appropriately controlled and output. In this way, the display as shown in FIG. 4 (E) is made on the display unit 1.

<Effects of the Invention> As described above in detail with reference to the embodiments of the present invention,
According to the liquid crystal display information processing device of the present invention which displays one pixel of the liquid crystal display element by one pixel, since the color information is added after being processed as monochrome information in G and C, it becomes possible to control each pixel. Since the display resolution is 1 pixel per pixel, high-resolution display is possible.
Further, in the prior art, the frame memories are provided separately for R, G and B, and one of them is selected for each pixel at the time of display. Since one of them is selected and stored in the frame memory, there is an effect that the memory amount can be reduced to 1/3 as compared with the prior art.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal display information processing apparatus showing a specific embodiment of the present invention, FIGS. 2 and 3 are diagrams for explaining the color information selection circuit of FIG. 1, and FIG. FIG. 5 is a block diagram of a conventional liquid crystal display information processing device, FIG. 6 is a diagram for explaining problems of the conventional technique, and FIG. 7 is a diagram of the prior art. FIG. 8 is a block diagram of a liquid crystal display information processing device, and FIG. 8 is a diagram for explaining problems of the prior art. 1 ... Display unit, 2, 20 ... CRT controller circuit (CRTC circuit), 20c ... Color information generating circuit, 4, 40 ... Display data processing unit.

Claims (1)

[Scope of utility model registration request] 1. A display unit for displaying liquid crystal by driving a driver circuit in which R, G, B color dots are regularly arranged, and a CP.
A CRT controller circuit that starts operation by U and outputs pixel data and control signals for displaying the liquid crystal,
A liquid crystal display information processing apparatus comprising: a display data processing unit that processes the pixel data into data suitable for display and outputs a drive signal to the driver circuit, wherein the CRT controller circuit includes a drawing controlled by the CPU. A graphic controller having a function, a color register controlled by the CPU, and a color information selection circuit for selecting and outputting color information actually displayed by an address signal from the graphic controller, When drawing a pixel, the drawing signal output from the graphic controller is input, and the color information from the color information selection circuit and the color information from the color register are ANDed and actually displayed. A color information generation circuit for generating color information and the color information generated by the color information generation circuit are stored. A liquid crystal display information processing device characterized by comprising a frame memory.