JPH08202310A - Screen driving circuit - Google Patents

Abstract

PURPOSE: To reduce a manufacturing cost by simplifying circuit constitution required for displays and to perform displays having quick response by suppressing data processing amounts to absolute minimums in the case of diving a display screen into two screens of upper and lower screens and of scanning both screen parallelly. CONSTITUTION: Two counters 20, 21 are provided in this circuit in accordance with upper and lower screens 14a, 14b and also both counters 20, 21 hold addresses while updating addresses of video memories 11 corresponding to scanning positions on screens. The addresses are taken out selectively by a multiplexer 18 and data are read out frown video memories 11 to a data buffer 19 and also the data are transmitted to a display device 10 at a stage in which one pair of data for both upper and lower screens are completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a screen drive circuit in various display devices such as LCDs and ELs, and in particular, it divides a display screen into a plurality of parts and drives the divided screens in parallel for display driving. Regarding things.

[0002]

2. Description of the Related Art Conventionally, there is a strong demand for simultaneously displaying a plurality of screens on a display screen of one display device. For example, in a display device such as an LCD or EL, the display screen 26 is vertically divided into two as shown in FIG. 5B, and the upper and lower screens 14a and 14b are driven in parallel to reduce the scanning speed to half. It is generally practiced to increase the contrast and brightness of the screen.

In such a two-screen drive, the two-screen drive described above is conventionally performed while maintaining consistency with the one-screen drive circuit for scanning as shown in FIG. 5A.
An image memory for storing image data for frames is provided separately from the video memory on the personal computer side, and while updating the data for the image memory, the necessary data in the image memory is sequentially read out to provide an image for two-screen drive. Generally used as data.

On the other hand, the base screen 14 displayed on the full screen
It is also possible to superimpose and display a plurality of smaller sub-screens 14d on c as shown in FIG. 7 (a). At the time of such display, one video frame for display is provided, and necessary display data is transferred from the frame provided for each sub-screen 14d to the above-mentioned video frame for display to configure the screen. The frame data is sent to the display device 10 to display an image.

[0005]

However, in the two-screen driving method described above, it is necessary to provide an image memory in addition to the conventional video memory, and
The circuit configuration becomes complicated due to the need for signal conversion,
This will increase the cost of the entire device.

On the other hand, in the above-described method of superimposing the screen, since it is necessary to transfer the data to the display video frame, when the number of screens to be superposed increases, the data processing amount increases and the data update is delayed. , There was an inconvenience that the display corresponding to the change of the display content could not be performed accurately.

The present invention solves the above-mentioned inconveniences associated with the simultaneous driving of a plurality of screens at a time, and is provided with a number of addressing registers corresponding to the number of screens to be driven simultaneously, and output from the registers. Screen drive that can selectively suppress the circuit configuration required for display or the amount of data processing by switching the address selectively and sending the data retrieved from the video memory directly to the display device for display. The purpose is to provide a circuit.

[0008]

A screen drive circuit 22 according to the present invention retrieves data 16 from a video memory 11 storing an image to be displayed, as schematically shown in FIG. This is for simultaneously displaying a plurality of screens 14 on the display device 10. Here, there are a number of addresses corresponding to the number of screens that can be displayed on the display device 10 at the same time, and an address specifying unit 12 that can specify the address 15 in the video memory 11 and an address output from the address specifying unit 12. The data 16 specified by 15 is retrieved from the video memory 11 and sent to the display device 10.

Further, the address designating means 12 includes an address 15 corresponding to the scanning position A in the display device 10.
The control means 13 sequentially reads the display data 16 from the video memory 11 and displays the display data 10 on the display device 10 while selectively switching the address 15 output from each address designating means 12. Characterized by sending.

The video memory 11 is divided into screens 14 which can be displayed, and the address designating means 12 is provided.
To the address 1 corresponding to each section on the video memory 11.
5 may be output individually, and the control means 13 may be configured to send the address 15 corresponding to the screen 14 having a high display priority to the video memory 11.

The screen drive circuit 22 according to the present invention is shown in FIG.
As described above, the display screen 26 of the display device 10 is vertically divided to form two screens 14a and 14b, and both screens 14a and 14b are scanned in parallel as shown in FIG. 5B to display an image. If possible, two different addresses 15a, 15 on the video memory 11
an address designating unit 17 that enables simultaneous designation of b, a multiplexer 18 that selectively takes out the address 15 output from the address designating unit 17, and a multiplexer 18
Data 16 specified by address 15 retrieved from
Is sequentially read from the video memory 11 and temporarily stored therein.

Further, the addressing section 17 is provided with first and second counters 20 and 21 corresponding to the upper and lower screens 14a and 14b, and displays the value each time one data 16 is read from the video memory 11. The address 15 corresponding to the scanning position A on the device 10 can be updated,
The data buffer 19 includes the first and second counters 2
Data 1 at addresses 15a and 15b specified by 0.21
It is preferable to hold 6a and 16b as one set until read.

[0013]

The display device 10 periodically scans the display screen 26 in the horizontal and vertical directions to display a predetermined image. Here, when a plurality of screens 14 are displayed on the display screen 26 in a superimposed manner, the number of address specifying means 12 corresponding to the number of screens to be superimposed is designated corresponding to each screen 14. Further, each address designating means 12 holds an address 15 for each screen 14 corresponding to the current scanning position A on the display screen 26.

In the control means 13, a plurality of screens 14 are displayed.
The display priority in the case of overlapping is set in advance, and the address with the highest priority is selectively taken out of the plurality of addresses 15 and sent to the video memory 11, and the corresponding data 16 is read out to display device. 10
By sending it to, the display corresponding to the change in the current contents of the video memory 11 is made.

[0015]

As described above, the present invention is provided with the addressing means 12 of a number corresponding to the number of screens to be displayed at the same time, and addresses 15 corresponding to the change of the scanning position A on the screen 14.
And the address 15 to be sent to the video memory 11 is selectively selected. Therefore, the display of the plurality of screens 14 requires the reconstruction of the entire screen using the display-only video memory. Directly, the circuit configuration required for display can be simplified, the manufacturing cost can be reduced, the amount of data processing can be suppressed to a necessary minimum, and a highly responsive display can be performed.

[0016]

2 to 6 show an example in which the screen drive circuit according to the present invention is applied to a drive circuit for two screens. As shown in FIG. CPU via various bus lines 23 such as
24, a general-purpose memory 25 or various devices such as a video memory 11 and the like, while inputting an output signal thereof to the display device 10.

The video memory 11 is, as illustrated in FIG.
At least one frame of image data for each dot on the display screen 26 of the display device 10 is displayed on the display screen 26.
The data can be stored in correspondence with the above display coordinates, and by designating an address on the video memory 11 and applying a read signal or a write signal, data at an arbitrary address can be accessed. ing.

The display device 10 used in this embodiment is a single gradation type such as LCD or EL, and as shown in FIG. 5, the display screen 26 has a resolution of 480 dots vertically and horizontally. An example is shown in which each dot is represented by 1 bit with 640 dots. Therefore, the video memory 11 shown in FIG. 4 has a memory capacity of at least 480 × 640 bits, and data of a bit number corresponding to the bus width of the data bus (4 bits in this embodiment) can be read / written at one time.

Further, the display screen of the display device 10 is shown in FIG.
As shown in (b), the upper screen 14a and the lower screen 14b are divided into two between the 240th line and the 241st line, and both screens 14a and 14b are simultaneously scanned in parallel. ing. That is, while scanning the coordinates (1.1) to (1.4) on the upper screen 14a described above, the corresponding coordinates (241.1) to (241.4) on the lower screen 14b are scanned.

The screen drive circuit 22 has a control signal generating section 28, an address designating section 17 for generating an address on the video memory 11, as shown in the concrete structure of FIG.
A multiplexer 18 that selectively takes out the address output from the address designating unit 17 and sends it to the video memory 11
And a data buffer 19 for temporarily storing the data taken out from the video memory 11.

The control signal generator 28 is a trigger type flip-flop, and as shown in FIG. 6, the output level is inverted every time one pulse-shaped timing signal 29 is input, and a rectangular wave-shaped control is performed. Create signal 30.

The address designating section 17 is provided with first and second counters 20 and 21 so that the addresses 15a and 15b of the portions corresponding to the upper screen 14a and the lower screen 14b in the video memory 11 can be individually designated. ing. That is, the first counter 20 has an address 15a corresponding to coordinates (1.1) to (1.4) of the upper screen 14a as an initial value in advance, and the second counter 21 has an initial value of the coordinates of the lower screen 14b ( The address 15b corresponding to 241.1) to (241.4) is set. Further, the count value thereof increases by the set value in conjunction with the input of the control signal 30 described above, and the first counter 20 sets (240.637) to (2
40.640), the second counter 21 is configured to return to the initial value when it reaches the address corresponding to the coordinates (480.637) to (480.640). .

The multiplexer 18 selectively takes out two kinds of data taken in from the input side in response to the level change of the control signal 30 inputted to the S terminal. In the present embodiment, the input side is connected to the output side of the first and second counters 20 and 21, and the output side end is connected to the address bus 36 of the video memory 11 to thereby obtain the first or second counter. The addresses 15a and 15b designated by 20 and 21 can be selectively taken out to the address bus 36.

The data buffer 19 is composed of three D-type registers 31, 32, and 33. The first and second registers 31 and 32 are connected in series, while the first and third registers 31 and 33 are used for data. It is connected in parallel to the bus 37. Further, the first register 31 is driven by the timing signal 29, while the second and third registers 3 are driven.
2 and 33 are configured to be driven by the control signal 30.

The circuit operation of FIG. 3 will be described below in more detail with reference to the explanatory view shown in FIG. As shown in FIG. 6A, a plurality of horizontal synchronizing signals 35 are provided between two vertical synchronizing signals 34, and between the vertical synchronizing signals 34, 1 to 240 lines of data 16a for the upper screen 14a are provided. , Lower screen 1
Display data 16 of 241-480 lines for 4b
By sending b in parallel while synchronizing with the horizontal synchronizing signal 35, the upper screen 14a and the lower screen 14b are simultaneously scanned.

FIG. 6B shows data 16 from the video memory 11 during scanning of the 1st and 241st lines.
The read timing is described as an example, but other lines are omitted because they are substantially the same as this.

Here, at time t1, the first counter 2
0 is the coordinate (1.1), the second counter 21 is the coordinate (24
1) and the control signal 30 is at the "L" level, the multiplexer 18 stores the address 15a of the first counter 20 in the video memory 11
Is specified in.

At this time, interlocking with the input of the timing signal 29, the first register 31 stores the coordinates (1.1).
The (16) data 16a is read. Further, with the input of the timing signal 29, the control signal 30 changes to the “H” level at time t2. Then, the output of the multiplexer 18 is switched to the side of the second counter 21 and the address 15b corresponding to the coordinate (241.1) is sent to the video memory 11, and at the same time, the second and third registers 32 and 33 simultaneously transfer the data 16 to the data 16. Read. This time,
The second register 32 is the data 16a of the coordinates (1.1) to (1.4) which is the value held in the first register 31, while the third register 33 is connected to the data bus 37 of the video memory 11. Coordinates (241.1) to (2
The data 16b corresponding to 41.4) is fetched, and the upper screen and lower screen data 16a and 16b are simultaneously sent to the display device 10 as one set.

Further, the values of the first and second counters 20 and 21 are respectively updated at the falling time t3 of the control signal 30, and the above operation is repeated from time t4 by the address 15 set at the next read position. Due to
The next one line of data 16 is sent to the display device 10.

In the above-described embodiment, an example in which the image is displayed in binary is shown for the sake of simplicity, but it is needless to say that it can be carried out in substantially the same manner in the case of displaying in a plurality of stages or in color. Further, since the display device 10 used needs to send two kinds of data 16a and 16b at the same time, the data buffer 19 is provided.
If 6 can be sent sequentially, the data buffer 19 can be eliminated. Of course, if the plurality of addresses 15 can be designated alternatively, the address designating means 12 can be appropriately changed and implemented instead of the counter.

FIG. 7 shows an example in which the present invention is applied to a screen drive circuit which enables superimposition display of a plurality of screens 14, and the coordinate position (X1. With Y1) as the upper left corner, a sub screen 14d having a width of X2 and a height of Y2 is superimposed and displayed.
At this time, in addition to the video memory 11 for the base screen 14c, a video memory 11d for the sub screen 14d is provided as shown in FIG. 7B, and the image data 16 to be displayed on the sub screen 14d is provided on the video memory 11d. Is configured to write.

Further, the address designating means 12 for designating the scanning position in the video memory 11 for the base screen 14c.
In addition, an address designating means 12 for designating a corresponding scanning position in the video memory 11d for the sub screen 14d is provided. In the present embodiment, if the address of the upper left corner of the display range indicated by the alternate long and short dash line in FIG. 7B is M1, the address M1 is designated when scanning the coordinate position A (X1, Y1) on the display screen 26. Coordinate position A '(X
1 + X2.Y1 + Y2) is changed in association with the change of the scanning coordinate so that the address of M2 is designated at the time of scanning.

Here, by switching the output of the control means 13 for selectively switching the output from the two addressing means 12 depending on whether or not it is within the display range on the video memory 11d of the sub-screen 14d, The image data 16 is directly sent from the video memory 11d to the display device 10.

If there are a plurality of sub screens 14d,
An addressing means 12 is provided for each video memory provided for each sub-screen, and the display priority of each sub-screen is preset, and the display range of two or more sub-screens at the same time. When entering, the control means 13 selects the address designation means 12 of the sub-screen having a high priority.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a basic configuration of the present invention.

FIG. 2 is a schematic view showing an example in which the present invention is applied to a drive circuit for two screens.

FIG. 3 is a block diagram showing a specific configuration of a screen drive circuit.

FIG. 4 is an explanatory diagram showing a relationship between an address of a video memory and a coordinate position of a display screen.

FIG. 5 is an explanatory diagram showing a scanning procedure of the display screen,
(A) shows a scanning procedure for one screen, and (b) shows a scanning procedure for two screens.

6A and 6B are timing charts showing the relationship between various signals in the screen drive circuit. FIG. 6A shows the relationship between signals for one frame, and FIG. 6B shows the relationship between signals for one scanning line.

7A and 7B are explanatory views showing an example in which the present invention is applied to a window display screen, in which FIG. 7A is a positional relationship of each screen on the display screen, and FIG. 7B is a video memory for a sub screen and a display position. The relationship between

[Explanation of symbols]

 10 display device 11 video memory 12 address designating means 13 control means 14 screen 15 address 16 data 17 address designating section 18 multiplexer 19 data buffer 20 first counter 21 second counter 22 screen drive circuit 23 bus line 24 CPU 25 memory 26 display screen 28 control signal generator 29 timing signal 30 control signal 31 first register 32 second register 33 third register 34 vertical synchronization signal 35 horizontal synchronization signal 36 address bus 37 data bus

Claims (3)

[Claims] 1. A screen drive circuit for taking out data (16) from a video memory (11) storing an image to be displayed and displaying a plurality of screens (14) on a display device (10) at the same time. , Addressing means (12) capable of designating the address (15) in the video memory (11) by the number corresponding to the number of screens which can be simultaneously displayed on the display device (10), and the address designating means Address output from (12) (1
The data (16) specified in 5) is transferred to the video memory (1
1) and a control means (13) for sending it to the display device (10), wherein the addressing means (12) is the display device (1).
The address (15) corresponding to the scanning position A in 0) can be output, and the control means (13) is provided with each address designating means (12).
A screen drive circuit, wherein display data (16) is sequentially read from a video memory (11) and sent to a display device (10) while selectively switching an address (15) output from the device. 2. The video memory (11) is divided for each screen (14) that can be displayed, and the addressing means (12) includes a video memory (1).
1) The address (15) corresponding to each of the above categories is individually output, and the control means (13) sends the address corresponding to the screen having a high display priority to the video memory (11). The screen drive circuit according to claim 1, wherein: 3. A display screen of a display device (10) is vertically divided to form two screens (14a) (14b), and both screens (14a) (14b) are scanned in parallel to display an image. And a screen drive circuit that enables to specify two different addresses (15) on the video memory (11) at the same time, and an output from the address specification unit (17). Address (1
5) is selectively taken out from the multiplexer (18), and the address (1) taken out from the multiplexer (18)
And a data buffer (19) for sequentially reading out the data (16) specified in 5) from the video memory (11) and temporarily holding the data (16).
a) (14b) corresponding to the first and second counters (2
0) and (21) each time one data (16) is read from the video memory (11), the value is read at the address (1) corresponding to the scanning position A on the display device (10).
5) A screen drive characterized in that the data buffer (19) can be updated, and the data buffer (19) holds data of addresses individually designated by the first and second counters (20) and (21) until one set is read out. circuit.