JPH10207428A - Display controller and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display controller and a display device, wherein the amount of current consumption necessary for data transfer between an image memory and a displaying means. SOLUTION: The gradation of each display dot of an LCD panel 1 is decided by an ON/OFF ratio in 15 frames. Since a driver 2 has an internal memory 2a for holding the ON/OFF of each display dot, data transfer is carried out only for a display dot having middle gradation. At this time, since a bit (1) 2 corresponding to the pixel of the middle gradation is stored in a frame buffer 3b and (1) 2 is stored in a bit corresponding to a line having the pixel of middle gradation in a cache memory 5a, a controller 5 needs to search only gradation data corresponding to the display dot of middle gradation by referring to these memories without referring to all gradation data of an image data storage section 3a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for controlling a display gradation of each display dot of a liquid crystal display device or the like based on image data (gradation data) written in an image memory such as a VRAM. Further, the present invention relates to a display device including the display control device.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration example of a conventional display device. In this figure, the screen size of a liquid crystal display panel (hereinafter referred to as “LCD panel”) 1 is 320 × 240 pixels, and each pixel is red (R), G (green), B (blue). Are formed. The storage capacity of the image data storage unit 3a constituted by an IC memory such as a VRAM is 320 × 240 × 3.
× 4 = 921,600 bits = 115,200 bytes, and each display dot (320 × 240
× 3 dots), 4-bit gradation data is assigned to each. Thus, in each display dot of the LCD panel 1, 16 gradations, that is, (0
000) 2 to (1111) 2.
In FIG. 4, the image data storage unit 3a is provided with two, one for the front screen and the other for the back screen, for performing the screen switching process. When the grayscale data (DA) is input from the controller 105 in synchronization with the clock, the driver 102 sequentially drives the corresponding display dots on the LCD panel 1 so that the grayscale data indicates the grayscale display. I do.

In such a configuration, the CPU 4 comprises:
Write arbitrary image data (gradation data for one screen) to the image data storage unit 3a. On the other hand, the controller 105
Each time a predetermined frame signal (pulse signal at an interval of 1/150 second) is input, the grayscale data in the image data storage unit 3a is sequentially read from the head address, and each read grayscale data is read out together with the address. , Driver 102
Transfer to The driver 102 drives the display dots corresponding to the transferred address so that the display dots are represented by the gradation data indicated by the transferred gradation data. Each time the frame signal is input, the above processing is repeated, so that an image corresponding to the image data written by the CPU 4 is displayed on the LCD panel 1.

[0004]

By the way, in the above-mentioned conventional display device, the controller 105 reads all the gradation data in the image data storage section 3a every time a frame signal is inputted, and reads the gradation data. Since all the gradation data is transferred to the driver 102, if the screen size of the LCD panel 1 is large (for example, 320 × 240 pixels, as in the example shown in FIG. 4),
The amount of data transfer between the image data storage unit 3a and the controller 105 and between the controller 105 and the driver 102 becomes extremely large. As a result, the conventional display device has a problem that the current consumption for the data transfer is very large.

The present invention has been made under such a background, and by reducing the amount of data transfer between the image memory and the display means, the current consumption required for the data transfer can be suppressed. It is an object to provide a display control device and a display device.

[0006]

According to the present invention, there is provided gradation information for storing gradation information indicating a display gradation of a display dot corresponding to each display dot of a display means comprising a plurality of display dots. A storage unit and a first divided region which is a region obtained by dividing the storage region of the gradation information storage unit into a plurality of regions, wherein at least one or more of the gradation information stored in each of the first divided regions is First presence / absence information storage means for storing first presence / absence information indicating a first predetermined value in the case of an intermediate gradation corresponding to each first divided area; Is divided into a plurality of areas, at least one of the first presence / absence information stored in each of the second divided areas is the first predetermined value. In the case, the second presence / absence information indicating the second predetermined value is assigned to each of the second divided areas. Writing the first presence / absence information into the first presence / absence information storage unit based on the gradation information stored in the gradation information storage unit; First presence / absence information writing means;
A second presence / absence information writing unit that writes the second presence / absence information into the second presence / absence information storage unit based on the first presence / absence information stored in the first presence / absence information storage unit; Based on the second presence / absence information stored in the second presence / absence information storage means, at least one of the first presence / absence information stored in the second divided area constituting the first presence / absence information storage means First detecting means for detecting only a second divided area in which at least one of the first predetermined values is the first predetermined value, and first presence / absence stored in the second divided area detected by the first detecting means A first information constituting the gradation information storage means based on the information;
A second detecting means for detecting only a first divided area in which at least one of the stored gradation information is an intermediate gradation, and a second detecting means for detecting the first divided area which is detected by the second detecting means. A gray-scale information reading means for reading and outputting only gray-scale information which is an intermediate gray-scale from one divided area; storing gray-scale information output by the gray-scale information reading means; And driving means for driving and displaying the display dots corresponding to the gradation information at the display gradation indicated by the gradation information. Thus, according to the present invention, the first presence / absence information writing unit writes the first presence / absence information into the first presence / absence information storage unit based on the gradation information stored in the gradation information storage unit. The second presence / absence information writing means stores the second presence / absence information in the second presence / absence information storage means based on the first presence / absence information stored in the first presence / absence information storage means.
Is written. Then, the first detecting means is configured to store, based on the second presence / absence information stored in the second presence / absence information storage means, a second divided area constituting the first presence / absence information storage means. Only the second divided area in which at least one of the first presence / absence information is the first predetermined value is detected, and the second detecting means detects the second divided area detected by the first detecting means. Based on the stored first presence / absence information,
From among the first divided areas constituting the gradation information storage means,
Only the first divided region in which at least one of the stored gradation information is an intermediate gradation is detected. Thereby, the gradation information reading means reads only the gradation information which is the intermediate gradation from the first divided area detected by the second detection means, outputs the gradation information, and the driving means outputs the gradation information. The tone information output by the tone information reading means is stored, and based on the stored tone information, a display dot corresponding to the tone information is driven and displayed at a display tone indicated by the tone information. Therefore, the gradation information reading means can read only the gradation information which is an intermediate gradation from the gradation information storage means without referring to the entire area of the gradation information storage means. In some cases, current consumption for data transfer between the gradation information storage means and the display means can be suppressed low.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration example of a display device according to an embodiment of the present invention. In this figure, the LCD panel 1 is the same as that shown in FIG. Hereinafter, each pixel of the LCD panel 1 is designated by coordinates such as “pixel (m, n)” (where m is an integer of 1 ≦ m ≦ 320,
n is an integer of 1 ≦ n ≦ 240).

[0008] The driver 2 has a built-in memory 2a. The storage capacity of the built-in memory 2a is 320 × 24
0 × 3 = 230,400 bits = 28,800 bytes, and each display dot (320 × 240
× 3 dots), one bit is assigned to each. The driver 2 has a built-in memory 2a
Based on the stored contents, each display dot of the LCD panel 1 is driven to an ON state or an OFF state. That is, if the data (one bit) corresponding to a certain dot on the LCD panel 1 is (1) 2 in the built-in memory 2a, the driver 2 turns the display dot on, and if it is (0) 2. If so, it is turned off.

The VRAM 3 comprises an image data storage section 3a and a frame buffer 3b. The storage capacity of the image data storage unit 3a is 320 × 240 × 3 × 4 = 92.
1,600 bits = 115,200 bytes. In this device, each display dot (320 × 24
By assigning 4 bits of the image data storage unit 3a to (0 × 3 dots), 16 gradations, ie, (0000) 2 to (11) in each display dot.
11) Two gradation displays are possible.

Two image data storage units 3a having the same configuration are provided, one of which is used as a display memory (front screen) and the other is used as a screen rewriting memory (back screen). You. The present invention is applicable to a case where the image data storage unit 3a is provided for only one screen or a case where the image data storage unit 3a is provided for three screens or more.

On the other hand, the storage capacity of the frame buffer 3b is 320 × 240 = 76,800 bits = 9,600
Byte, and each pixel of the LCD panel 1 (320 ×
1 bit is assigned to each of them (240 pixels). Hereinafter, here, the frame buffer 3
In b, data (1 bit) corresponding to the pixel (m, n) of the LCD panel 1 is designated by coordinates such as "data of bit coordinates (m, n)".

The CPU 4 writes arbitrary image data to the image data storage unit 3a via the controller 5 in accordance with a program or an external input. The controller 5
Refreshes the image data storage unit 3a in synchronization with a pulse signal (frame signal) input at an interval of 1/150 second, and transfers the image data stored in the image data storage unit 3a to the driver 2. . Details of the operation of the controller 5 will be described later.

The controller 5 has a refresh flag (1 bit: not shown) inside. CPU
4 sets the refresh flag to (1) 2 to notify the controller 5 when the writing of the image data to the image data storage unit 3a is completed.
Further, the controller 5 has a cache memory 5 therein.
a. The storage capacity of the cache memory 5a is 240 bits = 30 bytes.
1 bit is assigned to each row (240 rows). Hereinafter, here, the cache memory 5
In a, data (1 bit) corresponding to the n-th row of the LCD panel 1 is designated by a number such as "data of bit number n".

Next, the operation of the display device having the above configuration will be described. First, the principle of displaying gradation in the present device will be described. FIG. 2A is an explanatory diagram showing an example of the gray scale display of the LCD panel 1, and FIG.
FIG. 9 is an explanatory diagram illustrating a processing example of the present apparatus when displaying the gradation display example illustrated in FIG. Here, the numbers (001 to 320 and 001 to 240) shown in FIG.
The coordinates of each pixel on the LCD panel 1 are shown. Also, “R” shown in FIG.
0, 50) and a pixel (120, 55) as a diagonal point indicate that a red display is performed with 100% gradient. Similarly, “8R / 15” is
This display area is displayed in red with a gradation of 8/15 (≒ 53%), and “R / 15” indicates that this display area is displayed in red with a gradation of 1/15 (≒ 7%). Respectively. Also, as shown in FIG.
The same applies to G ”(green display) and“ B ”(blue display).

On the other hand, each frame (first frame) shown in FIG.
Frames to the fifteenth frame show the display state of the LCD panel 1 in a certain extremely short time (specifically, 1/150 second). In this device, one display screen is configured by displaying 15 frames continuously and sequentially and repeatedly. At this time, since 15 frames are sequentially displayed at an interval of 1/150 second, the present apparatus displays 10 screens per second (one screen is composed of 15 frames). Also,
Nine squares or squares shown in each frame of FIG. 2B correspond to each display area shown at the same position in FIG. 2A. Here, Δ indicates that all display dots in the display area are ON, and □ indicates that all display dots in the display area are OFF.

As shown in FIG. 1, in this apparatus, one screen is composed of 15 frames, and the ratio of the number of display dots in the ON state to the number of display dots in the OFF state in the 15 frames is represented by the following formula. The gradation of the display dot in one screen is determined. For example, the display area in FIG.
In the case of displaying red with a gradation of 15/15 (= 100%) as in R ″, as shown in FIG. 2B, the corresponding display dots are turned on (■) in all the frames. The display area "8" in FIG.
In the case of displaying red with a gradation of 8/15 (≒ 53%) as in R / 15 ″, as shown in FIG. 2B, the corresponding display in the first to eighth frames is performed. The dots are turned on (■), and the corresponding display dots are turned off (□) in the ninth to fifteenth frames, and the display area “R / 15” in FIG.
As shown in FIG. 2B, when displaying red at a gradation of 1/15 (≒ 7%), as shown in FIG. 2B, the corresponding display dot is turned on (■) in the first frame. In the second to fifteenth frames, the corresponding display dots are turned off (□).

Further, as described above, in this device, each bit of the internal memory 2a of the driver 2 is stored in the LCD panel 1
The display content of each bit of the built-in memory 2a, that is, (1) 2 or (0) 2 is displayed as it is on the LCD panel 1 as it is. Since the state becomes the ON state or the OFF state, each bit of the internal memory 2a is rewritten to (1) 2 or (0) 2 in accordance with the display timing of each frame shown in FIG. , 16 gradations can be displayed.

The above is the description of the principle of displaying gradation in the present apparatus. In this apparatus, as shown in FIG.
The gradient is determined by the ratio between the ON state and the OFF state in the five frames, and the driver 2 has a built-in memory 2a for storing the state of the display dot for each display dot. 100% gradient
In the case of (15/15) or 0% (0/15), once (1) 2 or (0) 2 is written to the corresponding bit in the internal memory 2a, the value is retained. Thereafter, display of the gradation (100% or 0%) can be continued without receiving data supply from the controller 5.

Also, the gray scale of the display dot is the intermediate gray scale (0%
Even if the gradation is greater than 100%, the value (1) 2 or (0) 2 written in the internal memory 2a of the driver 2 is held until the next value is written. After writing (1) 2 in the first frame, (0) 2 is written at a timing (ie, frame number) corresponding to the halftone, so that the ON state and the OFF state in the 15 frames can be switched. The ratio, that is, the gradient, can be freely determined. That is, in the present apparatus, even when the gradation of the display dot is an intermediate gradation, (1) 2 and (0) 2 in 15 frames (that is, in 1/10 second).
Is written once at a maximum, whereby the display of the intermediate gradation can be performed.

As described above, in the present apparatus, in order to express the gradation, the contents stored in the internal memory 2a of the driver 2 are written in synchronization with the display timing of each frame (ie, in synchronization with the frame signal). You can change it. Therefore,
Next, the rewriting operation of the built-in memory 2a by the controller 5 will be described.

First, when an initial display of a screen is performed immediately after power-on or the like, the CPU 4 stores the image data to be displayed via the controller 5 in the image data storage section provided in the VRAM 3. The data is written into one of the memory cells 3a (display memory side). When all the image data has been written, the CPU 4 sets the refresh flag inside the controller 5 to (1) 2. On the other hand, when the currently displayed screen is changed, the CPU 4 transfers the image data to be displayed to the other (screen rewriting) of the two image data storage units 3 a provided via the controller 5. Memory side). And CPU ・ 4
Sets the refresh flag inside the controller 5 to (1) 2 at the actual screen switching timing after writing all the image data. Alternatively, it is also possible to directly write the data on the display memory side of the image data storage unit 3a.

FIG. 3 is an explanatory diagram showing an example of storage contents of the cache memory 5a, the frame buffer 3b, and the image data storage section 3a in the present apparatus. FIG. 2 shows a specific example.
When the display shown in (a) is performed on the LCD panel 1, corresponding data shown in FIG. 3 is written. Here, the numbers (001 to 320 and 001) shown in FIG.
To 240) indicate the coordinates of each pixel on the LCD panel 1. As described above, the storage capacity of the cache memory 5a is 240 bits, and one bit is assigned to each row (240 rows) of the LCD panel 1. The storage capacity of the frame buffer 3b is 320 × 240 bits, and the LCD panel 1
Corresponding to each pixel (320 × 240 pixels),
One bit is assigned to each. The storage capacity of the image data storage unit 3a is 320 × 240 × 3 × 4.
Bit, and each display dot (320
(* 240 * 3 dots), 4 bits are allocated to each.

When the writing of image data by the CPU 4 is completed and the refresh flag is set to (1) 2, the controller 5 synchronizes with the input of the frame signal to execute the following gradation data transfer processing, frame The write processing of the buffer 3b and the cache memory 5a is performed.

First, the controller 5 is an image data storage unit (hereinafter simply referred to as an "image data storage unit") whose image data is updated by the CPU 4 among the two image data storage units 3a. ) Is read from the memory 3a) (4 bit data) corresponding to the red dot of the pixel (1, 1). In the example shown in FIG. 3, in the data (000) 16 stored at the coordinates (001, 001) in the image data storage unit 3a, the leftmost “0” of three “0” s arranged in a row is a pixel. This corresponds to the gradation data of the red dot of (1, 1). And the controller 5
Based on the gradation data (and its address), a transfer process described below is performed on the internal memory 2a of the driver 2.

Next, the controller 5 operates in the same procedure,
A read process and a transfer process of the gradation data corresponding to the green dot of the pixel (1, 1) are performed. Further, the controller 5 performs a read process and a transfer process of the gradation data corresponding to the blue dot of the pixel (1, 1) in the same procedure. Here, if the gradation data corresponding to at least one of the three dots constituting the pixel (1, 1) is other than (0) 16 or (F) 16, the controller 5 sets the frame data in the frame buffer 3b. Write (1) 2 to the bit at bit coordinate (1,1). FIG.
In the example shown in FIG. 5, the pixel (1, 1) in the image data storage unit 3a
Since the gradation data of all three dots constituting 1) are (0) 16, the controller 5 sets the bit of the bit coordinates (1, 1) to (0) 2 in the frame buffer 3b.

Hereinafter, the controller 5 operates in the same procedure.
For each of the pixels (2, 1) to (320, 1), each display dot (R, G,
B) reading processing and transfer processing of the gradation data corresponding to
Then, a writing process to the frame buffer 3b is performed. At this time, in the frame buffer 3b, bits corresponding to the pixel group in the first row, that is, (1) 2 of the bits of bit coordinates (1,1) to (320,1)
If there is at least one bit that is
(1) 2 is written to the bit corresponding to the first row in the cache memory 5a, that is, the bit of bit number 1.

When the processing for the pixel group in the first row, that is, each of the pixels (1, 1) to (320, 1) is completed, the controller 5 then proceeds to the second row in the same procedure. Pixel group, ie, pixel (1,
2) to (320, 2), for each pixel, display processing (transfer processing) of gradation data corresponding to each display dot (R, G, B) constituting the pixel, and transfer to the frame buffer 3b. Is performed. Then, similarly to the pixel group on the first row, the controller 5 stores the bit corresponding to the pixel group on the second row, that is, the bit coordinates (1, 2) to (32) in the frame buffer 3b.
When there is one or more bits of (1) 2 among the bits of (0, 2), (1) 2 is written to the bit of bit number 2 in the cache memory 5a.

Hereinafter, the controller 5 performs the same processing.
The process is sequentially performed on the pixel groups on the third to 240th rows. Here, for example, in the example shown in FIG. 3, the pixels 3 (200, 50) of the image data storage unit 3a
Of the dots, the display dot corresponding to red has gradation data of (8) 16 = (1000) 2, so the controller 5 sets the bit of the bit coordinate (200, 50) in the frame buffer 3b to ( 1) It is 2. Correspondingly, the controller 5 controls the cache memory 5a
, The bit corresponding to the 50th row, that is, the bit of bit number 50 is (1) 2.

After the transfer of the gradation data to the driver 2 and the writing of the frame buffer 3b and the cache memory 5a are completed in the above-described procedure, the CPU 4 keeps writing until the next image data is written (updated). The controller 5 repeats the following process of rewriting the stored contents of the internal memory 2a in synchronization with the frame signal. In addition,
As described above, in the present apparatus, one display screen is configured by displaying 15 frames continuously and sequentially and repeatedly. Further, as described above, the frame signal is a pulse signal input at an interval of 1/150 second. That is, when a frame signal is input, the controller 5 waits until the next frame signal is input (1).
/ 150 seconds), image data transfer processing is performed for one frame (tentatively, the t-th frame). When the next frame signal is input, the controller 5
Performs image data transfer processing on the (t + 1) th frame. Hereinafter, each time a frame signal is input, processing for each frame is sequentially performed. Of course, the first
After the processing for five frames, the process returns to the processing for the first frame.

Therefore, when a frame signal is first input, the controller 5 starts processing for the first frame. Here, the controller 5 first reads data (1 bit) of bit number 1 from the cache memory 5a. When the data is (0) 2, the controller 5 reads the data (1 bit) of the bit number 2 from the cache memory 5a. Hereinafter, the controller 5 operates until (1) 2 is read.
Data (1 bit) is sequentially read from the cache memory 5a.

When the data of the bit number n of the cache memory 5a is (1) 2, the controller 5
Is the bit coordinate (1, n) from the frame buffer 3b.
Is read (1 bit). When the data is (0) 2, the controller 5 sends the data (1) of the bit coordinates (2, n) from the frame buffer 3b.
Bit). Hereinafter, the controller 5 includes (1)
Until 2 is read, data (1 bit) corresponding to the pixel in the n-th row is sequentially read from the frame buffer 3b.

When the data of the bit coordinates (m, n) of the frame buffer 3b is (1) 2, the controller 5 reads the data of the pixel (m, n) from the image data storage unit 3a as a red dot. The corresponding gradation data (4 bits) is read. When the gradation data is (0) 16 or (F) 16, the controller 5 does not perform the transfer process. On the other hand, if the gradation data is neither (0) 16 nor (F) 16, the controller 5
Is based on the gradation data (and its address)
The transfer process described below is performed on the internal memory 2a of the driver 2.

Next, the controller 5 reads the gradation data (4 bits) corresponding to the green dot of the pixel (m, n) from the image data storage unit 3a. When the gradation data is (0) 16 or (F) 16, the controller 5 does not perform the transfer process. On the other hand, when the gradation data is neither (0) 16 nor (F) 16,
The controller 5 performs a later-described transfer process to the internal memory 2a of the driver 2 based on the gradation data (and the address thereof).

Finally, the controller 5 reads gradation data (4 bits) corresponding to the blue dot of the pixel (m, n) from the image data storage unit 3a. When the gradation data is (0) 16 or (F) 16, the controller 5 does not perform the transfer process. On the other hand, if the gradation data is neither (0) 16 nor (F) 16, the controller 5 sends the data to the internal memory 2 a of the driver 2 based on the gradation data (and its address). , A transfer process described later is performed.

Hereinafter, the controller 5 sends the data (1) corresponding to the pixel in the n-th row from the frame buffer 3b.
) To the data at the bit coordinates (320, n)
If the data is (1) 2, the above-described gradation data reading process is performed for each dot (R, G, B) of the pixel, and if necessary, the floor is read. Key data transfer processing. Then, when the processing for the bit corresponding to the last pixel of the n-th row, that is, the bit of the bit coordinate (320, n) is completed in the frame buffer 3b, the controller 5 returns to the reading processing from the cache memory 5a. . Then, in the cache memory 5a, the last bit number 240
Is completed, the process for the first frame is completed.

When the next frame signal is input, the controller 5 operates in the same procedure as the first frame.
The processing for the second frame is performed. Hereinafter, every time a frame signal is input, the controller 5 sequentially repeats the same processing for each frame while incrementing the frame number to be processed. The above is the description of the rewriting operation of the built-in memory 2a by the controller 5.

Next, the transfer processing of the gradation data by the controller 5 will be described. In the present embodiment, whether to transfer to the internal memory 2a based on the frame number of the frame currently being processed (first frame to fifteenth frame) and the gradation data read from the image data storage unit 3a Is determined. That is, if the above-mentioned gradation data (gradation data read from the image data storage unit 3a) is (0) 16, the controller 5 transfers (0) 2 if the frame currently being processed is the first frame. And the second
If the frame is the 15th frame, no data is transferred.
If the gradation data is (1) 16, the controller 5 transfers (1) 2 if the frame currently being processed is the first frame, and transfers (0) 2 if it is the second frame. In the case of the third to fifteenth frames, no data is transferred. When the gradation data is (2) 16 to (D) 16 and the gradation data is (p) 16, if the frame currently being processed is the first frame, (1) 2 is transferred, and if the second frame to the p-th frame, no data is transferred, and if the (p + 1) -th frame, (0)
2 is transferred, and if the frame is the (p + 2) th frame to the fifteenth frame, no data is transferred. If the gradation data is (E) 16, the controller 5 transfers (1) 2 if the frame currently being processed is the first frame, and
If the frame is the 14th frame, no data is transferred, and if it is the 15th frame, (0) 2 is transferred. When the gradation data is (F) 16, the controller 5 transfers (1) 2 if the frame currently being processed is the first frame, and transfers data if the frame is currently in the second to fifteenth frames. do not do.

The data (1) 2 or (0) 2
Is transferred, the address (coordinate data on the LCD panel 1) of the gradation data corresponding to the data is also transferred. The driver 2 rewrites the corresponding bit data in the internal memory 2a to the transfer data (1) 2 or (0) 2 based on the address.

The description of the operation of the display device having the above configuration is completed. As described above, in the present apparatus, data transfer to the driver 2 only needs to be performed with respect to display dots whose gradation is intermediate gradation (1/15 to 14/15). At this time, according to the present apparatus, (1) 2 is stored in the bit of the bit coordinate (m, n) corresponding to the pixel of the intermediate gradation (having the display dot) in the frame buffer 3b. Also, in the cache memory 5a, since (1) 2 is stored in the bit of the bit number n corresponding to the row having the pixel of the intermediate gradation (having the display dot), the controller 5 Even without referring to all the gradation data in the data storage section 3a, the image data storage section 3a refers to the storage contents of the cache memory 5a and the frame buffer 3b, and stores the gradations corresponding to the display dots of the intermediate gradation. Only data can be found. For the above reasons, according to the present apparatus, the amount of gradation data read from the image data storage unit 3a and the amount of data transferred to the driver 2 can be considerably reduced as compared with the conventional apparatus.

Although the embodiment of the present invention has been described in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and changes in the design and the like can be made without departing from the gist of the present invention. Even if there is, it is included in the present invention. For example,
In the present embodiment, each memory (built-in memory 2a, VR
The data read / write between the AM 3 and the cache memory 5a) and the controller 5 may be performed in byte units or bit units.

In the present embodiment, the storage capacity of the frame buffer 3b is set to 320 × 240 = 76,800 bits, and each pixel (320 × 240
1 bit is assigned to each pixel, however, the form of division of the display screen of the LCD panel 1 and the storage capacity of the corresponding frame buffer 3b are not limited to the above example. The storage capacity of the frame buffer 3b is 2 × 240 = 480 bits, and each row (320 pixels) of the LCD panel 1 is
Various combinations are possible, such as dividing into left and right by 160 pixels each, and allocating each bit (480 bits) of the frame buffer 3b to each of the 480 (= 2 × 240) divided regions generated thereby. .
Similarly, the correspondence between the cache memory 5a and the LCD panel 1 is not limited to the example shown in the present embodiment.

In each of the above embodiments, one screen is composed of 15 frames, and the gradation of the display dot in one screen is determined by the ratio of the ON state / OFF state in the 15 frames. However, the number of frames constituting one screen is not limited to 15, and may be smaller or larger.

Next, the correspondence between each means described in the claims and this embodiment will be described. Gradation information storage means ... image data storage section 3a first presence / absence information storage means ... frame buffer 3b second presence / absence information storage means ... cache memory 5a first presence / absence information writing means ... controller 5 second Presence / absence information writing means ... controller 5 first detection means ... controller 5 second detection means ... controller 5 gradation information reading means ... controller 5 driving means ... driver 2 display means ... LCD panel 1 Gradation information writing means CPU 4

[0044]

The following is an example relating to a comparison of the data transfer amount between the conventional apparatus (see FIG. 4) and the above embodiment (see FIG. 1). The conditions of the present embodiment are as follows. The size of the LCD panel 1 is 320 × 240 pixels. Each pixel of the LCD panel 1 has red (R), G
(Green) and B (blue). In the LCD panel 1, each display dot can be displayed in 16 gradations (0/15 to 15/15). 1/4 of the display screen of the LCD panel 1 has a gradation of 8/15
The intermediate gradation of (# 53) is used, and the remaining gradation is 0% or 1
00%. In the conventional apparatus and the above-described embodiment, the frequency of the frame signal is the same (150 Hz).

The results of the embodiment under the above conditions are as follows. (1) Conventional device a. Transfer amount from the controller 105 to the driver 102 In the conventional device, data (1 bit) indicating the ON / OFF state of all display dots must be transferred to the driver 102 in every frame, so that one screen (frame) The transfer amount per (15 sheets) is 320 × 240 × 3 × 15 = 3,456,000 bits = 432,000 bytes.

B. Transfer amount from image data storage unit 3a to controller 105 In the conventional device, gradation data (4 bits) of all display dots
Must be read from the image data storage unit 3a for all frames, so that one screen (frame 1
The transfer amount per (5 sheets) is 320 × 240 × 3 × 4 × 15 = 13,824,000 bits = 1,728,000 bytes. However, in this case, it is necessary to transfer an address for designating the gradation data to be read. Therefore, the actual transfer amount is twice this, that is, 1,728,000 × 2 = 3,456,000 bytes. Becomes

C. Total a. And b. Is added to one screen (frame 15
The transfer amount per the conventional device is 432,000 + 3,456,000 = 3,888,000 bytes.

(2) The above embodiment a. Transfer amount from the controller 5 to the driver 2 In the above embodiment, only the display dots (1/4 of all dots) for displaying the intermediate gradation are turned on / off.
Since the data (1 bit) indicating the OFF state only needs to be transferred for two frames, the transfer amount per one screen (15 frames) is 320 × 240 × 3 × (１ ／) × 2 = 115, 200 bits = 14,400 bytes. However, in the above embodiment, along with the above data,
Coordinate data (address) for specifying the display dot
Must be transferred, the actual transfer amount is this 2
Double, ie, 14,400 × 2 = 28,800 bytes.

B. In the above embodiment, the frame buffer 3b is accessed based on the storage contents of the cache memory 5a, and the image data storage unit 3a is accessed based on the storage contents of the frame buffer 3b. I do. Here, the cache memory 5
Since a is built in the controller 5, only the transfer amount from the frame buffer 3b and the image data storage unit 3a poses a problem from the viewpoint of current consumption during transfer. Here, the transfer amount from the frame buffer 3b is 320 × (240/2) = 38,400 bits = 4,800 bytes. On the other hand, the transfer amount from the image data storage unit 3a is (320/2) × (240/2) × 3 × 4 × 2 = 460,800 bits = 57,600 bytes. However, in this case, it is necessary to transfer an address for specifying the gradation data to be read, so the actual transfer amount is twice this, that is, 57,600 × 2 = 115,200 bytes. Therefore, the total transfer amount at the time of accessing the VRAM · 3 is 4,800 + 115,200 = 120,000 bytes.

C. Total a. And b. Is added to one screen (frame 15
The data transfer amount per the above-mentioned embodiment is 28,800 + 120,000 = 148,800 bytes.

(3) Comparison result As described above, in the above embodiment, compared with the conventional device,
The total data transfer amount per one screen (15 frames) is about 1/26 ($ 3,888,000 $ 148,80
0), and accordingly, the current consumption also decreases. Further, in the present embodiment, the area of the intermediate gradation is set to と し た of the display screen of the LCD panel 1 as the above condition, but the smaller the area of the intermediate gradation, the smaller the area between the conventional apparatus and the present embodiment. The current consumption difference is further increased.

[0052]

As described above, according to the present invention, the amount of data transferred between the gradation information storage means and the display means is reduced, so that the current consumption required for the data transfer can be suppressed. There is an effect that.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a display device according to an embodiment of the present invention.

FIG. 2A is an explanatory diagram illustrating an example of a gradation display on an LCD panel, and FIG. 2B is an explanatory diagram illustrating a processing example when displaying the gradation display example illustrated in FIG.

FIG. 3 is an explanatory diagram showing an example of storage contents of a cache memory, a frame buffer, and an image data storage unit in the present apparatus.

FIG. 4 is a block diagram illustrating a configuration example of a conventional display device.

[Explanation of symbols]

1 ... LCD panel, 2 ... Driver, 2a ...
Internal memory, 3 ... VRAM, 3a ... Image data storage unit, 3b ... Frame buffer, 4 ... CPU,
5 Controller 5a Cache memory

Claims (8)

[Claims] 1. A gradation information storage means for storing gradation information indicating a display gradation of a display dot corresponding to each display dot of a display means composed of a plurality of display dots; Regarding the first divided area, which is an area obtained by dividing the storage area of the storage means into a plurality of areas, the first divided area is determined when at least one of the pieces of gradation information stored in each first divided area is an intermediate gradation. A first presence / absence information storage means for storing first presence / absence information indicating a predetermined value of 1 in correspondence with each first divided area; and a storage area of the first presence / absence information storage means in a plurality of areas. At least one of the first presence / absence information stored in each of the second divided areas is a second divided area that is a divided area.
A second presence / absence information storage means for storing second presence / absence information indicating a second predetermined value in a case where at least one of the first predetermined values is the first predetermined value, for each of the second divided areas; First presence / absence information writing means for writing the first presence / absence information in the first presence / absence information storage means based on the gradation information stored in the tone information storage means; A second presence / absence information writing means for writing the second presence / absence information in the second presence / absence information storage means based on the first presence / absence information stored in the means; and a second presence / absence information storage means Based on the second presence / absence information stored in the first presence / absence information storage unit, at least one of the first presence / absence information stored in the second divided area constituting the first presence / absence information storage unit is the first presence / absence information. A first detecting means for detecting only a second divided area having a predetermined value of Based on the first presence / absence information stored in the second divided area detected by the detection means, at least one of the stored gradation information is selected from among the first divided areas constituting the gradation information storage means. A second detecting means for detecting only a first divided area of which one or more are intermediate gray scales; and a gray scale information which is an intermediate gray scale only from the first divided area detected by the second detecting means. Reading and outputting gradation information reading means, and storing the gradation information output by the gradation information reading means, and displaying a display dot corresponding to the gradation information based on the stored gradation information. And a driving means for driving and displaying at a display gradation indicated by the gradation information. 2. The display control device according to claim 1, wherein said gradation information storage means and said first presence / absence information storage means are provided in the same integrated circuit. 3. The first presence / absence information writing means and the second presence / absence information writing means.
At least one of the presence / absence information writing means, the first detection means, the second detection means, and the gradation information reading means.
2. The display control device according to claim 1, wherein the at least one and the second presence / absence information storage means are provided in the same integrated circuit. 4. The display means is constituted by a matrix of pixels in units of pixels constituted by a predetermined number of display dots, and the first divided area is a storage area of the gradation information storage means. , A region divided into regions corresponding to respective pixels of the matrix, and the second divided region is a region obtained by dividing a storage region of the first presence / absence information storage unit into a region corresponding to each row of the matrix. The display control device according to claim 1, wherein: 5. A display device comprising: counting means for repeatedly counting from a first predetermined number to a second predetermined number, wherein the driving means turns on the display dots corresponding to each display dot of the display means. Instruction information storage means for storing instruction information indicating which one of an instruction state and an OFF state is to be set; and blinking for setting each corresponding display dot to an ON state or an OFF state based on the instruction information stored in the instruction information storage means. Means, wherein the gradation information reading means comprises: gradation information reading means for reading only gradation information that is an intermediate gradation from the first divided area detected by the second detection means; Instruction information writing means for writing instruction information to the instruction information storage means based on the gradation information and the current number indicated by the counting means only for the gradation information read by the key information reading means; This 2. The method according to claim 1, wherein
The display control device according to the above. 6. The display control device according to claim 5, wherein said instruction information storage means and said blinking means are provided in the same integrated circuit. 7. The display control device according to claim 1, comprising: display means comprising a plurality of display dots; and gradation information writing means for writing arbitrary gradation information in said gradation information storage means. A display device, comprising: 8. The display device according to claim 7, wherein said display means is a liquid crystal display panel.