JPS63245716A - Multiwindow display device - Google Patents

Abstract

PURPOSE:To speed up multiwindow display by allowing a main processor to directly access a processor bus having wide bit width in the case of transferring the large volume of bit data from the main processor. CONSTITUTION:In the case of writing picture data in a picture memory 7 by a main processor 1, the main processor 1 directly accesses the memory 7 through a main processor bus 2, a buffer control part 8 and a subprocessor bus 5. Since the subprocessor bus 5 has 128-bit width, the writing time of picture data in the memory 7 can be shortened. In addition, read data of 8 planes from the memory 7 can be transferred to a picture control part 6 by one transfer cycle.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a multi-window display device, which stores a plurality of image data in a screen memory and makes each image data correspond to a desired coordinate position. The present invention relates to a multi-window display device that writes a plurality of image data into a frame memory and simultaneously displays the plurality of image data on a display based on the contents of the frame memory.

<Prior art> Conventionally, in graphic display devices, etc.
There is a demand for displaying a plurality of image data simultaneously on a display, and in order to satisfy such a demand, it is becoming common to provide a multi-window function.

The above multi-window function is basically controlled entirely by software, takes into consideration the overlap of multiple image data, the context, etc., obtains the composite data that should be finally displayed, and writes it to the frame memory. It is understood that it is displayed on the display based on the contents of the frame memory.

However, as the resolution of displays increases, the processing burden on software increases rapidly.
This would significantly impair the real-time performance of graphic display, so recently, calculations that correspond to the overlap and context of multiple image data are performed using dedicated hardware instead of software. The real-time nature of graphic display is ensured.

FIG. 2 is a block diagram showing a conventional example of a graphic display device having a multi-window function.
A main memory (23) is connected to a main processor bus (22) connected to the main processor bus (22).

Also, for a sub-processor bus (25) connected to a sub-processor (24) for display control, a screen control unit (26) that performs rask calculations stores multiple image data to be displayed in different areas. Screen memory (27)
, and a frame memory (28) for storing composite data to be displayed on a CRT display (30), which will be described later. Then, the main processor bus (22
) and the sub-processor bus (25), and a CRT display device (30) is connected to the frame memory (28). (29) temporarily holds data sent from the main processor (21) (information for multi-window, data, etc.),
The temporarily held data is read by the sub-processor (24). Further, the screen memory (27) has a storage capacity multiple times that of the frame memory (28) in order to store a plurality of window images, and the subprocessor bus (25) has a storage capacity that is multiple times that of the frame memory (28). 24), for example, 16
Bit width is set.

When performing multi-window display in the graphic display device with the above configuration, information, data, etc. for multi-windows sent from the main processor (21) are sent to the buffer memory (29) through the main processor bus (22). temporarily stored in .

The information, data, etc. stored in the buffer memory (29) are then read out by the sub-processor (24) through the sub-processor bus (25) and interpreted into multi-window expansion. Also, the actual figure data is stored in the screen memory (
27) and is supplied to the screen control unit (26) where bit position shifting, rask calculation, etc. are performed.
The data is stored in the frame memory (28) as data corresponding to the actual display screen. Therefore, frame memory (
CRT display device (30) based on the contents of 28)
You can display multiple windows.

When the above configuration is adopted, the circuit section for graphics display is connected to the main processor bus (22
), the load on the main processor (21) can be significantly reduced.

<Problems to be Solved by the Invention> In the image display device having the configuration described in 2 above, when transferring a large amount of bit data such as image data from the main processor (21) to the screen memory (27), Once written to the buffer memory (29), the subprocessor (29)
Since it is necessary to write to the screen memory (27) under the control of step 4), there is a problem that the overall data transfer speed becomes slow.

Also, screen memory (27) and frame memory (27)
8) are both 16-bit wide subprocessor buses (25)
Therefore, in order to perform multi-window operation, the screen memory (2
After reading the data from 7) and performing necessary processing, the data is written to the frame memory (28). That is, in order to perform one data transfer, it is necessary to use the sub-processor bus (25) twice, resulting in a problem that the overall data transfer speed becomes slow.

Furthermore, a screen memory (27) for multicolor display;
And when the frame memory (28) has multiple planes, when transferring data for each plane,
Screen memory (2) through sub-processor bus (25)
7) and reading data from the subprocessor bus (
25) to the frame memory (28), and there is a problem in that the overall data transfer speed becomes slower in proportion to the number of planes.

When performing multi-window display, the above-mentioned problems are compounded, leading to a significant decrease in data transfer speed as a whole, which impairs the real-time performance of multi-window display.

<Object of the invention> This invention was made in view of the above problems,
It is an object of the present invention to provide a multi-window display device that can achieve high-speed multi-window display by increasing the data transfer rate.

Means for Solving the Problems> To achieve the above object, the multi-window display device of the present invention includes buffer control means, transfer control means, and a sub-processor bus having a bit width that is an integral multiple of the screen memory. It has

The buffer control means is connected between the main processor bus and the sub-processor bus,
The transfer control means allows direct access to the sub-processor bus by the main processor, and the transfer control means transfers data read from the screen memory directly from the sub-processor bus to the frame memory, and also by being connected to the main processor bus. This allows the main processor to access the frame memory.

A multi-window display device with the above configuration has a main processor bus to which the main processor is connected, and a sub-processor bus to which the sub-processors and screen memory are connected. When writing multiple image data in a multi-window composite image to the frame memory and displaying the contents of the frame memory on the display, (I) Transfer a large amount of bit data such as image data from the main processor to the screen memory. In this case, the buffer control means allows the sub-processor bus with a large bit width to be directly accessed by the main processor,
High-speed data transfer is possible.

(II) After that, when instruction data is transferred from the main processor to the screen control unit, the screen control unit reads the data from the screen memory, performs bit position shifting, etc., and transfers the instruction data to the subprocessor bus. Composite figure data can be obtained by writing it into the frame memory as it is without occupying it.

In addition, when the main processor accesses the frame memory, buffer control means,
The frame memory can be directly accessed through the main processor bus and the one-screen control unit without going through the sub-processor bus and the sub-processor bus, eliminating the need for unnecessary data reading and data writing operations.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 1 is a block diagram showing an embodiment of the multi-window display device of the present invention, in which a main memory (3) is connected to a main processor bus (2) connected to a main processor (1). At the same time, a screen control section (6) and a screen memory (7) are connected to a sub-processor bus (5) connected to the sub-processor (4). A buffer control section (8) is connected between the main processor bus (2) and the sub-processor bus (5), and a frame memory (9) is connected to the screen control section (6). ing.

The screen control unit (6) is connected to the main processor (2).
) is also connected. And the above frame memory (
9) is supplied to the CRT display 00).

To explain in more detail, the buffer control unit (8) allows the main processor (1) to directly access the sub-processor bus (5), and is used for temporary data retention as seen in the conventional example. The main processor (1) can directly access the screen control unit (6) connected to the sub-processor bus (5) and the screen memory (A) without the need for writing or reading operations. It is said that

In addition, the screen control section (6) performs, for example, only barrel shift, and performs a bin shift on the image data read from the screen memory (7) through the sub-processor bus (5).・After performing position shift, etc., the frame memory (
9), it is possible to write data that has been subjected to bit position shifting, etc.

Furthermore, the screen control section (6) is also connected to the main processor bus (2), and the main processor (1) controls the frame memory ( 9) can be accessed directly.

The screen memory (7) has, for example, an 8-plane configuration for color display, and the sub-processor bus (5) has a bit width of a normal sub-processor bus (16-bit width). ), i.e. 16X8=
128 bits wide, 8 planes of screen memory (7)
The screen control unit (6
) so that it can be transferred to

The operation of the multi-window display device having the above configuration is as follows.

First, the main processor (1) connects the screen memory (7) via the main processor bus (2), the buffer control section (8), and the sub-processor bus (5).
directly access and write the necessary image data.

Next, by supplying instructions for multi-window display (for example, instructions for instructing bit position shift amount for alignment, etc.) from the main processor (1) to the screen control unit (6),
Bit = 12- in the screen control section (6) Sets the position shift amount, and in this state the screen memory (
By supplying the image data read from 7) to the screen control section (6), the image data shifted by the above set amount can be written into the frame memory (9). still,
Image data is transferred from the screen memory (7) to the frame memory (9) through the screen control unit (6) for each graphic data to be displayed in a window, and finally the frame memory (9) is transferred to the frame memory (9). , the composite data written in an overlapping manner will be stored.

A multi-window display can be performed by displaying a composite image on the CRT display (10) based on the composite data stored in the frame memory (9).

The main processor (1) also uses the frame memory (
9), direct access is made through the main processor bus (2) and screen control unit (6), and image data in the frame memory (9) is changed, added, etc.

In the following cases, the main processor (1)
13- Image data is written to the screen memory (7) through the main processor bus (2), buffer control section (8), and sub-processor bus (5) without intervening access by the sub-processor (4). , directly by the main processor (1) to the screen memory (7).
) is done by accessing
The time required to write image data to the screen memory (7) can be significantly reduced. That is, conventionally, the image data sent from the main processor (21) is once written into the buffer memory (29), and then the sub-processor (24) occupies the sub-processor bus (25) and writes the image data to the buffer memory (29). Since image data is read from the sub-processor bus (25) and then written to the screen memory (27) while occupying the sub-processor bus (25) again, the number of times image data is written and read increases and the sub-processor bus (25) is occupied again. 25), and as a result, the time required to write image data to the screen memory (27) could not be reduced much. However, by adopting the above embodiment, writing of image data, number of reads, and subprocessor bus (5
) can be occupied, and the time required to write image data to the screen memory (7) can be shortened.

In addition, each image data is read out from the screen memory (7) and transferred to the frame memory (9) with the necessary alignment processing performed.
When writing to a 128-bit wide While occupying the sub-processor bus (5), the screen control unit (6)
After reading the image data from all the planes constituting the screen memory (7) and aligning the image data in accordance with the bit position shift amount set based on the instructions from the main processor (1). , can be written directly to the frame memory (9) without occupying the sub-processor bus (5), and the screen memory (7)
The time required to align the image data stored in the frame memory (9) and write it into the frame memory (9) can be shortened. That is, conventionally, the data in the screen memory (27) is read out by the screen control unit (26) while occupying the 16-bit wide sub-processor bus (25), and after the necessary alignment processing is performed, the data is read out again in the 16-bit wide sub-processor bus (25). The frame memory (2
8), the subprocessor bus (25) must be occupied twice for one image data transfer, and the subprocessor bus (25) must be occupied twice for each plane of the screen memory (27). Since the bus must be occupied, the time required to transfer image data from the screen memory (27) to the frame memory (28) is quite long. However, in the above embodiment, it is only necessary to occupy the sub-processor bus (5) when the screen control unit (6) reads image data from the screen memory (7), and moreover, the sub-processor bus (5) is Because of the bit width, image data can be read simultaneously from all planes that make up the screen memory (7). ),
Overall, the number of times the sub-processor bus (5) is occupied can be significantly reduced, and the time required to transfer image data can be significantly shortened.

By performing the above series of operations for each image data, a plurality of image data are stored in the frame memory (9) based on the order and relative positional relationship preset in the main processor (1). The data will be stored in an overlapping manner. As a result, multi-window display can be performed by displaying the contents of the frame memory (9) as they are on the CRT display (10).

Furthermore, when the frame memory (9) is directly accessed by the main processor (1), the main processor bus (2) is accessed only through the screen control unit (6) without occupying the sub-processor bus (5). Since the frame memory (9) is accessed while the frame memory (9) is occupied, the time required for access can be shortened. That is,
Conventionally, the main processor bus (22) is occupied, data is written to and read from the buffer memory (29), the sub-processor bus (25) is occupied, and the sub-processor (24) writes data to the frame memory (28). However, in the above embodiment, the main processor bus (2) is occupied and the frame memory (9) is read.
It was only necessary to write and read data to and from the memory, thereby reducing the time required for access.

<Effects of the Invention> As described above, the present invention allows the main processor to directly access the screen memory through the sub-processor bus, and also allows the main processor to directly access the screen memory through the sub-processor bus, and after performing alignment processing on the image data read from the screen memory. , image data can be written directly to the frame memory without occupying the sub-processor bus, and data read from multiple planes that make up the screen memory can be transferred in a single transfer operation. This has the unique effect of significantly shortening the overall time required to perform multi-window display.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the multi-window display device of the present invention, and FIG. 2 is a block diagram showing a conventional example. (1) Main processor, (2) Main processor bus, (4) Sub processor, (5) Sub processor bus, (6) Screen control unit, (7 )...Screen memory, (8)...Buffer control section, (9)
...Frame memory

Claims (1)

[Claims] 1. The main processor is connected to the In-processor bus and sub-processor, and the sub to which the screen memory is connected Processor bus and screen memory Frame multiple stored image data write to frame memory, write to frame memory Display the content on the display In the multi-window display device, Main processor bus and sub-processor connected between the bus and the main Direct access of the subprocessor bus by the processor Buffer control that allows access means and the data read from screen memory. processors directly from the subprocessor bus. At the same time, the data is transferred to the main memory. By connecting to the processor bus, In-processor frame memory It has a transfer control means that allows access. However, the sub-processor bus bit The width is set to the number of screens times the screen memory. Multi-window feature Display device.