JPH07199907A - Display controller - Google Patents

Abstract

PURPOSE:To increase the speed of data write to a VRAM. CONSTITUTION:When raster operation is not performed, the non-operation mode where raster operation is not executed is detected by a decoder 127, and then, the operation of a raster operation circuit 121 is disabled, and the input on the side of a system bus interface 123 is selected by a multiplexer 125. Therefore, write data from the system bus interface 123 is directly supplied to a memory control circuit 14 without passing a bus size conversion circuit 122 neither the raster operation circuit 121. Consequently, the division processing to segment the write data by 8 bits is unnecessary to increase the speed of write of 32-bit write data from the system to a VRAM 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device,
In particular, it relates to a display control device for controlling a display monitor of a computer system such as a personal computer or a workstation.

[0002]

2. Description of the Related Art Presently, as a display control device used in a computer system such as a personal computer or a workstation, a VGA specification having a display mode such as 640.times.480 dots and 256 colors simultaneous display is mainstream. In this VGA specification display control device, a 4-plane mode having four 8-bit buses is used as a basic plane mode, and a programmable 2-plane mode,
You can switch to 1-plane mode.

This type of display control device is provided with a raster operation circuit for speeding up the drawing process. The raster operation circuit performs operation processing such as rotation, set / reset, logical operation, and bit mask according to the operation mode instructed by the system to generate drawing data in the image memory. When the raster calculation is not performed, the raster calculation circuit outputs the data from the system as it is as the drawing data to the image memory.

However, in order to perform the raster operation, the system must set the operation mode in the register of the display device, and since the performance of the CPU of the system has advanced, the raster operation circuit is used rather than the raster operation circuit. In many cases, it is often possible to generate drawing data at a higher speed by executing the calculation in the CPU. Therefore, in reality, the raster calculation is rarely used.

However, as described above, even when the raster operation is not executed, the data from the system is sent to the image memory through the raster operation circuit. In this case, there is a problem that the drawing speed in the image memory is reduced due to the delay of the raster operation circuit.

That is, the raster operation circuit provided in the display controller of the VGA specification is configured to perform operation in 8-bit units in order to generate drawing data for each plane. Therefore, the bus size of the input port on the system side of the raster operation circuit is 8 bits. Therefore, 16 bits or 32 from the system data bus
Even if bit-width data is transferred to the display control device, it is necessary to divide the data into 8-bit units when inputting the data to the raster operation circuit. As a result,
Even when the raster calculation is not executed, the same time is required as when the raster calculation is executed.

[0007]

In the display control device having the conventional raster operation circuit, the data from the system is sent to the image memory through the raster operation circuit even when the raster operation is not executed. In this case, there is a drawback that the drawing speed in the image memory is reduced due to the delay of the raster operation circuit.

The present invention has been made in view of the above circumstances. When the raster calculation is not executed, the data from the system can be directly transferred to the image memory without passing through the raster calculation circuit. It is an object of the present invention to provide a display control device capable of rapidly writing data having a large bit width in an image memory.

[0009]

Means and Actions for Solving the Problems
In a display control device for controlling a display monitor of a computer system, an image memory for storing display data displayed on the display monitor, a register for holding an operation mode instructed by the computer system, and an input of a first bit width. A raster operation circuit which has a port and which processes the data supplied to the input port according to the operation mode held in the register to generate display data to be stored in the image memory; Is connected to a data bus of the computer system having a wide second bit width, and display data of a second bit width supplied from the computer system via the data bus is divided into data of the first bit width. Bus size conversion sequentially supplied to the input port of the data operation circuit Stage, connected to the data bus of the computer system and the output of the raster operation circuit, and selects one of display data supplied from the computer system and display data output from the raster operation circuit via the data bus. Display data selecting means, means for writing the display data selected by the display data selecting means into the image memory, and whether or not the arithmetic processing by the raster arithmetic circuit is requested by the computer system according to the contents of the register. Is detected, and means for causing the display data selection means to select display data on the data bus when not requested.

This display control device is provided with display data selecting means for selecting one of display data supplied from the computer system via the data bus and display data output from the raster operation circuit. In the mode in which is not executed, the display data supplied from the computer system is selected by the display data selection means. Therefore, when the raster operation is not executed, the display data from the system can be directly transferred to the image memory without passing through the raster operation circuit, and the display data with a large bit width from the system is written into the image memory at high speed. It becomes possible.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of a display control system according to an embodiment of the present invention. This display control system 4 has, for example, 1024 × 768 dots, 25
XGA (eXtend) with display mode such as simultaneous display of 6 colors
ed Graphics Array) specification display control system, CPU local bus 3A of portable computer
Connected to. The CPU local bus 3A includes a 32-bit wide data bus. The CPU 1 and the system memory 2 are also connected to the CPU local bus 3A. Further, the CPU local bus 3A is connected to the system bus 3B including a 16-bit wide data bus via the bus conversion circuit 3C.

The display control system 4 controls the display of both the flat panel display 40, which is provided as a standard display monitor in the portable computer, and the color CRT display 50, which is optionally connected.

The display control system 4 includes a display controller 10 and a dual port image memory (V
RAM) 30 is provided. These display controller 10, dual port image memory (VRA
M) 30 is mounted on a circuit board (not shown).

The display controller 10 is an LSI realized by a gate array, and is a main part of the display control system 4. The display controller 10 uses a dual port image memory (VRAM) 30 according to an instruction from the CPU 1 and uses a flat panel display 40 and a color CRT display 5.
Display control for 0 is executed. Further, the display controller 10 functions as a bus master and can directly access the main memory 2 of the computer.

Dual port image memory (VRAM) 3
0 has a serial port (serial DATA) used for serial access and a parallel port (DATA) for random access. The serial port (serial DATA) is used to read data for refreshing the display screen, and the parallel port (DA).
TA) is used to update image data. The dual-port image memory (VRAM) 30 is composed of a plurality of dual-port DRAMs and has 1 Mbyte to 4 Mbytes.
It has a storage capacity of M bytes. The dual port image memory (VRAM) 30 is used as a frame buffer, and image data to be displayed on the flat panel display 40 or the color CRT display 50 is drawn.

In this case, drawing data of XGA specifications created by an application program or the like conforming to XGA specifications is stored in the dual port image memory (VRAM) 30 by the packed pixel method. The packed pixel method is a color information mapping format in which one pixel is represented by a plurality of consecutive bits on a memory.
A method of representing pixels by 1, 2, 4, 8 or 16 bits is adopted. On the other hand, the VGA specification drawing data is V
It is created by an application program or the like conforming to the GA specifications, and is drawn in the dual port image memory (VRAM) 30 by the memory plane method.
This memory plane method is a method in which a memory area is divided into a plurality of planes designated by the same address and color information of each pixel is assigned to these planes. For example, 4
In plane mode, one pixel is one per plane
It is represented by a total of 4 bits of data, bit by bit. In this case, byte access is performed for each plane. Further, the plane mode can be switched programmatically from the above-mentioned four-plane mode to the two-plane mode and the one-plane mode.

Text data is also stored in the VRAM 30. Text data for one character is XGA,
Both VGA specifications have a total size of 2 bytes consisting of an 8-bit code and an 8-bit attribute. The attribute is composed of 4-bit data that specifies the foreground color and 4-bit data that specifies the background color.

The display controller 10 includes a system interface 12, a drawing coprocessor 13, a memory control circuit 14, and a CRT controller (CRTC) 1.
6, serial port control circuit 18, sprite memory 1
9, serializer 20, latch circuit 21, foreground / background multiplexer 22, graphic / text multiplexer 23, color palette control circuit 24, sprite color register 25, CRT video multiplexer 26, sprite control circuit 27, flat panel emulation circuit 28, And DAC (D
/ A converter) 35.

The system interface 12 is a CPU
It controls the interface with the CPU 1 via the local bus 3A, and a raster operation circuit (ROP).
121 and a bus size conversion circuit 122 are included.

The raster operation circuit (ROP) 121 performs operation processing such as rotation, set / reset, logical operation, and bit mask according to the operation mode instructed by the system to generate drawing data to the VRAM 30. In this case, the raster operation process is performed between the image data of the predetermined coordinates (raster) read from the VRAM 30 and the write data from the system, for example, and the image data created by this is rewritten in the VRAM 30. .
When the raster calculation is not performed, the raster calculation circuit 30 receives the data from the system as it is in the VRAM 30.
Output as drawing data to.

This raster operation circuit (ROP) 121 is V
It is of the GA specification, and is configured to perform operations in 8-bit units in order to generate drawing data for each plane.

The bus size conversion circuit 122 is for adapting the write data from the system to the number of bits of the raster operation circuit (ROP) 121, and the 32-bit data received from the CPU local bus 3A in 8-bit units. Then, the data is cut out and sequentially output to the raster operation circuit (ROP) 121.

In the system interface 10, when performing a raster operation, write data from the system is sent to the memory control circuit 14 via the bus size conversion circuit 122 and the raster operation circuit (ROP) 121. When the raster operation is not performed, the write data from the system is directly sent to the memory control circuit 14 without passing through the bus size conversion circuit 122 and the raster operation circuit (ROP) 121.

The structure of the system interface 12 is a feature of the present invention, and its details will be described later in the description of FIG.

The drawing coprocessor 13 is a graphic accelerator, and in response to an instruction from the CPU 1,
Various drawing functions are provided for drawing data in the VRAM 30. This drawing coprocessor 13 is a BIT
It has block transfer of pixels such as BILT, line drawing, area filling, logical / arithmetic operations between pixels, screen cutout, map mask, XY addressing, and memory management function by paging. . The drawing coprocessor 13 is provided with a VGA / XGA compatible data operation circuit 131, a two-dimensional address generation circuit 131, and a paging unit 133.

The data operation circuit 131 performs data operations such as shifts, logical arithmetic operations, bit masks and color comparisons, and also has a VGA compatible BITBLT function. The two-dimensional address generation circuit 131 generates an XY two-dimensional address for accessing a rectangular area or the like. The two-dimensional address generation circuit 131 also performs a region check and a conversion process to a linear address (real memory address) using segmentation or the like. The paging unit 133 is for supporting the same virtual memory mechanism as the CPU 1, and converts the linear address created by the two-dimensional address generation circuit 131 into a real address by paging when paging is valid. Further, when paging is invalid, the linear address becomes the real address as it is. The paging unit 133 has a TLB for paging.

The memory control circuit 14 is for controlling access to the VRAM 30, and controls access to the parallel port of the VRAM 30 according to a read / write request of image data from the CPU 1 or the drawing coprocessor 13 and also controls from the CRTC 16. Data read control from the serial port of the VRAM 30 is performed according to the display position address.

Further, the memory control circuit 14 has a frame buffer cache 141 built therein. The frame buffer cache 141 is used for speeding up read / write of image data by the CPU 1 and the drawing coprocessor 13, and is a VRAM.
A part of 30 image data is held. When the image data requested to be read by the CPU 1 or the drawing coprocessor 13 exists in the frame buffer cache 141, the image data is read from the frame buffer cache 141 and transferred to the CPU 1 or the drawing coprocessor 13. In this case, read access via the parallel port of the VRAM 30 is not performed.

The CRTC 16 has various display timing signals (horizontal sync signal, vertical sync signal, etc.) for displaying a screen on the flat panel display 40 or the CRT display 50 at a high resolution (for example, 1024 × 768 dots) that conforms to the XGA specifications. ) And various display timing signals (horizontal sync signal, vertical sync signal, etc.) for displaying the screen on the flat panel display 40 or the CRT display 50 at a medium resolution (for example, 640 × 460 dots) that meets VGA specifications. Occurring in a sudden way. The CRTC 16 also generates a display address for reading image data to be displayed on the screen from the serial port (serial DATA) of the VRAM 30, and the memory control circuit 14
Supply to.

Serial port control circuit 18, sprite memory 19, serializer 20, latch circuit 21, foreground / background multiplexer 22, graphic / text multiplexer 23, color palette control circuit 24, sprite color register 25, CR
T video multiplexer 26, sprite control circuit 2
7. The flat panel emulation circuit 28 and the DAC (D / A converter) 35 convert the image data of the VRAM 30 into the flat panel display 40 or CR.
A display circuit for displaying on the T display 50 is configured.

The serial port control circuit 18 is a VRAM.
A serial clock SCK and a serial output enable signal SOE for controlling the data read timing from the 30 serial data ports are generated. The memory control circuit 18 also controls access to the sprite memory 19 and sprite display timing control.

Sprite data is written to the sprite memory 19 in the graphic mode, and fonts are written in the text mode. In text mode, VRAM3
The code of the text data read from 0 is supplied to the sprite memory 19 as an index, and the font corresponding to the code is read.

The serializer 20 is a parallel / serial conversion circuit for converting parallel pixel data for a plurality of pixels into pixel units (serial). In the graphic mode, the serializer 20 reads the memory data read from the serial port of the VRAM 30 and the sprite memory 19. The sprite data to be converted is parallel / serial converted, and in the text mode, the font data read from the sprite memory 19 is parallel / serial converted.

The latch circuit 21 is for delaying the attribute output timing by the delay time of conversion from code data to font data, and holds the attribute of text data read from the VRAM 30 in the text mode. Foreground /
The background multiplexer 22 is the foreground color (front color) of the attribute in the text mode.
/ Select one of the background colors (background color). This selection is controlled by the values "1" (foreground) and "0" (background) of the font data output from the serializer 20. The graphic / text multiplexer 23 is for switching between the graphic mode and the text mode. In the graphic mode, the memory data output from the serializer 20 is selected, and in the text mode, the foreground / background multiplexer 22 is selected. Select an output.

The color palette control circuit 24 is for performing color conversion of graphic or text data. The color palette control circuit 24 includes a two-stage color palette table. The first color palette table is composed of 16 color palette registers. Each color palette register contains
6-bit color palette data is stored. The second color palette table is composed of 256 color palette registers. Each color palette register stores 18-bit color data composed of 6 bits for each of R, G, and B.

In the graphic mode, 8-bit / pixel XGA specification memory data is sent directly to the second color palette table without passing through the first color palette table, where R, G and B are each 6 Converted to color data composed of bits. Also,
The 4-bit / pixel VGA memory data is first sent to the first color palette table, where it is converted into 6-bit color data and output. And
To this 6-bit color data, 2-bit data output from the color selection register built in the color palette control circuit 19 is added, whereby a total of 8-bit color data is obtained. After that, the 8-bit color data is sent to the second color palette table, where it is converted into color data of 6 bits for each of R, G, and B.

On the other hand, in the text mode, XG
Text data of both A and VGA can be read via R, R, and R via the first and second two-stage color palette tables.
It is converted into color data composed of 6 bits for each of G and B.

In the XGA graphics mode, there is a direct color mode in which one pixel is composed of 16 bits. In this case, the memory data of 16 bits / pixel does not go through the color palette control circuit 24. Are directly supplied to the CRT video multiplexer 26.

The sprite color register 25 specifies the sprite display color. CRT video multiplexer 2
Reference numeral 6 selects a CRT video display output, and selects the output of the color palette control circuit 24 or the direct color output from the serializer 20, and further performs the video switching of sprite display. The sprite control circuit 27 controls the CRT video multiplexer 26 in accordance with the sprite data converted from parallel / serial by the serializer 20, and controls video switching during sprite display. Flat panel emulation circuit 28 converts the CRT video output to produce flat video data for flat panel display 40.

The DAC 35 converts the CRT video data output from the CRT video multiplexer 26 into analog R, G, B signals and supplies them to the CRT display 50.

In FIG. 2, the system interface 12 is shown.
An example of a concrete circuit configuration of is shown.

As shown in the figure, the system interface 12 is provided with a system bus interface 123, a parameter register group 124, a multiplexer 125, and a FIFO buffer 126 in addition to the raster operation circuit 121 and the bus size conversion circuit 122 described above. .

The system bus interface 123 is
It is connected to the CPU local bus 3A and exchanges data with the system in 32-bit units. The 32-bit write data from the system is supplied to the bus size conversion circuit 122 and the first input of the multiplexer 125.

As described above, the bus size conversion circuit 122 cuts out 32-bit data from the system into 8-bit units and sequentially supplies the data to the first input port of the raster operation circuit 121. If the data from the system is a calculation parameter such as a calculation mode, it is set in the register group 124. In this register group 124,
The pre-change mode specification parameter from the system is also set.

The raster operation circuit 121 has an 8-bit wide first input port connected to the output of the bus size conversion circuit 122 and a 32-bit wide second input port for receiving read data from the VRPM 30, and 32. Has a bit width operation result output port. The 32-bit data output from the operation result output port is the multiplexer 1
25 second input. This raster operation circuit 12
The operation by 1 is designated by the operation mode set in the register group 124. FIG. 3 shows an example of a specific circuit configuration of the raster operation circuit 121.

As shown in FIG. 3, the raster operation circuit 121 includes four 8-bit operation circuits 201 respectively corresponding to planes 0 to 3 and an 8-bit shift circuit 20.
2 and a 32-bit latch circuit 203. 8 bits for each plane of VRAM30, total 3
The 2-bit read data is latched by the latch circuit 203 and sent to the four arithmetic circuits 201 by 8 bits each. On the other hand, write data from the system is sequentially output from the bus size conversion circuit 22 in the order of planes 0 to 3, and sequentially supplied to the four arithmetic circuits 201 via the shift circuit 202. Each of the four arithmetic circuits 201 performs 8-bit arithmetic between the read data and the write data in order to generate the drawing data of the corresponding plane. The results of these 8-bit operations are written back to the corresponding plane. In this way, the raster calculation circuit 121 is configured to perform calculation in 8-bit units in order to generate drawing data for each plane.

The multiplexer 125 of FIG. 2 includes the data from the system bus interface 123 supplied to the first input and the raster operation circuit 121 supplied to the second input.
Select one of the data from. In this case, the multiplexer 125 selects the output of the raster operation circuit 121 when performing the raster operation, and selects the output from the system bus interface 123 when not performing the raster operation. This selection operation is controlled by the decoder 127. The decoder 127 decodes the operation mode set in the register group 124 and generates a detection signal when detecting that the raster operation is not performed.

The FIFO buffer 126 is provided for synchronization between the system interface 12 and the memory control circuit 14, receives write data in synchronization with the clock CLK1 of the system interface 12, and controls the memory. The write data is output to the 32-bit internal bus in synchronization with the clock CLK2 of the circuit 14.

In the system interface 12 thus constructed, the write data transfer path differs depending on whether the raster operation is performed or not. When performing the raster operation, the system bus interface 12 is used.
The 32-bit write data received by 3 is sent to the memory control circuit 14 via the bus size conversion circuit 122, the raster operation circuit 121, the multiplexer 125, and the FIFO buffer 126. In this case, the bus size conversion circuit 122 divides the 32-bit write data into four and sends them to the raster operation circuit 121 in 8-bit units. In the raster operation circuit 121, the register group 124
The calculation process according to the calculation mode set to
An 8-bit operation between the write data and the read data from the VRAM 30 is executed in the same plane to generate drawing data for each plane, and write data for 4 planes (32 bits = 8 bits × 4 planes) Is generated.

On the other hand, when the raster operation is not performed, the decoder 127 detects that the raster operation is not executed and the operation of the raster operation circuit 121 is disabled, and the multiplexer 125 is used. The input on the system bus interface 123 side is selected. For this reason,
The write data from the system bus interface 123 is directly supplied to the memory control circuit 14 without passing through the bus size conversion circuit 122 and the raster operation circuit 121. Therefore, since it is unnecessary to divide the write data into 8-bit units, data can be written at high speed.

When the raster operation is not performed, the data transfer bus width to the VRAM 30 is controlled according to the plane mode so that the VRAM 30 can be word-accessed in 16-bit units or double-word access in 32-bit units. It becomes possible to carry out.

FIG. 4 shows the relationship between the plane mode and the data transfer size.

As described above, the VGA VRAM plane mode includes three modes of 1 plane / 2 plane / 4 plane. In the 4-plane mode, an 8-bit wide data bus is assigned to each plane and byte access is performed for each plane. In this case, the image data is written in the VRAM 30 in a plane format of 4 bits / pixel (one pixel is represented by 4 bits of data, 1 bit for each plane). Similarly, in the 2-plane mode, a 16-bit wide data bus is assigned to each plane and word access is performed for each plane.
In this case, the image data can be written in the VRAM 30 in a 2-bit / pixel plane format or the like. In the 1-plane mode, a 32-bit wide data bus is assigned to the 1-plane and double word access is performed.
In this case, the image data for 4 pixels having the packed pixel format of 8 bits / pixel can be written in the VRAM 30 at one time. These plane modes are controlled by V
This can be performed by the memory control circuit 14 by using the control signal to the RAM 30.

The 32-bit write data is transferred to the VRAM 30.
When writing to, via the raster operation circuit 121,
Byte write is required four times in any plane mode of 1 plane / 2 plane / 4 planes. On the other hand, when the raster operation circuit 121 is not used,
By controlling the data transfer bus width to the VRAM 30 in the plane mode, 32-bit write data can be written in the VRAM 30 by two word writes in the two-plane mode and one double word write in the one-plane mode.
It becomes possible to write in.

The data transfer bus width is controlled by, for example, adjusting the data transfer width on the internal bus (32 bits / plane according to the plane mode (1 plane / 2 plane / 4 plane) set in the register group 124). 16 bits / 8
By providing a bus size conversion circuit that dynamically changes the bit size) in the system bus interface 123, for example, at the output stage of the multiplexer 125 or the FIFO 126, data can be divided and transferred according to the plane mode. . Further, it may be provided in the memory control circuit 14.

[0057]

As described above, according to the present invention, when the raster operation is not executed, the data from the system can be directly transferred to the image memory without passing through the raster operation circuit. It becomes possible to write data having a large bit width into the image memory at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a display control device according to an embodiment of the present invention.

2 is a diagram showing an example of a specific circuit configuration of a system interface provided in the display control device of FIG.

3 is a diagram showing an example of a specific circuit configuration of a raster calculation circuit provided in the system interface of FIG.

4 is a diagram showing a relationship between a plane mode and a data transfer size in the display control device of FIG.

[Explanation of symbols]

3A ... CPU local bus, 4 ... Display control system, 1
0 ... Display controller, 12 ... System interface, 14 ... Memory control circuit, 30 ... VRAM,
121 ... Raster arithmetic circuit, 122 ... Bus size conversion circuit, 123 ... System bus interface, 124 ...
Register group, 125 ... Multiplexer, 126 ... FIF
O buffer.

Claims (2)

[Claims] 1. A display control device for controlling a display monitor of a computer system, an image memory for storing display data displayed on the display monitor, a register for holding an operation mode instructed by the computer system, A raster operation circuit which has an input port having a plurality of 1-bit widths and which processes the data supplied to the input port according to the operation mode held in the register to generate display data to be stored in the image memory; A second multi-bit width display connected to a data bus of the computer system having a second multi-bit width wider than the first multi-bit width and supplied from the computer system via the data bus The data is divided into the first multi-bit width data and the data Bus size conversion means for sequentially supplying to an input port of the circuit, display data supplied from the computer system via the data bus of the computer system and an output of the raster operation circuit, and the raster operation Display data selecting means for selecting one of the display data output from the circuit, means for writing the display data selected by the display data selecting means into the image memory, and arithmetic processing by the raster arithmetic circuit according to the contents of the register. Is detected by the computer system, and means for causing the display data selecting means to select the display data on the data bus when not requested by the computer system. 2. A display control device for controlling a display monitor of a computer system, having a plurality of plane modes in which writable data sizes are different from each other by one access, and displaying display data to be displayed on the display monitor. An image memory for storing, a first register for holding an operation mode instructed by the computer system, a second register for holding a plane mode instructed by the computer system, and a first multi-bit width input port. A raster operation circuit that has an operation processing of data supplied to the input port according to an operation mode held in the register to generate display data to be stored in the image memory; and the first plurality of bits. The computer system having a second multiple bit width wider than the width Connected to the data bus of the data system, and the display data of the second multi-bit width supplied from the computer system via the data bus is divided into the data of the first multi-bit width and input to the data operation circuit. Bus size conversion means for sequentially supplying to the ports, display data supplied from the computer system via the data bus of the computer system and the output of the raster operation circuit, and output from the raster operation circuit Display data selecting means for selecting one of the display data to be displayed, and whether or not the arithmetic processing by the raster arithmetic circuit is requested by the computer system according to the contents of the first register. Causes display data selection means to select display data on the data bus And a data transfer bus for transferring the display data to the image memory according to the plane mode held in the second register when the display data on the data bus is selected by the display data selecting means. And a means for changing the width.