JPH06332791A - Image memory and display control system using image memory - Google Patents

Abstract

PURPOSE:To embody an image memory which is capable of automatically inserting a split transfer cycle without the control from an external circuit. CONSTITUTION:When a shift register to be a reading object from a serial port is switched from one side to the other side of a left side shift register 307 and a right side shift register 308, a split transfer operation is started by a split transfer trigger circuit 317. In this split transfer, a low address for split transfer generated by a split transfer address generation counter 315 is delivered to a low decoder 304 and one line of the memory array 301 designated by the low address for split transfer is selected. The data which is the half of the selected one line is split transferred to one side shift register. Therefore, a split transfer cycle can be performed within a VRAM without the control from the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory and a display control system using the image memory, and more particularly to an image memory used as a frame buffer memory of a computer display monitor and a display monitor using the image memory. The present invention relates to a display control system for controlling a display.

[0002]

2. Description of the Related Art Conventionally, as a display control system used in a computer such as a personal computer or a workstation, a display control system having a medium resolution of about 640 × 480 dots has been mainly used. Recently, sophisticated graphical user interfaces are needed, for example 1024
High resolution display such as x768 dots or 1280x1024 dots has been required.

In such a display control system for displaying high resolution graphics, a dual port VRAM is often used as a frame buffer memory for holding image data such as characters and figures.

This dual port VRAM has a random access port and a serial access port that can access the memory independently of each other. The random access port is a port for randomly accessing the memory cell array of the dual port VRAM and is used for updating image data. The serial access port is for serially outputting one row of image data transferred from the memory cell array to the shift register,
It is used to read image data for screen refresh.

The VRAM having such a configuration is suitable for high resolution graphics display because it can avoid the problem of conflict between the screen refreshing process and the image data updating process.

However, when the VRAM is used, it is necessary to control the insertion timing of the data transfer cycle from the memory cell array to the shift register by an external circuit.

That is, when high resolution display of 1024 dots or more is performed, a plurality of VRAMs are used to realize a large capacity frame buffer memory. In this case, each VRA depends on the configuration of the frame back memory.
The number of pixels that can be supported by one row of image data in the M memory cell array is usually smaller than the number of pixels in one horizontal display line of the display screen. Therefore, it is necessary to insert a data transfer cycle during the display period and transfer the next row of data to the shift register.

In this case, the control of the insertion timing of the data transfer cycle is performed by an external circuit, but since it is necessary to insert the data transfer cycle at the moment when all the data is read from the shift register, the timing control for that is required. Is very complicated.

Therefore, recently, a VRAM having a split transfer function has been developed in order to ease the timing control of the data transfer cycle. This split transfer function uses a shift register divided into two to transfer data from the memory cell array to the shift register in units of half of one line. By using this split transfer function, data can be transferred to the other shift register while the data in one shift register is being read from the serial port. Therefore, the data transfer cycle can be inserted relatively easily even during the display period.

However, even when a VRAM having a split transfer function is used, the fact that the start timing of the split transfer must be controlled by an external circuit is the same, and the VRAM by the external circuit is the same.
The control burden is still heavy.

In particular, recently, a display control system has been required to be integrated into one chip for the purpose of cost reduction and high performance of a computer, but in the case of this one chip, simplification of VRAM control by the display control system is required. Will be needed.

[0012]

In the conventional VRAM,
The timing for inserting the data transfer cycle must be generated by an external circuit, and there is a drawback that complicated timing control is required especially when the data transfer cycle is inserted during the display period.

The present invention has been made in view of the above circumstances, and provides an image memory in which a data transfer cycle can be automatically inserted during a display period without control from an external circuit, and the image memory. VRA by the display control system so that the display control system used can be realized
The purpose is to simplify the M timing control.

[0014]

Means and Actions for Solving the Problems
In a dual-port image memory having a random access port and a serial access port, a memory cell array composed of a plurality of memory cells arranged in a matrix of rows and columns and half data of one row of the memory cell array are held respectively. The first and second data buffers, and serial reading means for selectively selecting the data buffers and serially reading the data held in the selected data buffers to the serial access port; Split transfer address generating means for generating a row address for split transfer for designating one row of the memory cell array in which data following the data held in the data buffer is stored, and the row address for split transfer. It is specified Selecting one row of the memory cell array and detecting switching of the data buffer selected by the serial transfer means and split transfer means for transferring half the data of the selected row to the non-selected data buffer; It is characterized in that a split transfer starting means for executing data transfer by the split transfer means in response to the detection is provided on one chip.

In this image memory, when the data buffer selected by the serial reading means is switched from one to the other, the split transfer starting means starts the split transfer operation.

In this split transfer, the row address for split transfer generated by the split transfer address generating means is used. Then, one row of the memory cell array designated by the split transfer row address is selected, and half the data of the selected one row is split-transferred to the data buffer in which the data is not read. Therefore, during the display period in which the data is read from the serial access port, the split transfer cycle can be automatically inserted without control from the external circuit.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of a display control system according to an embodiment of the present invention. This display control system 4 is, for example, 1024 × 768 dots, 256
XGA (eXtended G) that has a display mode of simultaneous color display
It is a display control system of the raphics Array) specification and is connected to the system bus 3 of the portable computer.
The display control system 4 includes a flat panel display 40 that is provided as standard equipment in a portable computer body and a color CRT display 5 that is optionally connected.
Display control for both 0 is performed.

The display control system 4 includes a display controller 10 and a dual port image memory (V
RAM) 30 is provided. These display controller 10, dual port image memory (VRA
M) 30 is mounted on a circuit board (not shown).

The display controller 10 is an LSI realized by a gate array and is a main part of the display control system 4. The display controller 10 executes display control for the flat panel display 40 and the color CRT display 50 using a dual port image memory (VRAM) 30 according to an instruction from the host CPU 1. Further, the display controller 10 functions as a bus master and can directly access the main memory 2 of the computer.

Dual port image memory (VRAM) 3
0 is the flat panel display 40 or color C
It is used as a frame buffer for storing image data to be displayed on the RT display 50,
A serial access port (serial DATA) used for serial access and a random access port (DATA) for random access are provided. The serial access port (serial DATA) is used for reading data for refreshing the display screen, and the parallel access port (DATA) is used for updating image data.

Further, the VRAM 30 has two operation modes for data transfer, that is, a normal transfer mode and a split transfer mode. The normal transfer mode is a mode in which data for one row of one memory cell array (for example, 512 × 8 bits) is collectively transferred to the shift register in one cycle. Split transfer mode is
This is a mode in which the shift register is divided into two and half the data for one row (for example, 256 × 8 bits) is transferred to one of the two divided shift registers in one cycle. A logic for automatically inserting a split transfer cycle is incorporated in the VRAM 30 and the split transfer is automatically executed as necessary. When the split transfer cycle is automatically inserted, the VRAM 30 outputs a wait signal to the memory control circuit 14 to make it wait for execution of another operation cycle.

VRAM 30 having logic for automatically inserting split transfer cycle is a characteristic part of the present invention, and its configuration will be described later with reference to FIG. XG
The XGA specification drawing data created by an application program or the like conforming to the A specification is stored in the VRAM 30 by the packed pixel method. This packed pixel system is a color information mapping format in which one pixel is represented by a plurality of consecutive bits on a memory, and for example, a system in which one pixel is represented by 1, 2, 4, 8 or 16 bits is adopted. . On the other hand, VGA specification drawing data is VGA
It is created by an application program that conforms to the specifications, and VRAM is created by the memory plane method.
30 is drawn. This memory plane method is a method in which a memory area is divided into a plurality of planes designated by the same address and color information of each pixel is assigned to these planes. For example, when there are four planes, one pixel is represented by a total of 4 bits of data, one bit for each plane.

Text data is also stored in the VRAM 30. Text data for one character is XGA,
Both VGA specifications have a total size of 2 bytes consisting of an 8-bit code and an 8-bit attribute. The attribute is composed of 4-bit data that specifies the foreground color and 4-bit data that specifies the background color.

The display controller 10 includes a register control circuit 11 and a system bus interface 1.
2, a drawing coprocessor 13, a memory control circuit 14,
CRT controller (CRTC) 16, serial port control circuit 18, sprite memory 19, serializer 2
0, latch circuit 21, foreground / background multiplexer 22, graphic / text multiplexer 23, color palette control circuit 24, sprite color register 25, CRT video multiplexer 2
6, sprite control circuit 27, flat panel emulation circuit 28, and DAC (D / A converter)
It is composed of 35.

The register control circuit 11 receives an address and data from the system bus 3 via the system bus interface 12, decodes the address, and performs read / write control on various registers designated by the decoding result. The system bus interface 12 controls the interface with the host CPU 1 via the system bus 3, and supports a bus interface conforming to various specifications such as ISA, EISA, micro channel, and local bus.

The drawing coprocessor 13 is a graphic accelerator, and responds to an instruction from the CPU 1 in response to a V
Various drawing functions are provided for drawing data in the RAM 30. This drawing coprocessor 13 is
It has pixel block transfer such as ILT, line drawing, area filling, logical / arithmetic operation between pixels, screen cutout, map mask, XY addressing, and paging memory management function. . The drawing coprocessor 13 is provided with a VGA / XGA compatible data operation circuit 131, a two-dimensional address generation circuit 131, and a paging unit 133.

The data operation circuit 131 performs data operations such as shifts, logical arithmetic operations, bit masks and color comparisons, and also has a VGA compatible BITBLT function. The two-dimensional address generation circuit 131 generates an XY two-dimensional address for accessing a rectangular area or the like. The two-dimensional address generation circuit 131 also performs a region check and a conversion process to a linear address (real memory address) using segmentation or the like. The paging unit 133 is for supporting the same virtual memory mechanism as the CPU 1, and converts the linear address created by the two-dimensional address generation circuit 131 into a real address by paging when paging is valid. Further, when paging is invalid, the linear address becomes the real address as it is. The paging unit 133 has a TLB for paging.

The memory control circuit 14 is for controlling access to the VRAM 30. The memory control circuit 14 controls access to the parallel port of the VRAM 30 in accordance with a read / write request of image data from the CPU 1 or the drawing coprocessor 13, and also controls the access from the CRTC 16. Data read control from the serial port of the VRAM 30 is performed according to the display position address. Also, the period during which the wait signal is generated from the VRAM 30 (split transfer execution period)
, The memory control circuit 14 does not execute the access operation to the VRAM 30 until the generation of the wait signal is stopped.

Further, the memory control circuit 14 has a frame buffer cache 141 built therein. The frame buffer cache 141 is used for speeding up read / write of image data by the CPU 1 and the drawing coprocessor 13, and is a VRAM.
A part of 30 image data is held. When the image data requested to be read by the CPU 1 or the drawing coprocessor 13 exists in the frame buffer cache 141, the image data is read from the frame buffer cache 141 and transferred to the CPU 1 or the drawing coprocessor 13. In this case, read access via the parallel port of the VRAM 30 is not performed.

The CRT controller 16 has various display timing signals (horizontal synchronization signal, vertical synchronization signal) for displaying a screen on the flat panel display 40 or the CRT display 50 at a high resolution (for example, 1024 × 768 dots) that conforms to the XGA specifications. Signals) and various display timing signals (horizontal synchronization signal, vertical synchronization signal, etc.) for displaying the screen on the flat panel display 40 or the CRT display 50 at a medium resolution (for example, 640 × 460 dots) that meets VGA specifications. Occurs selectively. In addition, the CRT controller 15 has the VRAM 3
A display address for reading the image data to be displayed on the screen is generated from the serial port 0 (serial DATA) and is supplied to the memory control circuit 14.

The serial port control circuit 18 is a VRAM.
A clock SCK for controlling the data read timing from the serial port 30 and an output enable signal SOE are generated. The memory control circuit 18 also controls access to the sprite memory 19 and sprite display timing control.

Sprite memory 19, serializer 2
0, latch circuit 21, foreground / background multiplexer 22, graphic / text multiplexer 23, color palette control circuit 24, sprite color register 25, CRT video multiplexer 2
6, sprite control circuit 27, flat panel emulation circuit 28, and DAC (D / A converter)
Reference numeral 35 constitutes a display circuit for displaying the image data of the VRAM 30 on the flat panel display 40 or the CRT display 50.

Sprite data is written to the sprite memory 19 in the graphic mode, and fonts are written in the text mode. In the text mode, the code of the text data read from the dual port image memory (VRAM) 30 is supplied to the sprite memory 19 as an index, and the font corresponding to the code is read.

The serializer 20 is a parallel / serial conversion circuit for converting parallel pixel data for a plurality of pixels into pixel units (serial). In the graphic mode, the serializer 20 reads the memory data read from the serial port of the VRAM 30 and the sprite memory 19. The sprite data to be converted is parallel / serial converted, and in the text mode, the font data read from the sprite memory 19 is parallel / serial converted.

The latch circuit 21 is for delaying the attribute output timing by the delay time of conversion from code data to font data, and holds the attribute of text data read from the VRAM 30 in the text mode. Foreground /
The background multiplexer 22 is the foreground color (front color) of the attribute in the text mode.
/ Select one of the background colors (background color). This selection is controlled by the values "1" (foreground) and "0" (background) of the font data output from the serializer 20. The graphic / text multiplexer 23 is for switching between the graphic mode and the text mode. In the graphic mode, the memory data output from the serializer 20 is selected, and in the text mode, the foreground / background multiplexer 22 is selected. Select an output.

The color palette control circuit 24 is for performing color conversion of graphic or text data. The color palette control circuit 24 includes a two-stage color palette table. The first color palette table is composed of 16 color palette registers. Each color palette register contains
6-bit color palette data is stored. The second color palette table is composed of 256 color palette registers. Each color palette register stores 18-bit color data composed of 6 bits for each of R, G, and B.

In the graphic mode, 8-bit / pixel XGA specification memory data is sent directly to the second color palette table without passing through the first color palette table, where R, G and B are each 6 Converted to color data composed of bits. Also,
The 4-bit / pixel VGA memory data is first sent to the first color palette table, where it is converted into 6-bit color data and output. And
To this 6-bit color data, 2-bit data output from the color selection register built in the color palette control circuit 19 is added, whereby a total of 8-bit color data is obtained. After that, the 8-bit color data is sent to the second color palette table, where it is converted into color data of 6 bits for each of R, G, and B.

On the other hand, in the text mode, XG
Text data of both A and VGA can be read via R, R, and R via the first and second two-stage color palette tables.
It is converted into color data composed of 6 bits for each of G and B.

In the XGA graphics mode, there is a direct color mode in which one pixel is composed of 16 bits. In this case, the memory data of 16 bits / pixel does not go through the color palette control circuit 24. Are directly supplied to the CRT video multiplexer 26.

The sprite color register 25 specifies the sprite display color. CRT video multiplexer 2
Reference numeral 6 selects a CRT video display output, and selects the output of the color palette control circuit 24 or the direct color output from the serializer 20, and further performs the video switching of sprite display. The sprite control circuit 27 controls the CRT video multiplexer 26 in accordance with the sprite data converted from parallel / serial by the serializer 20, and controls video switching during sprite display. Flat panel emulation circuit 28 converts the CRT video output to produce flat video data for flat panel display 40.

The DAC 35 converts the CRT video data output from the CRT video multiplexer 26 into analog R, G, B signals and supplies them to the CRT display 50.

FIG. 2 shows an example of a concrete configuration of the VRAM 30. The VRAM 30 is a dual port VRAM having a 256K × 8 bit structure, and includes a memory cell array 301, a column decoder 302, and a sense amplifier 3.
03, row decoder 304, left transfer gate 305, right transfer gate 306, left shift register 307, right shift register 308, shift register selector 30
9, serial port output buffer 310, column address MSB register 311, serial address counter 3
12, a decoder 313, a row address register 314,
A split transfer row address (ST-RA) generation counter 315, a row address selector 316, a split transfer trigger circuit 317, a split transfer timing control circuit 318, and a timing generation circuit 319 are provided.

The memory cell array 301 is a 512 × 512 × 8-bit cell array which is composed of a plurality of memory cells arranged in a matrix of rows and columns.
The column decoder 302 decodes a 9-bit column address, and outputs 512 × 8 according to the decoding result.
1 × 8 of the bit lines are selected.

The sense amplifier 303 amplifies the data read on the selected bit line and outputs it to the random access port (DATA). The amplification function of the sense amplifier 303 is also used for memory refresh.

The row decoder 304 has one row of the memory cell array 301, that is, 51 rows according to the 9-bit row address input from the row address selector 316.
Select 1 × 8 of 2 × 8 word lines.

The memory cell array 301, the column decoder 302, the sense amplifier 303, and the row decoder 304 form a RAM section in the VRAM 30. The left transfer gate 305 transfers the left half data (256 × 8 bits) of one row of the memory cell array 301 to the left shift register 307. The right-side transfer gate 306 is used for the right half data (256) of one row of the memory cell array 301.
X8 bits) is transferred to the right shift register 308.

The left shift register 307 is a 256 × 8-bit data register, and outputs 1 × 8-bit data stored in the position selected by the output of the decoder 313 to the selector 309 as left-side transfer data. The right shift register 308 is a data register having a 256 × 8 bit structure, and outputs the 1 × 8 bit data stored in the position selected by the output of the decoder 313 to the selector 309 as the right transfer data.

The selector 309 selects one of the left transfer data and the right transfer data and outputs it to the serial port output buffer 310. Which of the left-side transfer data and the right-side transfer data is selected is determined by the output QSF of the register 311 which holds the most significant bit MSB of the counter output of the serial address counter 312.

That is, when QSF = “0” (serial address MSB = “0”), the left transfer data is selected and QSF = “1” (serial address MSB =
In the case of "1"), the right transfer data is selected.

The serial port output buffer 310 is for outputting the data from the selector 309 to the serial access port (serial DATA), and is activated by the serial output enable signal SOE. The serial address counter 312 is initially set with a 9-bit column address indicating the start address value of the serial read cycle. The serial address counter 312 sequentially counts up the set address value by +1 in synchronization with the serial clock SC, and outputs the count value as a 9-bit serial address.

The most significant bit MSB of this 9-bit serial address is supplied to the register 311, and the remaining lower 8 bits are supplied to the decoder 313. Decoder 3
13 decodes the lower 8 bits of the serial address and outputs the decoding result output to the shift registers 307, 3
Send to 08.

These left transfer gate 305, right transfer gate 306, left shift register 307, right shift register 308, shift register selector 309, serial port output buffer 310, column address MSB register 311, serial address counter 312, and decoder 313 are arranged as follows. , Configure serial access memory.

Row address register 314 holds a 9-bit row address and outputs it to row address selector 316 and split transfer row address (ST-RA) generation counter 315.

Split transfer row address (ST-R
A) The generation counter 315 is a counter for generating a split transfer row address (ST-RA), and outputs the row address (row address for the normal transfer mode) from the row address register 314 in synchronization with the clock CK. The value is incremented by +1. This count output is the split transfer row address (ST-RA).
Are supplied to the row address selector 316.

The row address selector 316 receives the row address (RA) from the row address register 314 or the split transfer row address (ST-R) from the split transfer row address (ST-RA) generation counter 315.
A) is selected and supplied to the row decoder 304.

The selection operation of the row address selector 316 is controlled by the trigger signal from the split transfer trigger circuit 317. That is, the row address selector 316 receives the split transfer row address (S) when the trigger signal is generated from the split transfer trigger circuit 317.
T-RA) is selected, and the row address (RA) from the row address register 314 is selected otherwise.

The split transfer trigger circuit 317 monitors a change in the output QSF of the register 311. When the QSF changes from "0" to "1" or from "1" to "0" in the serial read cycle, the split transfer trigger circuit 317 performs split transfer. Generates a trigger signal for automatic cycle insertion. Also,
The split transfer trigger circuit 317 also generates a trigger signal when the QSF is "1" immediately after the end of the serial read cycle. The trigger signal is supplied to the split transfer timing control circuit 318 and the row address selector 316.

Split transfer timing control circuit 318
When the trigger signal is received, various timing signals necessary for executing the split transfer cycle (a signal EN1 for enabling the left transfer gate 305, a signal EN2 for enabling the right transfer gate 306, and a row decoder 304 are enabled). Signal EN3 to be set, clock C to the split transfer row address generation counter 315
K, etc.). In this case, the signals EN1 and EN2 are alternatively generated according to the value of QSF.

That is, when QSF changes to "1", the signal EN1 is generated so that split transfer to the left shift register 307 is executed, and when QSF changes to "0", the right shift register 308 is transferred. Signal EN2 is generated so that split transfer is executed.

Further, the split transfer timing control circuit 318 generates a wait signal WAIT during the automatically inserted split transfer cycle. This wait signal WAIT is for notifying the memory control circuit 14 via the predetermined external output terminal of the VRAM 30 that the split transfer cycle is being executed, and the memory control is performed until the generation of the wait signal WAIT is stopped. Circuit 1
The insertion of another memory control cycle by 4 is awaited.

The timing generation circuit 319 receives various control signals (row address strobe (RAS), column address strobe (CAS), data transfer / output enable (DT / OE), write per bit / write enable from the memory control circuit 14. (WB / WE), etc.), a timing signal for controlling the operation mode of the VRAM 30 is generated.

As described above, in this VRAM 30,
In addition to the normal circuit configuration for random access and serial access, a row address register 314 and a split transfer row address (ST-RA) generation counter 31 are provided as circuits for automatic insertion of split transfer cycles.
5, a row address selector 316, a split transfer trigger circuit 317, and a split transfer timing control circuit 318 are provided.

Next, the start-up operation of the split transfer cycle using these circuits will be described. When reading the image data from the serial access port (serial DATA) of the VRAM 30, the memory control circuit 14 first sets the RA
The normal transfer cycle of the VRAM 30 is activated by S and DT / OE.

In this normal transfer cycle, the row address (RA) output from the memory control circuit 14 is selected by the row address selector 316 and supplied to the row decoder 304. As a result, the row address (R
Data of 512 × 8 bits (data D1 and D2 indicated by diagonal lines) for one row of the memory cell array 301 designated by the value of A) are read from the memory cell array 301 and transferred via the transfer gates 305 and 306. It is transferred to the shift registers 307 and 308.

After that, serial read transfer is started. In this serial read transfer, a column address indicating the start address of the serial read transfer is set in the serial address counter 312. Data D1
The value of the start address is "0" when the data is read from the left end of, and this value is counted up by +1 in synchronization with the serial clock SC and output as a 9-bit serial address. The value of the 9-bit serial address is sequentially changed from "0" to "511" and becomes "5".
After 11 ", it returns to" 0 "again.

The serial address value is from "0" to "25".
Since QSF is "0" when it belongs to the range of 5 ", the left shift register 307 is selected by the selector 309. Then, the 256 x 8-bit data D1 transferred to the left shift register 307 is lower According to the value of the 8-bit serial address, the data is sequentially read from the 8-bit wide serial port (serial DATA) in 1 × 8 bit units.

The value of the 9-bit serial address is "25
When it becomes 6 ”, the QSF changes from“ 0 ”to“ 1 ”, and thus the right shift register 308 is selected by the selector 309. Then, the right shift register 3
The 256 × 8-bit data D2 of 08 is sequentially read in 1 × 8-bit units from the 8-bit wide serial port (serial DATA) according to the value of the lower 8-bit serial address.

When the QSF changes from "0" to "1", a split transfer cycle is automatically inserted in response to the change. That is, when the QSF changes from “0” to “1”, the split transfer trigger circuit 317
Generates a trigger signal to activate split transfer. In this split transfer, the row address RA is incremented by +1 by the split transfer row address (ST-RA) generation counter 315, which is used as the split transfer row address (ST-RA).
Sent to 04. At this time, the row decoder 304 is energized by the enable signal EN3.

Then, the data D3 and D4 of the row next to the row transferred in the normal transfer mode are read and sent to the left transfer gate 305 and the right transfer gate 306. Here, since QSF = "1", the enable signal E
Only N1 is generated and no enable signal EN2 is generated. Therefore, only the left half data D3 is transferred to the shift register 307. This transfer operation of the left half data D3 is performed in parallel with the serial read operation from the right shift register 308 described above.

After that, when the serial read operation from the right shift register 308 ends and the value of the 9-bit serial address returns to "0", the QSF changes from "1" to "0".
Changes to. Therefore, this time, the left shift register 307 is selected by the selector 309. Then, 256 split-transferred to the left shift register 307.
× 8-bit data D3 is serial port (serial D
ATA).

Further, in response to the change of QSF from "1" to "0", a split transfer cycle to the right shift register 308 is automatically inserted. That is, QSF
Of "1" to "0", a split transfer trigger circuit 317 generates a trigger signal to activate split transfer. In this split transfer, data D3 and D4 designated by the split transfer row address (ST-RA) are read and sent to the left transfer gate 305 and the right transfer gate 306. Here, since QSF = "0", the enable signal E
Only N2 is generated and no enable signal EN1 is generated. Therefore, only the right half data D4 is transferred to the shift register 308. This transfer operation of the right half data D4 is performed in parallel with the serial read operation from the left shift register 307 described above.

As described above, in this embodiment, when the shift register to be read by the selector 309 is switched from one of the left shift register 307 and the right shift register 308 to the other, the split transfer trigger circuit 317 performs the split transfer operation. Is started. In this split transfer, the split transfer row address ST-RA generated by the split transfer address generation counter 315 is the row decoder 304.
1 row of the memory cell array 301 designated by the split transfer row address ST-RA is selected.

Then, half the data of the selected one row is split-transferred to the shift register in which the data has not been read. Therefore, during the display period in which the data is read from the serial access port, the split transfer cycle can be automatically inserted without control from the external circuit.

In this embodiment, only the automatic insertion of the split transfer cycle has been described, but if the trigger signal is used as the enable signal of the sense amplifier 303, the refresh cycle can be automatically inserted in the same manner. .

[0075]

As described above, according to the present invention, the image memory and the image memory are used so that the data transfer cycle can be automatically inserted during the display period without the control from the external circuit. The display control system is realized, and the VRAM timing control by the display control system can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of a display control system according to an embodiment of the present invention.

FIG. 2 is a VR provided in the display control system of FIG.
The block diagram which shows an example of a concrete structure of AM.

[Explanation of symbols]

1 ... CPU, 2 ... System memory, 3 ... System bus,
4 ... Display control system, 10 ... Display controller, 13 ... Drawing coprocessor, 14 ... Memory control circuit,
30 ... Dual port image memory, 301 ... Memory cell array, 304 ... Row decoder, 305 ... Left transfer gate, 306 ... Right transfer gate, 307 ... Left shift register, 308 ... Right shift register, 309 ... Shift register selector, 312 ... Serial Address counter,
315 ... Split transfer row address generation counter, 3
16 ... Row address selector, 317 ... Split transfer trigger circuit, 318 ... Split transfer timing control circuit.

Claims (3)

[Claims] 1. In a dual port image memory having a random access port and a serial access port, a memory cell array composed of a plurality of memory cells arranged in a matrix of rows and columns, and a half of one row of the memory cell array. First and second data buffers that respectively hold the data and serial reading means that selectively selects these data buffers and serially reads the data held in the selected data buffers to the serial access port. Split transfer address generating means for generating a row address for split transfer designating one row of the memory cell array in which data following the data held in the selected data buffer is stored, and the split transfer To the row address for Selected one row of the memory cell array, and split transfer means for transferring half the data of the selected row to the non-selected data buffer, and switching of the data buffer selected by the serial reading means. An image memory comprising a split transfer starting means for detecting a ring and executing a data transfer by the split transfer means in response to the detection. 2. The image memory according to claim 1, further comprising an output terminal for outputting a signal indicating that the data transfer is being executed by the split transfer means to the outside. 3. A display control system for controlling a display monitor of a computer, wherein a dual port image memory having a random access port and a serial access port, and access control of the dual port image memory are performed through the random access port. Memory control means for drawing image data to the dual port image memory and reading image data from the serial access port; and image data read from the dual port image memory to a video signal of the display monitor. The dual port image memory includes a memory cell array composed of a plurality of memory cells arranged in a matrix of rows and columns, and holds half data of one row of the memory cell array. The first and second data buffers, and serial reading means for selectively selecting these data buffers and serially reading the data held in the selected data buffers to the serial access port; Split transfer address generating means for generating a row address for split transfer for designating one row of the memory cell array in which data following the data held in the data buffer is stored; and a row address for split transfer. Split transfer means for selecting one row of the specified memory cell array and transferring half the data of the selected row to the non-selected data buffer, and switching of the data buffer selected by the serial reading means. Detect and respond to the detection by the sp A display control system comprising: a split transfer starting means for executing data transfer by a lit transfer means on one chip.