JPH08255107A - Display controller - Google Patents

Abstract

PURPOSE: To provide a display controller which is inexpensive and has high performance by improving the efficiency of read/write transfer of image data without using a 2-port VRAM. CONSTITUTION: A synchronous DRAM 30 is used as a video memory which stores screen images instead of a VRAM. A memory control circuit 14 which controls the synchronous DRAM 30 is provided with an address control circuit 143 including a page hit detecting mechanism and a command control circuit 144, which perform command generation control for switching access cycles of the synchronous DRAM 30 according to address values. Therefore, a precharge cycle is prevented from being inserted at the time of sequential access, and consequently the access efficiency of the synchronous DRAM 30 can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display controller, and more particularly to a display controller for controlling a display monitor of a personal computer.

[0002]

2. Description of the Related Art In recent years, various portable laptop or notebook type portable personal computers have been developed. Conventionally, as a display controller used in this type of computer,
The one that supported a medium resolution display of about 640 × 480 dots was the mainstream. Recently, in order to realize an advanced graphical user interface, for example, 10
Display controllers have also been developed that can support high resolution displays such as 24x768 dots or 1280x1024 dots.

In a display controller that supports such high resolution graphics display, a dual port VRAM is often used as a video memory for holding screen images such as characters and figures.

The dual port VRAM has a parallel port and a serial port that can be accessed independently of each other. The parallel port is a port for randomly accessing the memory cell array of the dual port VRAM and is used for updating display data. The serial port is for serially outputting one row of display data from the memory cell array and is used for reading display data for screen refresh.

A dual port VRAM having such a configuration
Is suitable for high-resolution graphics display in that the problem of conflict between the screen refresh process and the image data update process can be avoided.

However, when such a dual port VRAM is used, the control of the serial port is required in addition to the control of the parallel port, so that the configuration of the memory control logic incorporated in the display controller becomes very complicated. This causes a problem of increasing the chip area and cost when the display controller is realized by a one-chip LSI.

Therefore, recently, dual port VRA
As a memory replacing M, a synchronous DRAM is drawing attention. Although the synchronous DRAM does not have a serial port, it has a characteristic that data transfer via a parallel port can be executed at a relatively high speed. Therefore, if the synchronous DRAM is used, the screen refreshing process and the image data updating process can be compatible with each other at a higher level than in the case of using the normal DRAM, and the dual port V
The memory control logic can be simplified as compared with the case of using the RAM.

However, the architecture of the conventional memory control logic for a synchronous DRAM is not based on the assumption that the synchronous DRAM is used as a video memory, but is designed mainly to randomly access the synchronous DRAM. Has been done. The conventional access control procedure for the synchronous DRAM is as follows.

That is, the operating states of the synchronous DRAM are all controlled by commands. The commands include a bank active command, a read / write command, and a bank precharge command. These three commands are sequentially generated in one access cycle for the synchronous DRAM.

The bank active command selects one bank out of two banks in the synchronous DRAM and specifies that a page (row) in the bank is selected by a row address to activate it. Command. The read / write command specifies execution of a read / write cycle for reading / writing the column in the page, and the precharge command specifies precharging the read / write accessed page. Command.

Originally, the precharge cycle executed by the precharge command only needs to be executed when the pages to be accessed are different, and need not be executed if the same page is continuously accessed.

However, since the conventional memory control logic is designed on the premise of random access as described above, no command control logic for switching the access procedure of the synchronous DRAM according to the address value is incorporated.

Therefore, in the past, synchronous DRA has been used.
When the access cycle for M is repeatedly executed, the bank precharge cycle and the bank precharge cycle are always provided between the previous read / write cycle and the next read / write cycle regardless of the value of the page to be accessed, that is, the row address. An active cycle was inserted.

Therefore, the conventional memory control logic has a problem that the access efficiency of the synchronous DRAM, particularly the access efficiency at the time of sequential access, deteriorates. In recent systems, the number of cases in which a display controller is connected to a high speed local bus such as a PCI bus is increasing. Therefore, it is desired that the data read operation from the video memory to the system be performed at high speed by burst transfer or the like. Since the synchronous DRAM has a burst transfer function in the chip itself, it is effective to use the synchronous DRAM as a video memory also from this point.

However, since the burst transfer function of the synchronous DRAM itself has a low degree of freedom in control, various characteristics such as read / write for display data update and display data read for screen refresh are provided. Is practically not sufficient when used as a video memory to be accessed.

Therefore, in order to realize a low-cost and sufficiently high-performance display controller, in addition to the command control for switching the access procedure of the synchronous DRAM as described above, the flexibility suitable for the access of the video memory is provided. It is desirable to implement a high burst transfer function within the memory control logic.

[0017]

Conventionally, when repeatedly executing an access cycle for a synchronous DRAM, a bank precharge cycle and a bank are always provided between a previous read / write cycle and a next read / write cycle. There is a problem that the active cycle is inserted and the access efficiency of the synchronous DRAM, particularly the access efficiency at the time of sequential access, is deteriorated. Further, conventionally, a data transfer function suitable for video memory access has not been provided, and a sufficient data transfer function cannot be realized.

The present invention has been made in view of the above circumstances, and a circuit for realizing a command control for switching the access procedure of the synchronous DRAM and a data transfer function suitable for the video memory access is provided in the synchronous D.
It is an object of the present invention to provide a display controller which is realized in a memory control logic for a RAM and thereby has a low cost and a sufficiently high performance.

[0019]

Means and Actions for Solving the Problems
In a display controller which uses a synchronous DRAM as a video memory and controls a display monitor of a computer system, in response to a read / write request from various memory access devices requesting read or write of image data to the video memory, A memory control unit for accessing the synchronous DRAM is provided, and the memory control unit sets a memory address from the memory access device in the previous video memory access cycle and a memory address from the memory access device in the next video memory access cycle. A page hit detection means for comparing and detecting a page hit / page miss according to the comparison result, and the synchronous DR according to the detection result of the page hit detection means A command control means for generating a command for controlling the operation of M. When a page miss is detected, a precharge command is generated to generate a precharge command between the previous video memory access cycle and the next video memory access cycle. A command that inserts a precharge cycle and, when a page hit is detected, prohibits the generation of the precharge command so that the precharge cycle is not inserted between the previous video memory access cycle and the next video memory access cycle. And a control means.

In this display controller, a synchronous DRAM is used as a video memory for storing a screen image. Synchronous DRA
The memory control means for controlling M is provided with a page hit detection means and a command control means, and by these, command generation control for switching the access cycle of the synchronous DRAM according to the address value is performed.

That is, if the page hit detection means detects the occurrence of a page miss, a precharge command is generated as usual, and a precharge command is generated between the previous video memory access cycle and the next video memory access cycle. Although a charge cycle is inserted, if it is a page hit, the precharge command is not generated and the read / write command for the next video memory access cycle is immediately generated.

Therefore, in the case of sequential access, it is possible to prevent the precharge cycle from being inserted, which makes it possible to access the synchronous DRAM at high speed.

Further, it is preferable that the memory control means is provided with a read transfer control means for repeatedly executing a read access cycle of the synchronous DRAM a predetermined number of times in the read mode. An address counter that sequentially increments the value of the memory address supplied from the memory access device in units of a predetermined value can be used as the read transfer control means.

According to this structure, the memory address value can be automatically incremented in the memory control means.
With a read address supplied from a memory access device such as a CPU, an accelerator, or a display circuit as a start address, data can be continuously read from a plurality of addresses subsequent thereto. Therefore, synchronous DRAM
The read data transfer speed can be greatly increased. In particular,
By changing the increment unit of the address value by the address counter according to the display mode of the display controller, the above-mentioned high-speed read transfer can be applied to various display modes.

Further, in order to prevent the storage locations in different boundaries from being accessed by the read transfer control means for a predetermined number of times of continuous read transfer, the read transfer control means is provided with the predetermined number of times of continuous operation according to the output of the address counter or the like. It is desirable to provide a read transfer stop means for terminating the execution of the read access cycle up to an arbitrary cycle among them.

As a result, it is possible to prevent a situation where a page miss occurs during high speed read transfer and a precharge cycle must be inserted. Therefore, the high-speed read transfer using this read transfer stop means is suitable for a read transfer for screen refreshing which requires reading display data for one screen across pages.

Further, instead of the read transfer stopping means, a wrap round means for returning the value of the address counter to the first storage position in the boundary when the address value from the address counter reaches the final storage position in the boundary may be provided. good. By using this wrap round means, all storage locations within the same boundary are always read accessed by a predetermined number of continuous read access cycles.

The high speed read transfer using the wrap round means is suitable for display data read by the CPU, for example. Memory access by most CPUs is performed, for example, via a cache inside a display controller or a system cache. Therefore,
If the high-speed read transfer using the wrap round means is used, it is possible to efficiently transfer, for example, one cache line of display data including the image data designated by the address from the CPU to the cache.

The high-speed read transfer using the above-mentioned wrap-round means is not limited to the synchronous DRAM, but D
It is very effective even when the video memory is composed of RAM or the like, and the system performance can be improved.

Further, the write access to the video memory by the CPU or the accelerator is often random access, and the read access is often sequential access.
It is desirable to access the video memory by directly using the memory address from the accelerator or accelerator and to perform burst read using the output of the address counter in the case of read.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the overall configuration of a display control subsystem using a display controller according to an embodiment of the present invention. The display control subsystem 4 complies with the XGA specification, and is a flat panel display 40 that is standardly equipped in the portable computer body and a color CRT display 50 that is detachably connected to the portable computer body.
Performs display control for both. The display control subsystem 4 is connected to the PCI bus 3 as shown.

The display control subsystem 4 includes a display controller 10 and a synchronous DRAM 30.
Is provided. These display controller 1
The 0 and the synchronous DRAM 30 are mounted on a circuit board (not shown).

The display controller 10 is one LSI realized by a gate array, and constitutes the main part of the display control system 4. The display controller 10 controls the flat panel display 40 and the color CRT display 50 according to an instruction from the host CPU 1. Further, the display controller 10 functions as a bus master and can directly access the system memory 2.

The synchronous DRAM 30 has a clock synchronous operation, an operation mode control by a command,
It is a memory having a characteristic of a two-bank memory cell array configuration, and is used here as a video memory for storing a screen image to be displayed on the flat panel display 40 or the color CRT display 50. The synchronous DRAM 30 constituting the video memory is, for example, a 256K × 16 bit synchronous DRAM.
This can be realized by connecting two chips in parallel. In this case, data read / write is performed in 32-bit width units.

Image data created by an application program or the like conforming to the XGA specifications is stored in the synchronous DRAM 30 by the packed pixel method. This packed pixel method is a color information mapping format in which one pixel is represented by a plurality of consecutive bits on a memory. For example, a method in which one pixel is represented by 1, 2, 4, 8, 16 or 24 bits is adopted. ing. On the other hand, VGA
The image data of the specification is created by an application program or the like conforming to the VGA specification, and is stored in the synchronous DRAM 30 by the memory plane method. This memory plane method is a method in which a memory area is divided into a plurality of planes designated by the same address, and color information of each pixel is assigned to these planes.
For example, when there are four planes, one pixel is represented by a total of 4 bits of data, one bit for each plane.

Text data is also stored in the synchronous DRAM 30. The text data for one character consists of an 8-bit code and an 8-bit attribute for a total of 2 in both XGA and VGA specifications.
Has a size of bytes. The attribute is composed of 4-bit data specifying a foreground color and 4-bit data specifying a background color.

The display controller 10 includes a register control circuit 11, a system bus interface 12,
Graphics accelerator 13, memory control circuit 1
4, CRT controller (CRTC) 16, sprite memory 19, serializer 20, latch circuit 21, foreground / background multiplexer 22, graphic / text multiplexer 23, color palette control circuit 24, sprite color register 25, CR
T video multiplexer 26, sprite control circuit 2
7, a flat panel emulation circuit 28, and a DAC (D / A converter) 35.

The register control circuit 11 receives an address and data from the PCI bus 3 via the system bus interface 12, decodes the address, and performs read / write control for various registers designated by the decoding result.

The system bus interface 12 has a P
It controls the interface with the host CPU 1 through the CI bus 3 and supports burst transfer. Further, the system bus interface 12 has a cache 121 built therein. The cache 121 is used to speed up the transfer of image data between the CPU 1 or the accelerator 13 and the synchronous DRAM 30, and the synchronous DR
It holds a part of the image data of AM30. CPU1
If the image data requested to be read by the accelerator or the accelerator 13 exists in the cache 121, the image data is read from the cache 121 and the CP is read.
It is transferred to U1 or the accelerator 13. In this case, the synchronous DRAM 30 is not read accessed.

The graphics accelerator 13 is a CP
In response to the instruction from U1, the synchronous DRAM 30
It provides various drawing functions for the image data inside. The accelerator 13 performs pixel block transfer such as BITBIL, line drawing, area filling, logical / arithmetic operation between pixels, screen cutout, map mask, XY addressing, and paging memory management function. have. This accelerator 1
3 is a VGA / XGA compatible data operation circuit 131,
A two-dimensional address generation circuit 131 and a paging unit 133 are provided.

The data operation circuit 131 performs data operations such as shifts, logical arithmetic operations, bit masks and color comparisons, and also has a VGA compatible BITBLT function. The two-dimensional address generation circuit 131 generates an XY two-dimensional address for accessing a rectangular area or the like. Further, the two-dimensional address generation circuit 131 also performs an area check and a conversion process to a linear address (real memory address) using segmentation or the like. The paging unit 133 is for supporting the same virtual storage mechanism as the CPU 1, and converts a linear address created by the two-dimensional address generation circuit 131 into a real address by paging when paging is enabled. Further, when paging is invalid, the linear address becomes the real address as it is. The paging unit 133 has a TLB for paging.

The memory control circuit 14 is a synchronous DRA.
CPU for access control of M30, CPU
1 and the synchronous DRAM 30 according to the read / write request of the image data from the accelerator 13.
Read / write access, and read access to the synchronous DRAM 30 for screen refresh according to the display position address from the CRTC 16.

The memory control circuit 14 incorporates an address control logic and a command control logic for improving the access efficiency to the synchronous DRAM 30. These logics make it possible to continuously execute a plurality of read / write cycles for the synchronous DRAM 30 without inserting a precharge cycle. Further, the memory control circuit 14 has a built-in address counter and has a burst read transfer function of continuously reading data from a plurality of addresses following the read address as a start address.

Memory control circuit 14 and synchronous DRA
The data bus width between M30s is set to 32 bits, which is the same as the data transfer width of the PCI bus 3. The configuration of such a memory control circuit 14 is a feature of the present invention, and its details will be described later with reference to FIG.

CRT controller 16, sprite memory 19, serializer 20, latch circuit 21, foreground / background multiplexer 22, graphic / text multiplexer 23, color palette control circuit 24, sprite color register 25, CRT video multiplexer 26, sprite control. Circuit 27, flat panel emulation circuit 28, and DAC
The (D / A converter) 35 constitutes a display control circuit for reading image data from the synchronous SRAM 30 and converting it into a video signal for screen refresh.

The CRT controller (CRTC) 16 is
Various display timing signals (horizontal synchronizing signal, vertical synchronizing signal, etc.) for controlling the flat panel display 40 or the CRT display 50, and synchronous DRA
A display address for reading the image data to be displayed on the screen from M30 is generated.

Sprite data is written in the graphics mode in the sprite memory 19, and fonts are written in the text mode. In the text mode, the code of the text data read from the synchronous DRAM 30 is supplied to the sprite memory 19 as an index, and the font corresponding to the code is read.

The serializer 20 is a synchronous DRA.
A parallel / serial conversion circuit for dividing parallel pixel data for a plurality of pixels read from the M30 into pixel units (serial) and outputting the same. In the graphics mode, the image data read from the synchronous DRAM 30 and the sprite memory. The sprite data read from 19 is converted to parallel / serial, and in the text mode, the font data read from the sprite memory 19 is converted to parallel / serial.

The latch circuit 21 is for delaying the attribute output timing by the delay time of conversion from code data to font data, and holds the attribute of text data read from the synchronous DRAM 30 in the text mode. The foreground / background multiplexer 22 selects one of the attribute foreground color (front color) / background color (background color) in the text mode. This selection is made by selecting the font data values “1” (foreground) and “0” output from the serializer 20.
Controlled by (background). The graphic / text multiplexer 23 is for switching between the graphics mode and the text mode,
The memory data output from the serializer 20 is selected in the graphics mode, and the foreground / background multiplexer 2 is selected in the text mode.
Select 2 outputs.

The color palette control circuit 24 is for performing color conversion of graphics or text data. The color pallet control circuit 24 has a two-stage color pallet table. The first color palette table is composed of 16 color palette registers. Each color palette register has
6-bit color palette data is stored. The second color pallet table is composed of 256 color pallet registers. Each color palette register stores 24-bit color data consisting of 8 bits for each of R, G, and B.

In the graphics mode, 8-bit / pixel XGA specification memory data is sent directly to the second color palette table without going through the first color palette table, where R, G, and B are each 8 Converted to color data composed of bits. Also,
The 4-bit / pixel memory data of the VGA specification is first sent to the first color palette table, where it is converted into 6-bit color data and output. And
To this 6-bit color data, 2-bit data output from a color selection register built in the color pallet control circuit 19 is added, thereby forming a total of 8 bits of color data. After that, the 8-bit color data is sent to the second color palette table, where it is converted into color data of 8 bits for each of R, G, and B.

On the other hand, in the text mode, XG
Text data of both A and VGA can be read via R, R, and R via the first and second two-stage color palette tables.
Each of G and B is converted into color data composed of 8 bits.

In the XGA graphics mode, there is a direct color mode in which one pixel is composed of 16 bits or 24 bits. In this case, the pixel data of the pixel does not go through the color palette control circuit 24. It is directly supplied to the CRT video multiplexer 26.

The sprite color register 25 stores sprite display data designating a sprite display color of a hardware cursor or the like. The CRT video multiplexer 26 selects the CRT video display output, and selects the output of the color palette control circuit 24, the direct color output from the serializer 20, the sprite display data, or the external video data. This selection operation is controlled by the display timing signal from the CRTC 16. The external video data is video data such as a moving image input from outside the display control system 4, for example. The sprite control circuit 27 uses the serializer 20.
The sprite display data of the sprite color register 25 is output according to the parallel / serial converted sprite data.

Flat panel emulation circuit 28
Converts the CRT video output to produce flat video data for flat panel display 40. DA
The C 35 converts the CRT video data output from the CRT video multiplexer 26 into analog R, G, B signals and supplies the analog R, G, B signals to the CRT display 50.

Next, referring to FIG. 2, the memory control circuit 1
A specific configuration of No. 4 will be described. The memory control circuit 14 is
A plurality of memory access devices (CPU 1, accelerator 13, requesting read / write of image data,
Display circuit) from each memory address (ADDRES
S), access mode (MODE), data (DAT)
A) is received and the command required for accessing the synchronous DRAM is issued. Access mode (MODE)
Indicates the read / write type and three read modes (single mode,
Boundary list top mode, wrap round mode).

The memory control circuit 14 includes an arbiter 141, a multiplexer 142, an address control circuit 143, and a command control circuit 144, as shown in the figure. The arbiter 141 is a logic for arbitrating contention of video memory access by a plurality of memory access devices, selects one of the video memory access requests (REQ) output from the plurality of memory access devices, An access permission signal (ACK) is issued to the device.

The multiplexer 142 receives the memory address (ADD) from each of the plurality of memory access devices.
RESS), access mode (MODE), and data (DATA), the memory address (ADD) from the device to which access is permitted by the arbiter 141.
RESS), access mode (MODE), and data (DATA).

The address control circuit 143 is a logic for controlling the address value given to the synchronous DRAM 30, and converts the memory address selected by the multiplexer 142 into the physical address ADRS (row address, column address) of the synchronous DRAM 30. To do. Further, the address control circuit 143 holds the row address in the previous memory access cycle, and determines the page hit / miss according to whether the row address and the row address in the current memory access cycle match. If the page is missed, the bank enable request signal BEQ is generated, but if the page is hit, the bank enable request signal BEQ is not generated.

Here, a page hit means that the row address in the previous memory access cycle and the row address in this memory access cycle match, that is, the same page in the same bank of the synchronous DRAM 30 is continuously accessed. Means that. On the other hand, a page miss means that the row address in the previous memory access cycle and the row address in the current memory access cycle do not match, that is, different banks in the synchronous DRAM 30 between the previous time and this time, or different pages in the same bank. Means being accessed.

Further, the address control circuit 143 has an address counter in order to realize a burst transfer function for continuously accessing the synchronous DRAM 30. This address counter is a multiplexer 14
The value of the column address corresponding to the memory address selected by 2 is sequentially incremented to generate a plurality of continuous column addresses. This contiguous address is
It is used for read access to the synchronous DRAM 30. On the other hand, when performing write access to the synchronous DRAM 30, the memory address selected by the multiplexer 142 is used as it is,
The address counter is not used.

The command control circuit 144 generates various commands for controlling the operation of the synchronous DRAM 30. These commands include bank active commands, read / write commands, and bank precharge commands.

The bank active command selects one of the two banks in the synchronous DRAM 30 and specifies that a page (row) in the bank is selected by a row address and activated. Command. The read / write command is a command for designating a column in a page and designating execution of a read / write cycle for reading / writing the column. The bank precharge command is a command that specifies precharging a page that is read / write accessed.

Generation of these commands by the command control circuit 144 is controlled by a bank enable request signal (BEQ) from the address control circuit 143. That is, in the case where a read / write cycle for the synchronous DRAM 30 is executed a plurality of times, if a page miss occurs, a bank precharge command and a bank active command are issued after the last read / write cycle is completed. , Next lead /
A read / write command for the write cycle is generated. On the other hand, if there is a page hit, the previous read /
Immediately after the end of the write cycle, a read / write command for the next read / write cycle is generated.
FIG. 3 shows how such a command generation sequence is switched. As can be seen from FIG. 3, in the case of a page miss, the bank precharge cycle and the bank active cycle are always inserted between the previous read / write cycle and the next read / write cycle, but in the case of a page hit. , The bank precharge cycle and the bank active cycle are omitted.

Further, the commands generated from the command control circuit 144 include a mode register set command. The mode register set command is a command for initializing the operation mode of the synchronous DRAM 30, and is generated in response to the release of the reset signal when the system is powered on or the system is reset. As a result, the mode register in the synchronous DRAM 30 is
Mode information that specifies the contents of the CAS delay amount (2 clocks, 3 clocks, or 4 clocks), addressing mode (sequential mode or interleave mode), burst mode (burst length = 0, 2, 4, or 8) is set. To be done. The content of this mode information is stored in the register 145 in advance, and in response to the release of the reset signal, the address ADR from the address control circuit 143 is sent.
The S is notified to the synchronous DRAM 30 and is set in the mode register in the synchronous DRAM 30.

Here, the sequential mode is a mode in which addresses are sequentially arranged for all pages included in the two banks of the synchronous DRAM 30. In this sequential mode, two banks do not operate simultaneously. The interleave mode is a mode in which addresses are alternately arranged in two banks in page units so that an active cycle of one bank of the two banks of the synchronous DRAM 30 can be executed during a precharge cycle of the other bank. Since this interleave mode enables simultaneous operation of two banks, it enables faster access than the sequential mode, but consumes more power accordingly. In both of the sequential mode and the interleave mode, the control of command generation based on the page hit determination described above can be applied.

However, since the access efficiency can be sufficiently improved only by the command generation control by the page hit determination of this embodiment without using the interleave mode, the sequential operation is performed in this embodiment from the viewpoint of reducing the power consumption. I will use the mode.

The burst mode is a synchronous DRAM
In this mode, burst transfer is performed by using the address increment function of 30 itself. In this embodiment, since the burst transfer is performed by using the address counter of the address control circuit 143, the burst mode of the synchronous DRAM 30 is not used. Therefore, the burst length is set to 0 when the synchronous DRAM 30 is initialized.

Next, the specific structure of the address control circuit 143 will be described with reference to FIG. As shown in FIG. 4, the address control circuit 143 includes a page hit detection circuit 201, an address counter 202, an address multiplexer 203, a latch circuit 204, and the like.

The page hit detection circuit 201 includes a latch circuit 201a and a row address comparator 201b.
It has. The latch circuit 201a holds the row dress (RA) in the previous memory access cycle. The row address comparator 201b compares the row dress (RA) held in the latch circuit 201a in the previous memory access cycle with the row dress (RA) held in the latch circuit 204 in the current memory access cycle. Latch circuit 201a
When the page address is detected by the row address comparator 201b, the value of the row address held at is switched to the row address (RA) in the current memory access cycle held in the latch circuit 204 at that time.

The address counter 202 includes an increment constant multiplexer 202a and an address adder 202.
b, a column address multiplexer 202c, and a flip-flop 202d.

Increment constant multiplex 202a
Selects one of the three increment constants (+1, +2, +4) in order to define the address count-up unit by the address counter 202. This selecting operation is automatically performed according to the display mode designated by CPU 1.

The address adder 202b holds the column address multiplexer 20 held by the flip-flop 202d in order to sequentially increment the value of the column address supplied to the synchronous DRAM 30.
2c output value, increment constant multiplex 20
The increment constant selected by 2a is added.

Column address multiplexer 202c
Selects one of the mode information of the mode register 145, the row address RA, the column address CA, and the address counter output CAX in order to switch the address to be supplied to the synchronous DRAM 30, and supplies it to the synchronous DRAM 30 as ADRA. To do. FIG. 5 shows the relationship between the address selection operation of the column address multiplexer 202c and the memory cycle.

As shown in FIG. 5, in the mode setting cycle for initializing the synchronous DRAM 30, the mode information of the mode register 145 is selected. Further, in the bank active cycle for selecting the bank of the synchronous DRAM 30, the row address RA included in the memory address selected by the multiplexer 142 is selected. In the write access cycle, the column address CA included in the memory address selected by the multiplexer 142 is selected. In the single read access cycle, the column address CA included in the memory address selected by the multiplexer 142 is selected. In the burst read access cycle, the column address CA included in the memory address selected by the multiplexer 142 is selected in the first read cycle, but the output CAX of the address counter 202 is selected in the second and subsequent read cycles. It

Next, the read / write access operation of the image data to the synchronous DRAM 30 will be described with reference to the timing chart of FIG. here,
It is assumed that the read / write transfer of four consecutive times is the minimum unit of the memory cycle, and the same page is always addressed in the read / write transfer of the four times.

First, the memory control circuit 14 sends a bank active command BA to the synchronous DRAM 30.
Is generated and the row address is specified. In this case, the address multiplexer 203 selects the row address value Ra consisting of the upper bit part of the memory address selected by the multiplexer 142.

Thereafter, the memory control circuit 14 sends a read / write command (R) to the synchronous DRAM 30.
/ W) is generated and the column address is designated.
In this case, the address multiplexer 203 selects the column address value a1 formed of the lower bit part of the memory address selected by the multiplexer 142. When the column address is designated, the synchronous DRAM 30 starts the read / write operation.

The memory control circuit 14 writes 4 bits to the synchronous DRAM 30 while sequentially redesignating the column address.
Perform one read / write operation. In this case, as the column addresses a2 to a4, in the write mode, the column address CA composed of the lower bit part of the memory address selected by the multiplexer 142 is used.
In the read mode, the address counter output CAX is used. This completes the memory cycle including four read / write transfers.

In parallel with the fourth read / write transfer,
The page hit detection circuit 201 checks whether the row address value Rb for the next memory cycle matches the row address value Ra in the previous memory cycle. If there is a page miss, page hit detection circuit 2
A bank enable request signal (BEQ) is generated from 01. Then, the bank precharge command PR for precharging the page accessed in the previous memory cycle by the command control circuit 144, and the bank active command B for designating the bank and page accessed in the next memory access cycle.
A is generated. When the bank active command BA is generated, the address multiplexer 203 selects the row address value Rb consisting of the upper bit part of the new memory address selected by the multiplexer 142.

Thereafter, the memory control circuit 14 sends a read / write command (R) to the synchronous DRAM 30.
/ W) is generated and the column address is designated.
In this case, the address multiplexer 203 selects the column address value b1 formed of the lower bit part of the memory address selected by the multiplexer 142. When the column address is designated, the synchronous DRAM 30 starts the read / write operation.

The memory control circuit 14 sequentially re-specifies the column address and, while sequentially redesignating the column address, the memory
Perform one read / write operation. In this case, as the column addresses a2 to a4, in the write mode, the column address CA composed of the lower bit part of the memory address selected by the multiplexer 142 is used.
In the read mode, the address counter output CAX is used. As a result, 2 including 4 read / write transfers
The second memory cycle ends.

In parallel with the fourth read / write transfer in the second memory cycle, it is determined whether the row address value Rc for the next memory cycle matches the row address value Rb in the previous memory cycle. It is checked by the page hit detection circuit 201. If it is a page hit, the bank enable request signal (BEQ) is not generated from the page hit detection circuit 201. Then, the command control circuit 144 immediately generates a read / write command (R / W) for the next memory cycle and specifies the column address.

As described above, in the case of page hit, the precharge cycle and the bank active command are not inserted, so that the memory access efficiency can be improved.

Next, three read modes (single mode, boundary list mode, wrap round mode) supported by the memory control circuit 14 will be described. As described above, in the read mode, when the start address is designated, the address after that is automatically generated by the address counter 202 and the read transfer is performed a predetermined number of times (for example, four times).

[Single Read Mode] In this mode, the read transfer of the specified start address is performed only once, and the memory cycle is completed.

[Boundary List Mode] This mode is one of the burst transfer modes in which four read transfers are used as the minimum memory cycles, but it is ensured that the storage positions in different boundaries are not accessed by the four read transfers. In addition, according to the value of the column address, the execution of four consecutive read transfers is ended by an arbitrary transfer cycle among them.

Here, the data size read by one read transfer is 32 bits (double word),
Since four read transfers are performed in one read cycle, one boundary is 4 double words (= 32 bits × 4). Double word data at the first address of each boundary is the lower 2 bits of column address = "00"
, The double word data of the second address is "01", and the double word data of the third address is "1".
Double word data of 0 "and the last address is designated by" 11 ".

Therefore, when the lower 2 bits of the column address become "11", the subsequent address increment is not executed and the cycle ends there. Figure 7
Shows the relationship between the memory cycle and the start address in the boundary list mode.

In cycle 1 of FIG. 7, since the lower 2 bits of the column address included in the start address are "01", the read transfer is aborted 3 times. In cycle 2 and cycle 3, since the lower 2 bits of the column address included in the start address are “00”,
All four read transfers are executed.

By using this boundary list mode, memory locations in different boundaries are not accessed by four read transfers. Therefore, it is possible to prevent a situation in which a carry occurs from the column address to the row address during the increment of the address and a page miss occurs during the memory cycle.

Therefore, this boundary list mode is suitable for read transfer for screen refreshing, which requires reading display data for one screen across pages.

FIG. 9 is a timing chart showing four times of boundary list transfer. In the figure, (a) shows a clock signal, (d) shows a row address signal, and (e).
Is the column address signal, and (j) is the RD_LAST signal indicating the end of the cycle. The other signals are internal generation signals generated by the address control circuit shown in FIG. 4, and are not directly related here, and therefore their explanations are omitted.
In this timing chart, when the column addresses a1 and a2 shown in (e) are output, it is determined that the address has come to the boundary boundary, and the RD_LAST signal indicating the termination of the cycle is output as shown in (k). As a result, when the lead is read four times, the read is finished in two times. Then, as shown in (l), the precharge command and the bank active command are output. Then, in the next cycle (row address R), since it starts from the initial address (column address b1),
As shown in (l), all four read transfers are executed.

[Wrap Round Mode] This mode is C
This mode is suitable for PU read. Memory access by the CPU is performed via the read buffer. C
When reading the memory data, the PU first reads the data into the read buffer, and then also collectively reads other data in the same boundary as the data. Then, after that, the first data is read from the buffer. At the time of the next data read, the read address is compared with the address of the data transferred to the buffer. If a hit occurs, the data is read directly from the buffer, and if a miss occurs, the same read access is made to the SDRAM. To request. For this reason, in this mode, a wrap round address is created that allows access to all 4WD data (address data that differs only in the lower 2 bits), which is the same boundary as the address passed from the device, as the start address. There is.

This mode is one of the burst transfer modes in which the minimum memory cycle is four read transfers as in the boundary list mode. However, when the lower 2 bits of the column address become "11", Is returned to "00" and the address increment operation by the address counter 202 is continued. FIG. 8 shows an example of the relationship between the address value generated in the wrap round mode and the start address.

In FIG. 8, in case 1, since the start address is the value “0000” that specifies the start address of the 4 × double word boundary, the wrap round is not executed, and three consecutive addresses following the start address are executed. The values "0001", "0010", "0011" are generated by the address counter 202.

In case 2, the start address is 4 × the value "001" designating the final address of the double word boundary.
Since it is "1", the output value of the address counter 202 is returned to "0000", and counting up is started from there. Therefore, following the start address "0011", three address values "0000" smaller than the start address are started. “,” “0001” and “0010” are generated by the address counter 202.

In case 3, the start address designates the third address of the 4 double word boundary "101".
Since it is "0", the output value of the address counter 202 is "1011" which is the fourth address.
Generated by, and returned to the first address "1000",
The second address "1001" is generated. Similarly,
In case 4, since the start address is "1001" which specifies the second address of the 4 double word boundary, the output value of the address counter 202 is "1010" which is the third address, and further at the fourth address. A certain "1011" is generated.

FIG. 10 is a timing chart showing four wrap round transfers. Column addresses a1, a2, a3, and a4 are output as shown in FIG.
(For example, in case 3 shown in FIG. 8, a1 = “101
0 ", a2 =" 1011 ", a3 =" 1000 ", a4
= “1001” is output. ) Then, the RD_LAST signal indicating the end of the cycle is output when the column address a4 is output. As a result, as shown in FIG. 10 (l), the data of 4 bytes in the same boundary is read.

As described above, if the wrap round mode is used, it is possible to read the data at all the storage locations within the same boundary by four times of read transfer. This wrap round mode is suitable for reading image data by the CPU 1 or the accelerator 13. This is for the following reason.

That is, when the CPU 1 or the accelerator 13 reads image data, the image data read from the synchronous DRAM 30 is temporarily held in the cache memory 121, and the CPU 1 or the accelerator 13 is read from the cache memory 121.
Transferred to.

In the next read access by the CPU 1 or the accelerator 13, a cache hit / miss is determined, and if it is a cache hit, the synchronous DRA is performed.
The read access of M30 is not performed, and the data is immediately read from the cache memory 121. If it is a mishit, a read cycle for the synchronous DRAM 30 is executed, and the CPU 1 or the accelerator 1
The image data (4 double words) for one cache line including the image data designated by the start address from 3 can be efficiently transferred to the cache 121.

In the case of the display control subsystem having no cache in the display controller, the image data of 4 double words continuously read from the synchronous DRAM 30 is the primary cache or the secondary cache in the system. Alternatively, it is transferred to the CPU 1 via various buffers and the like corresponding thereto. Therefore, the lap round mode is
It can also be applied to a display control subsystem that does not have a cache.

[Text read mode] In this mode, the upper word (16 bits) and the lower word (16 bits) of data are
(Bit) is read in a time division manner. As shown in FIG. 11, the upper word stores font data, and the lower word stores character code and attribute data. Therefore, it is necessary to read them separately.

FIG. 12 is a timing chart showing a text read four times. In the case of text data, the code data is a continuous address, but the font data is a random address. Therefore, the active command for the code and the active command for the font data are separately output, and the read is also shown in FIG. And as shown in (w), the code reading and the font data reading are performed separately. Note that Pf shown in (i) and (w) is an auto precharge signal. As described above, since the code data is continuous, there is a high probability of hits, but since the font data is random, there is a high probability of a miss hit. For this reason, if a bank precharge command is output after determining a mishit, a delay occurs in time, so a command called read with autoprecharge is executed in addition to the normal bank precharge command. This read with autoprecharge command is provided as SDRAM as one of the memory read / write commands of SDRAM.

[Random Write Mode] In this mode, the precharge cycle is executed unless the next request comes during the write cycle.

FIG. 13 is a timing chart showing four random write transfers. When a write command request is output as shown in (h) of the figure, a WT_LAST signal indicating the end of the write cycle shown in (i) is output, and the fourth write command shown in (j) is output. If the request for the next write command is not output, the precharge cycle (PR) is executed.

[Continuous Light Mode] FIG.
Is a timing chart showing four continuous write transfers.

This mode is suitable when it is known that continuous write transfer is performed, such as rectangular transfer called BitBlt in write transfer of the accelerator. When this mode is designated, information that write transfer is to be continuously performed is given, and as shown in FIG. 14I, after the write cycle is completed, the precharge cycle is not inserted and the next request is waited for.

FIG. 15 shows the command control circuit 14 shown in FIG.
4 is a circuit included in 4 for satisfying the operation specifications of the SDRAM. It is output to the SDRAM. The minimum time that must be satisfied is defined between commands such as active commands, precharge commands, refresh commands, and read / write commands. These specified times take different values depending on the type of SDRAM. The control circuit shown in FIG. 15 is an SDRAM to be used.
By simply specifying the product type and operating frequency of, the access that satisfies the regulations is enabled.

The control circuit shown in FIG. 15 controls the internal operation to generate a command to the SDRAM at the same time when the internal operation transits to the next state, and further has a plurality of counters inside to count the time from the generation of each command. are doing. By adding that the output of the counter has a value satisfying the specified time (PAS *) in the transition condition to the next state, an access flow satisfying the specified time is realized.

In FIG. 15, the counter 1441 starts counting in response to the bank active command. The output of the counter 1441 indicates the elapsed time from the command issuance to the present. The gate circuit 1143 outputs a signal that satisfies the specified values of various SDRAMs. For example, in the case of an SDRAM defined to output a read / write command at the second clock after the bank active command is output, the counter 1441 outputs a "1" signal when it counts for two clocks. Each signal from the gate circuit 1143 is output to the multiplexer 1445. In the register 1447, a value according to the type of SDRAM and operating frequency is set. The multiplexer 1445 changes the output corresponding to the value from the register 1447 to the condition signal (PAS).
Output as *).

FIG. 16 is a diagram showing a state of internal operation of the memory control circuit 14. SDRAM in power-on state
The operation of 30 is started. In the SDRAM register set state, the SDRAM mode register set is executed. Self refresh is a state in which self refresh is being executed. Idle indicates the state of waiting for a request from the device. Bank check is a state in which bank comparison is performed. Auto refresh is a state in which auto refresh is being executed. The ACK precharge is a state indicating that the request has been accepted and the precharge is being executed. Bank active is a state indicating that bank active is being executed. Write is a state indicating that write transfer is being executed. Read is a state in which read transfer is being executed. The wait state indicates a wait for the output of read data to end. NOP precharge has no request and indicates the state of precharge execution. FIG. 17 is a state transition diagram of each state shown in FIG. Further, FIG. 18 shows transition conditions of the state transition shown in FIG.

[0114]

As described above, according to the present invention, the command control logic for switching the access procedure of the synchronous DRAM is realized in the memory control logic for the synchronous DRAM. Therefore, in the case of sequential access, it is possible to prevent the precharge cycle from being inserted, which makes it possible to access the synchronous DRAM at high speed.

Since the memory address value can be automatically incremented in the memory control means, the read address supplied from the memory access device such as the CPU, accelerator and display circuit is used as a start address, and data is read from a plurality of addresses following the read address. Can be read continuously. Therefore, the read data transfer rate of the synchronous DRAM can be significantly increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a display control subsystem using a display controller according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a memory control circuit provided in the display controller of the embodiment.

FIG. 3 is a view for explaining the procedure of access control to the synchronous DRAM in the display controller of the embodiment.

FIG. 4 is a block diagram showing a configuration of an address control circuit provided in the memory control circuit of FIG.

5 is a diagram for explaining an address selection operation by the address control circuit of FIG.

FIG. 6 is a timing chart explaining an access operation of the synchronous DRAM by the display controller of the embodiment.

FIG. 7 is a diagram for explaining a boundary list mode used when read access is made to the synchronous DRAM in the display controller of the embodiment.

FIG. 8 is a view for explaining a wrap round mode used when read access is made to the synchronous DRAM in the display controller of the embodiment.

FIG. 9 is a timing chart showing four times of boundary list transfer.

FIG. 10 is a timing chart showing four wrap round transfers.

FIG. 11 is a diagram showing a storage state of text data.

FIG. 12 is a timing chart showing the timing of four-time text read in which a pair of code data and font data is transferred four times.

FIG. 13 is a timing chart showing four random write transfers.

FIG. 14 is a timing chart showing four continuous write transfers.

FIG. 15 is a block diagram showing a control circuit for generating a command so as to satisfy a timing time defined by specifications of various SDRAMs.

16 is a diagram showing a state of internal operation of the memory control circuit 14. FIG.

FIG. 17 is a state transition diagram of each state shown in FIG.

18 is a diagram showing transition conditions of the state transition shown in FIG.

[Explanation of symbols]

1 ... CPU, 10 ... Display controller, 13 ...
Accelerator, 14 ... Memory control circuit, 30 ... Synchronous DRAM, 121 ... Cash memory, 141 ... Arbiter, 142 ... Multiplexer, 143 ... Address control circuit, 144 ... Command control circuit, 201 ... Page hit detection circuit, 202 ... Address counter .

Claims (14)

[Claims] 1. A display controller which uses a synchronous DRAM as a video memory and controls a display monitor of a computer system, wherein read / write requests from various memory access devices requesting read or write of image data to the video memory. According to the synchronous DRA
The memory control means for accessing M compares the memory address from the memory access device in the previous video memory access cycle with the memory address from the memory access device in the current video memory access cycle. A page hit detection means for detecting a page hit / page miss according to the comparison result, and a command control means for generating a command for controlling the operation of the synchronous DRAM according to the detection result of the page hit detection means. Therefore, when a page miss is detected, a precharge command is generated, a precharge cycle is inserted between the previous video memory access cycle and the next video memory access cycle, and a page hit is detected. Last video memorial Display controller characterized by comprising a command control means for prohibiting the generation of the precharge command as precharge cycle is not inserted between the Seth cycle and the next video memory access cycle. 2. The command control means, when a page miss is detected, a precharge command for precharging a bank accessed in the previous video memory access cycle after the end of the previous video memory access cycle, and a next time When a bank active command for selecting a bank and a page to be accessed in a video memory access cycle is generated, a read / write command for accessing the selected page is generated, and when a page hit is detected, 2. The display controller according to claim 1, wherein the read / write command is generated immediately after the end of the previous video memory access cycle without generating the bank precharge command and the bank active command. 3. The memory control means, when a read access request for the video memory is issued from the memory access device, read transfer for reading image data from the synchronous DRAM to the memory access device continues. Read transfer control means for executing a read cycle repeated a predetermined number of times, the read transfer control means sequentially incrementing the value of the start address designated by the memory access device in units of a predetermined value. An address counter supplied to the DRAM, and a display mode of the display controller,
2. The display controller according to claim 1, further comprising means for changing the increment unit of the address value by the address counter. 4. The read transfer control means responds to an output of the start address or the address counter according to an output of the start address so that an address in a different boundary is not accessed by a predetermined number of continuous read transfers included in the read cycle. 4. The display controller according to claim 3, further comprising a read transfer stop means for ending the read cycle after an arbitrary number of read transfers. 5. The read transfer control means sets an address value output from the start address or the address counter so that all addresses in the same boundary are accessed by the read transfer of a predetermined number of times. 4. The display controller according to claim 3, further comprising wrap round means for returning the value of the address counter to the head address in the boundary when the final storage position in the boundary is reached. 6. A display controller which uses a synchronous DRAM as a video memory and controls a display monitor of a computer system, wherein read / write requests from various memory access devices requesting read or write of image data to the video memory. According to the synchronous DRA
The memory control means for accessing M compares the memory address from the memory access device in the previous video memory access cycle with the memory address from the memory access device in the current video memory access cycle. A page hit detection means for detecting a page hit / page miss according to the comparison result, and a command control means for generating a command for controlling the operation of the synchronous DRAM according to the detection result of the page hit detection means. Therefore, when a page miss is detected, a precharge command is generated, a precharge cycle is inserted between the previous video memory access cycle and the next video memory access cycle, and a page hit is detected. Last video memorial Access cycle between the access cycle and the next video memory access cycle, command control means for prohibiting generation of the precharge command so that a precharge cycle is not inserted, and a read access request for the video memory is issued from the memory access device. Read transfer control means for executing a read cycle in which read transfer for reading image data from the synchronous DRAM to the memory access device is continuously repeated a predetermined number of times, and the read transfer control means comprises: An address counter that sequentially increments the value of the start address designated by the memory access device in units of a predetermined value and supplies the incremented value to the synchronous DRAM; and according to a display mode of the display controller,
A means for changing the increment unit of the address value by the address counter, and font data is stored in the upper word of the data, and the upper word and the lower word of the text data in which the character code and the attribute data are stored in the lower word are time-shared. Further comprising means for reading, wherein the upper word is
A display controller characterized in that the lower word is transferred by the read transfer stop means, and the lower word is transferred based on an address designated by the memory access device. 7. The memory control means has means for executing a precharge cycle if no next write request comes in a video memory access cycle in response to a write request from the memory access device. The display controller according to claim 1, wherein the display controller is a display controller. 8. The memory control means, in response to a continuous write transfer request from the memory access device, does not execute a precharge cycle after the end of the video memory access cycle, and waits for the next read / write request. The display controller according to claim 1, further comprising: 9. The command control means includes a precharge command for precharging a bank accessed in the previous video memory cycle, a bank for selecting a bank and a page accessed in the next video memory access cycle. An active command, a read / write command for accessing the selected page after generating the bank active command, and a refresh command for refreshing the selected page are generated, and are defined by the type of the synchronous DRAM. There is provided a means for generating the command according to the type and operating frequency of the synchronous DRAM so that the minimum specified time between the precharge command, the bank active command, the read / write command, and the refresh command is satisfied. The display controller according to claim 1, wherein the display controller is a display controller. 10. A cache memory for holding a part of the image data stored in the synchronous DRAM, wherein the read transfer control means is an image read from the synchronous DRAM by the continuous read transfer. The display controller according to claim 5, wherein data is transferred to the cache memory. 11. The memory access device is a CPU of the computer system, a graphics accelerator provided in the display controller, or a display device for screen refresh provided in the display controller. The display controller according to claim 1. 12. The apparatus further comprises means for holding mode information for designating an operation mode of the synchronous DRAM, wherein the command control means responds to power-on by supplying the mode information to the synchronous DRAM. The display controller according to claim 1, wherein a mode register set command for setting the mode register is issued. 13. A display controller for controlling a day-play monitor of a computer system, comprising: a video memory for storing display data; and a memory access device when a write access request to the video memory is issued by the memory access device. Write means for performing write access to the video memory according to the specified memory address, an address counter for sequentially incrementing the value of the memory address specified by the memory access device in a predetermined value unit, and reading from the memory access device to the video memory The start address specified by the memory access device when the access request is issued,
And read means for continuously performing read access to the video memory a predetermined number of times by using the output value of the address counter, the read means including all of the same boundaries by the predetermined number of continuous read accesses. Wrap round means for returning the value of the address counter to the first storage position in the boundary when the start address or the address value from the address counter reaches the final storage position in the boundary so that the address of A display controller comprising: 14. A display controller for controlling a day-play monitor of a computer system, which is specified by a video memory for storing display data and a memory access device when a write access request for the video memory is issued from the memory access device. Write means for performing write access to the video memory according to the specified memory address, an address counter for sequentially incrementing the value of the memory address specified by the memory access device in a predetermined value unit, and reading from the memory access device to the video memory The start address specified by the memory access device when the access request is issued,
And a read means for read-accessing the video memory continuously for a predetermined number of times by using the output value of the address counter, wherein the read-out means is a storage position in a boundary different depending on the predetermined number of continuous read accesses. Read access stop means for ending execution of the predetermined number of continuous read accesses within an arbitrary cycle of the read addresses in response to the start address or the output of the address counter. Display controller.