JP2002278919A - Display control method and display controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently transfer display data to a display memory so as to store it. SOLUTION: An SDRAM arbiter 14 arbitrates data reading from SDRAM and data writing from CPU 11 for display, and automatically writes the prescribed amount of data in SDRAM 16 based on setting from CPU 11. An acceleration module 12 receives color information of display data and an address on a picture from CPU 11, and calculates the writing address of SDRAM 16 from the address on the picture of a liquid crystal display part 20, which is set by CPU 11. The data amount which is most suitable for burst transfer is calculated from the calculated address. A mask processing for preventing data writing is performed on data other than the data writing address on SDRAM 16, which is thus calculated. Then, data are written by burst transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control method and apparatus for controlling writing and reading of data to and from storage means for storing display data.

[0002]

2. Description of the Related Art A TFT liquid crystal display device is superior in resolution and color expression ability as compared with other methods, and has become mainstream as a display device of a notebook personal computer (hereinafter abbreviated as PC). On the other hand, as a color display device used in a small portable device, an STN type liquid crystal display device has been frequently used in view of cost, but in recent years, a TFT type display device has been used in view of resolution and color expression capability. The rate of use has increased.

Usually, a TFT liquid crystal display controller is used to drive a TFT type liquid crystal display device. This liquid crystal controller requires a memory area called a VRAM (video memory) for creating a display image. Is done. The type of memory used as the VRAM is an SRAM or a DRAM. Since access control to the memory is easier with the SRAM, the S
Although a RAM is used, a DRAM is usually used because an SRAM is disadvantageous in terms of cost for a large-capacity memory. Among such DRAMs, a synchronous dynamic RAM (hereinafter, referred to as an SDRAM) enables continuous transfer (burst transfer) of data of a specified number of words with one address setting.
M is frequently used. Such SDR
The AM controls the internal operation by a command.

In an electronic apparatus having a video memory using such an SDRAM, a predetermined initialization operation is performed at power-on, a mode setting command is issued to the SDRAM, and a burst length (8 words, 4 words) is issued. Word 2
By setting (word, word, full page), the data transfer amount in the subsequent read / write operation can be determined. In reading and writing data, it is necessary to set an address to be accessed after setting a read command or a write command, and then to input and output data.

FIG. 10 is a block diagram showing a schematic configuration of a conventional liquid crystal display device.
M is used.

In FIG. 10, a TFT liquid crystal display unit 905
Can display an image by a prescribed display clock, enable signal or synchronization signal, and data signal output from the TFT timing controller 907. However, since there is no means for storing image data in the TFT liquid crystal display unit 905 itself, the SDRAM controller 904 periodically performs burst transfer in units of 8 words from the SDRAM 906, which is a video memory, to read out image data and read out the TFT timing controller. 907 is transferred. The TFT timing controller 907 outputs image data in synchronization with a control signal such as a synchronization signal to the TFT liquid crystal display unit 905.

First, the CPU 901 creates image data to be displayed in the main memory 903 for one screen. After that, the write start address of the pixel data (corresponding to one dot) is designated in the SDRAM 906, and the pixel data is transferred to the SDRAM controller 904. Thus, the SDRAM controller 904 writes the pixel data sent from the CPU 901 to a specified address of the SDRAM 906 using a period other than a period for reading out pixel data to be displayed on the TFT liquid crystal display unit 905. When writing pixel data to the SDRAM 906, as in the case of reading, there is a burst transfer / write function for writing. Therefore, if this function is used for writing pixel data, it is possible to draw image data even faster.

[0008]

However, in such a conventional TFT liquid crystal display device using an SDRAM in a VRAM, pixel data for each dot is written. (Write command setting period) + (write address setting period)｝ became too large, and the efficiency was extremely low.

In addition, when data is written using burst transfer, the SDRAM controls data access by a column address and a row address, and the row address must be updated when the data exceeds 256 column addresses. There is. Therefore, when 8-word burst transfer is used effectively in the SDRAM, it is necessary to access from column 0 in units of 8 words in order to use all column addresses without waste. This means that when one dot is expressed by one word (32 bits), data is read and written by setting an address in units of 8 dots on the display screen and by 16 (= 8x2) dots when expressing two dots by one word. (Usually called an 8-dot boundary or a 16-dot boundary).

Therefore, in order to write data at an arbitrary position on the display screen, all data that does not meet the condition of the unit of 8 or 16 dots must be written in the unit of 1 dot. Therefore, when a display image is updated, a measure is taken such that image data for the entire screen including the updated portion is created in the main memory, and the data for the entire screen is transferred to the video memory by the DMA controller. There were cases.

The present invention has been made in view of the above conventional example, and has as its object to provide a display control method and apparatus for efficiently transferring and storing display data in a display memory.

[0012]

In order to achieve the above object, a display control device according to the present invention has the following arrangement.
A display data storage unit for storing display data; a data read control unit for sequentially reading display data stored in the display data storage unit and outputting the display data to a display unit; Data transfer control means for transferring and storing the display data in the display data storage means, and for inhibiting the burst transfer of the display data in accordance with the mask data for inhibiting the data transfer in the burst transfer in the predetermined data amount unit, It is characterized by having.

In order to achieve the above object, a display control method according to the present invention comprises the following steps. A display data storing step of storing display data in a display memory; and transferring and storing display data to the display memory by burst transfer in a predetermined data amount unit, and a burst transfer in the predetermined data amount unit. A data transfer control step of prohibiting burst transfer of the display data in accordance with the mask data of prohibiting data transfer, and a data reading step of sequentially reading the display data stored in the display data storing step and outputting the display data to a display unit. And the following.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

[First Embodiment] FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display device according to one embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes a CPU which controls the operation of the whole liquid crystal display device and generates image data to be displayed on a display unit (here, a TFT liquid crystal display unit 20). An acceleration module 12 is an SDRAM 16 based on a setting from the CPU 11.
Writes predetermined data to the main memory.
The main memory 13, which is used as a work memory for temporarily storing various data during operation control by the PU 11, is constituted by, for example, an SDRAM or a flash memory. Reference numeral 14 denotes an SDRAM arbiter, which inhibits writing of data from the CPU 11 to the SDRAM 16 while the data reading unit 17 is reading data from the SDRAM 16, and performs data writing to the SDRAM 16 and SD writing.
Reading of data from the RAM 16 is managed.
Reference numeral 15 denotes an SDRAM controller for writing data to the SDRAM 16 and reading data from the SDRAM 16. Reference numeral 16 denotes an SDRAM, which is used as a VRAM, where one word is composed of 32 bits. Reference numeral 17 denotes a data readout unit which receives an SDRA according to a count signal from the TFT timing controller 19
Data of one line of the TFT liquid crystal display unit 20 is read from M16. Reference numeral 18 denotes an asynchronous FIFO which stores data read by the data reading unit 17 and has a TF
Data is output in response to a request from the T timing controller 19. This FIFO 18 has 32 bits × 20
4A and 4B, which will be described later, stores image data for 400 dots (because one word is equivalent to 2 dots) on the screen of the liquid crystal display unit 20. be able to. The TFT timing controller 19 reads data from the asynchronous FIFO 18, generates a display clock and a synchronization signal that match the specifications of the TFT liquid crystal display unit 20, and generates a data signal necessary for displaying an image on the TFT liquid crystal display unit 20. Is generated and output. 20 is TF
This is a TFT liquid crystal display section provided with a T liquid crystal.

In FIG. 1, the SDRAM 16 includes:
The system clock signal (C
PU_CLK), chip select signal (CS), write enable signal (WE), row and column address strobe signal (RA
S, CAS), address bus (A0-A10) and data bus (DATA)
(32 bits) are connected.

Next, the operation of the apparatus shown in FIG. 1 will be briefly described.

The SDRAM arbiter 14 arbitrates the reading of data from the SDRAM for display and the writing of data from the CPU 11, and automatically transfers a predetermined amount of data based on the settings from the CPU 11.
Write to AM16. Acceleration module 1
2 is a CPU for displaying color information of display data and an address on the screen.
11 and set by the CPU 11,
From the address on the screen of the liquid crystal display unit 20, the SDRAM 1
6 is calculated. Then, a data amount most suitable for burst transfer is calculated from the calculated address. The data other than the data write address on the SDRAM 16 calculated in this way is subjected to a mask process for preventing data from being written, so that the influence of the data write does not occur. This allows
While performing burst transfer in units of 8 dots or 16 dots from the column address 0, not only can drawing processing be performed on an arbitrary dot, but also data of only a necessary portion can be written.

FIGS. 2A and 2B show this SDRAM 1
FIG. 2 is a timing chart showing timings of various control signals, data, and address signals input / output to / from the CPU 6;
2A shows data read timing, and FIG.
(B) shows the data write timing.

In FIG. 2A, 201 is an SDRAM
16 shows a data readout period required to read out data from 16. System clock (CPU_
CLK) 202 is supplied to the SDRAM 16.
When the row address strobe (RAS) signal 204 of the SDRAM 16 and the chip select signal 203 are enabled at the same timing, at this time, the address bus 207
Is held in the SDRAM 16 as a row address. Next, when the column address strobe (CAS) signal 205 and the chip select signal 203 of the SDRAM 16 are enabled at the same timing, at this time, the address output to the address bus 207 is held in the SDRAM 16 as a column address. Here, the write enable (WE) signal 20
6 is not active, the SRAM 16 reads data from that address and outputs it to the data bus 208.

Next, referring to FIG. 2B, SDRAM 1
6 will be described.

Reference numeral 210 denotes a data writing period necessary for writing data to the SDRAM 16. Also in this case, the row address strobe (RA
S) The signal 204 and the chip select signal 203 are enabled at the same timing, and the address data output to the address bus 207 becomes the row address as S.
When the column address strobe (CAS) signal 205 and the chip select signal 203 of the SDRAM 16 are enabled at the same timing and held in the DRAM 16,
The address output to the address bus 207 at that time is held in the SDRAM 16 as a column address.
At this timing, the write enable (WE) signal 20
6 is active (low level), the data output to the data bus 208 at this time is RAS,
The data is written to the address of the SDRAM 16 held by the CAS signal.

Reference numerals 220 and 221 denote DQM signals for masking data writing to the SDRAM 16;
In the case of bit data, DQM0 and DQM1 mask the lower 16 bits, and DQM2 and DQM3 mask the upper 16 bits.

The internal operation of the SDRAM 16 is controlled by a command from the CPU 11. The CPU 11
At power-on, after performing a predetermined initial operation, SDR
A mode setting command is issued to the AM controller 15, and the burst length (8 words, 4 words, 2 words, 1 word,
(Word, full page), latency, etc., the amount of data transferred in the subsequent read / write operation to the SDRAM 16 can be determined.

The reading of data from the SDRAM 16 and the writing of data to the SDRAM 16 are performed by C
After the state in which both S203 and RAS204 are at low level, the read command (WE206 is at high level while both CS203 and CAS205 are at low level at the same time), the write command (CS203 and CAS20
5 and WE206 are both low level at the same time)
Is performed by issuing

FIGS. 4A and 4B show dot positions and S on the display screen of the TFT liquid crystal display unit 20 according to the present embodiment.
FIG. 3 is a diagram illustrating a relationship with data in a DRAM 16.

In FIG. 4A, reference numeral 401 denotes a screen of the TFT liquid crystal display unit 20. 402 is a TFT liquid crystal display unit 2
0 indicates one dot on the screen 401, and each dot is represented by a grid in the figure. Here, the screen 4 of the liquid crystal display unit 20
The upper left dot position of 01 is represented by Y: X = 0: 0. 40
Reference numeral 3 denotes one line drawn by the acceleration function. Here, burst reading of data from the SDRAM 16 is performed in a maximum of 8 words (corresponding to 16 dots). Therefore, in the start point portion of the line 403, the mask area 40 on the start point side in the burst write
4 and the drawing area 40 on the starting point side in burst writing
5 is included. Reference numeral 406 denotes a writing area (16 dots) in which writing can be performed by one burst writing of a maximum of 8 words. Also, line 403
At the end, a drawing area 407 on the end point side in burst writing and a mask area 408 on the end point side in burst writing are included.

FIG. 4B is a diagram for explaining an address map of data stored in the SDRAM 16.

In the present embodiment, the SDRAM 16 has a structure in which one word is 32 bits and each word is represented by two dots. The lower 16 bits of one word are an even dot, and the upper 16 bits are an odd dot. I do. 411 represents the coordinates of the dots on the screen of the TFT liquid crystal display unit 20,
412 represents the structure of RGB data in one word. Here, R (red) is represented by 5 bits, G (green) is represented by 6 bits, and B (blue) is represented by 5 bits. 413 is S
4 shows actual row addresses and column addresses of the DRAM 16.

FIG. 3 is a flowchart showing processing by the CPU 11 and the acceleration module 12 of the liquid crystal display device 20 according to the first embodiment. Here, a case will be described where data for drawing the line 403 as shown in FIG. 4A is transferred to the SDRAM 16 and stored.

First, in step S301, in order to perform a process of writing an arbitrary line or graphic data to the SDRAM 16 which is a VRAM, the CPU 11 stores, in a register of the acceleration module 12, arbitrary color information of the graphic, The start point information on the display (here, the start address of the line 403, Y: X = 0: 5) and the drawing range information (here, Y: X = 0: 37) are written. Next, step S302
The CPU 11 instructs the acceleration module 12 to start line drawing.

In step S303, the acceleration module 12 instructed to start drawing in step S303, based on the given start point information (Y: X = 0: 5) on the screen, stores 8 words (16 words) in the SDRAM 16. Dot)
The address calculation for the first burst transfer in units is performed, and the raw (00) and column (0)
0) Calculate each value. Next, the process proceeds to step S304, in which the starting point information (Y: X = 0: 5) and the drawing range information (Y: X = 0: 3) in the XY directions on the given screen 401 are provided.
7), the starting point mask range 404 (= 5 dots) at the time of the first burst transfer and the starting point writing range 40
5 (= 11 dots) is calculated. Next, step S30
Go to 5 and start point information of line 403 (Y: X = 0: 5)
From the drawing range information (Y: X = 0: 37) of the line 403 on the given screen in the X and Y directions, the total number of burst transfers required to transfer the data (here, “3”) ) Is calculated. Next, the process proceeds to step S306, where the last burst is obtained from the start point information (Y: X = 0: 5) and the drawing range information (Y: X = 0: 37) in the X and Y directions on the given screen. End point mask range 408 at transfer (= 6
Then, the end point writing range 405 (= 10 dots) is calculated.

After the above calculation of the writing condition is completed,
Proceeding to step S307, the acceleration module 12 waits for a write permission command from the SDRAM arbiter 14. When the write permission signal is output, the process proceeds to step S308, where the address (0
From 0:00), three 8-word burst writes are executed.

At this time, the starting point mask range 40 shown in FIG.
4 is input to the data bus of the SDRAM 16, in order to mask this portion of data,
DQM0.1 (220) is set to the high level for three data (D0 to D2), and DQM2.3 (221) is set to the high level for two data (D0 to D1). This allows
Writing of the first 5 dots of data is masked and SD
Writing to the RAM 16 is stopped.

Similarly, at the time of writing data of a portion corresponding to the end point mask range 408 (here, 6 dots),
DQM0.1 (220) is converted to the last three data (D5 to D
7) Set DQM2.3 (221) to high level for 3 minutes
The high level is set for the data (D5 to D7).

At the time when all the data writing processes have been completed, the acceleration module 12
Output a processing end signal to the PU 11 (step S
309).

When the image data is stored in the SDRAM 16 in this manner, the data readout unit 17 responds to the count signal from the TFT timing controller 19 in accordance with the SDRA.
The data for one line of the TFT liquid crystal display unit 20 is read from M16 and stored in the asynchronous FIFO 18. The data from the FIFO 18 is output in response to a request from the TFT timing controller 19, sent to the TFT liquid crystal display unit 20 in synchronization with a display clock or a synchronization signal of the TFT liquid crystal display unit 20, and displayed there.

As described above, according to the first embodiment, display data can be transferred and stored in a VRAM (SDRAM) at high speed.

[Second Embodiment] In the first embodiment described above, line drawing with predetermined color information using the acceleration function has been described. However, this processing is repeated an arbitrary number of times under an arbitrary condition. It is possible to draw an arbitrary figure on the TFT liquid crystal display section 20.

FIG. 5 is a flowchart showing a drawing process in the liquid crystal display device according to the second embodiment of the present invention. The hardware configuration of the liquid crystal display device according to the second embodiment is the same as that of the first embodiment. And the description is omitted.

FIG. 6 is a view for explaining a drawing image which is an arbitrary figure.

In FIG. 5, first, in step S501,
From the CPU 11 to the acceleration module 12,
Various conditions such as coordinates and color information are set. Next, step S
In step 502, the CPU 11 issues a drawing start command to the acceleration module 12. Next, the process proceeds to step S503, where the acceleration module 1
2 to the SDRAM 16 to transfer and write image data by burst transfer. Next, the process proceeds to step S504, in which the acceleration module 12
Outputs a drawing end signal indicating the end of writing to the SDRAM 16, which is a VRAM. C which received this signal
In step S505, the PU 11 determines whether or not all drawing has been completed, and if not, returns to step S502 to perform the next line drawing process.

In FIG. 6, reference numerals 510 to 517 denote lines for setting drawing conditions from the CPU 11 when drawing an arbitrary figure. In order to draw the figure of FIG. 6, the CPU 11 can draw this figure only by drawing instructions eight times (for eight lines). That is, the CPU 11 can write the data corresponding to each of the lines 510 to 517 into the SDRAM 16 by one burst transfer only by setting each start point mask and end point mask.

As described above, according to the second embodiment, image data representing an arbitrary figure can be transferred to the SDRAM 16 and displayed.

[Third Embodiment] In the first embodiment described above, line drawing using burst transfer has been described, but a function of calculating a data write amount suitable for burst transfer among them is used. Can process font drawing at high speed.

FIG. 7 is a flowchart showing a drawing process in the liquid crystal display device according to the third embodiment of the present invention.

FIG. 8 is a diagram showing a 32 × 32 bit font pattern of the kanji character “ta”.

In FIG. 7, steps S601 to S60
Steps S30 to S6 in the first embodiment described above
This is the same processing as the processing in 1 to S306. Next, proceeding to step S607, the CPU 11 inputs the font map data to the acceleration module 12.
Next, the processing proceeds to step S608, where the acceleration module 12 determines that the input font map data is, for example, a 32-bit font “ta” and that the data bus is 32 bits, and that the first line 800
Font data in hexadecimal "ffffffff
c "h. When this value is converted to binary, “1111111
111111111111111111111110
0 ". Here, in the part where the data is “1”, the arbitrary color designated in step S601 is
Set to write to.

That is, when the start point information Y: X = 0: 0,
First burst transfer data (8 words: 16 dots)
FIG. 4 shows that the map data is "ffff" h
Addresses D0 to D7 of SDRAM 16 in (B)
Stores the color information specified in step S601. Next, the data at the time of the second burst transfer is “fff
c ”h, the SDRAM 16 in FIG.
In the addresses D0 to D6, the color information set in S601 is stored, and the portion of the address D7 is masked.
Thus, the top line 800 of the font shown in FIG.
Is completed. If the above process is repeated for each line and executed for 31 lines as in the second embodiment, the font data of “ta” is stored in the SDRAM 16 and displayed on the TFT liquid crystal display unit 20.

As described above, according to the third embodiment, there is an effect that font data such as kanji can be verse-transferred to the SDRAM, stored, and displayed.

[Fourth Embodiment] In the first embodiment described above, line drawing using burst transfer effectively has been described. However, a function of calculating a data write amount suitable for burst transfer therein is used. Thus, drawing of image data can be processed at higher speed. In this case, the acceleration module 12 receives the RGB data to be used for display by the data write amount from the CPU 11 and starts the write operation.

FIG. 9 is a flowchart showing processing by the CPU 11 and the acceleration module 12 in the liquid crystal display device according to Embodiment 4 of the present invention. Note that, also in the fourth embodiment, the hardware configuration of the liquid crystal display device is the same as that of the above-described first embodiment, and thus the description thereof will be omitted.

In FIG. 8, steps S801 to S80
6 correspond to steps S301 to S30 of the first embodiment.
Same as 6.

Next, in step S807, step S80
The amount of data received by the acceleration module 12 from the CPU 11 based on the starting point mask amount obtained in step 4 and the number of write dots for burst transfer obtained in the calculation process (=
Set the number of writing dots). Next, step S808
To start receiving the RGB data from the CPU 11. Next, the process advances to step S809 to determine whether RGB data for the number of write dots has been received. If not, the process returns to step S808 to receive the RGB data. If it is determined that RGB data for the number of write dots has been received, the process advances to step S810 to wait for a write enable command from the SDRAM arbiter 14. In step S810, when the write enable signal is output, the process proceeds to step S811 to start a process of writing to the SDRAM 16 by burst transfer. Then, in step S812, when the write processing by the first burst transfer is completed, the process proceeds to step S813, and it is determined whether a plurality of burst transfer times have been set and all of them have been completed. In step 813, it is determined that the burst transfer is necessary, and the process returns to the setting of the data amount in step 807, and the input of image data for the next burst transfer is started.

Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus including one device (for example, a copying machine, a facsimile machine, etc.) ) May be applied.

Another object of the present invention is to supply a storage medium (or a recording medium) in which program codes of software for realizing the functions of the above-described embodiments are recorded to a system or an apparatus, and to provide a computer (or a computer) of the system or the apparatus. This is also achieved by a CPU or MPU) reading and executing a program code stored in a storage medium. In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. When the computer executes the readout program codes, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instructions of the program codes. This also includes a case where some or all of the actual processing is performed and the functions of the above-described embodiments are realized by the processing.

Further, after the program code read from the storage medium is written into the memory provided in the function expansion card inserted into the computer or the function expansion unit connected to the computer, the program code is read based on the instruction of the program code. , The CPU provided in the function expansion card or the function expansion unit performs part or all of the actual processing,
The case where the function of the above-described embodiment is realized by the processing is also included.

As described above, according to this embodiment, in the drawing acceleration function of the display control device using the SDRAM as the VRAM, it is possible to perform the most efficient burst transfer writing while executing the line starting from an arbitrary dot. , Drawing of a figure in a designated color, font drawing, and image data drawing can be realized. This allows V
The time for writing the display data to the RAM can be greatly reduced.

Further, since the time required for the CPU to perform the drawing process can be greatly reduced, the throughput and operability can be improved by allocating the free CPU time to other processes.
Further, an effect such as a significant reduction in power consumption in the device can be expected.

[0061]

As described above, according to the present invention, display data can be efficiently transferred to a display memory and stored.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a liquid crystal display device according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating a liquid crystal display device according to the first embodiment;
5 is a timing chart illustrating timings of writing data to and reading data from a DRAM.

FIG. 3 is a flowchart showing a drawing process by a CPU and an acceleration module according to the first embodiment of the present invention.

FIG. 4 is a diagram showing display coordinates (A) on a display screen of a liquid crystal display unit according to the first embodiment and a data configuration of an SDRAM.

FIG. 5 is a flowchart showing a drawing process by a CPU and an acceleration module according to Embodiment 2 of the present invention.

FIG. 6 is a diagram illustrating an example of display data on a display screen of a liquid crystal display unit according to the second embodiment.

FIG. 7 is a flowchart showing a drawing process by a CPU and an acceleration module according to Embodiment 3 of the present invention.

FIG. 8 is a diagram illustrating an example of display data on a display screen of a liquid crystal display unit according to the third embodiment.

FIG. 9 is a flowchart showing a drawing process by a CPU and an acceleration module according to Embodiment 3 of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a conventional liquid crystal display device.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 5/00 550 G09G 5/00 550P 550T 550R 555J

Claims (6)

[Claims] A display data storage unit for storing display data; a data read control unit for sequentially reading display data stored in the display data storage unit and outputting the display data to a display unit; and a burst transfer in a predetermined data amount unit. Data transfer control for transferring display data to the display data storage means and storing the display data in the display data storage means, and prohibiting burst transfer of the display data in accordance with mask data for prohibiting data transfer in the burst transfer in the predetermined data amount unit. And a display control device. 2. The display data storage means according to claim 1, wherein said display data storage means includes a synchronous dynamic RAM.
3. The display control device according to 1. 3. The data transfer control unit: a unit that determines an address to be stored in the display data storage unit based on color information of the display data and display coordinates on a screen of the display unit; 2. The display control device according to claim 1, further comprising: a number setting unit that sets the number of times of burst transfer to the display data storage unit. 4. A display data storing step of storing display data in a display memory; and transferring and storing the display data to said display memory by burst transfer in a predetermined data amount unit, and further comprising: A data transfer control step of prohibiting the burst transfer of the display data in accordance with the mask data for prohibiting the data transfer in the burst transfer, and sequentially reading out the display data stored in the display data storing step and outputting the display data to the display unit. A data reading step. 5. The display control method according to claim 4, wherein the display memory includes a synchronous dynamic RAM. 6. In the data transfer control step, a step of determining an address to be stored in the display memory based on color information of the display data and display coordinates on a screen of the display unit; 5. The display control method according to claim 4, further comprising: a number setting step of setting a number of times of burst transfer to the display memory.