JP2000322044A - Display control device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute control of a display device formed by combination of plural display devices, by a single display control device. SOLUTION: In this display control device equipped with plural memories 192-195 for display corresponding respectively to plural display devices forming a display device, for providing received display information to a corresponding display device through each memory corresponding to its bank address, a memory control means 1915 for generating writing control signals WE(1)-WE(4) on each memory for diving the display information into corresponding each memory and writing it thereon, is installed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a display control device for a display device constituted by combining a plurality of display devices and a control method therefor.

[0002]

2. Description of the Related Art In recent years, with the improvement of computer performance,
The information handled by computers has changed from text-based to graphic-based, and the quality of graphics has recently been required. However, in a CRT (Cathode-Ray Tube) or a liquid crystal display device that is generally used as an information output device in an information processing system, the resolution is 100 DPI (Dot Per Inch) due to the difficulty of fine dot arrangement.
The image quality is clearly inferior to that of a printing device such as a printer device which realizes a resolution of 1000 DPI or more, since only a considerable resolution is realized.

In order to improve this point, a liquid crystal display device which realizes an image quality equivalent to a photograph (equivalent to 300 DPI) by combining a plurality of display devices has recently been developed. Conventionally, as control means of a display device realized by combining a plurality of display devices,
A display control device is provided for each of the combined display devices, and each display device is independently controlled.

[0004]

However, in the above conventional example, since the same number of display control devices are required to control a plurality of display devices, the occupied area and power consumption increase, and the component cost also increases. It will take more minutes.

The present invention has been made based on the above-described viewpoint, and has as its object to control a display device constituted by a combination of a plurality of display devices with one display control device. And

[0006]

In order to achieve this object, a display control device according to the present invention includes a plurality of display memories respectively corresponding to a plurality of display devices constituting a display device, and stores received display information. In accordance with the bank address, a display control device that supplies the display information to the corresponding display device via the respective memories via the respective memories includes a write control signal for each memory for distributing and writing the display information to the corresponding memories. It is characterized by comprising a memory control means for generating.

Further, according to the display control method of the present invention, the received display information is transmitted to a plurality of display memories respectively corresponding to a plurality of display devices constituting a display device in accordance with the bank address. In the display control method for supplying the display information to the display device, when the display information is distributed and written to each memory, the distribution is performed by a write control signal for each memory.

In the configuration of the present invention, when the received display information is written into each memory, the display information is distributed to each memory by a write control signal for each memory. Need not be received by a plurality of display control devices corresponding to each memory. That is, the display information is received by one display control device, and the display information is distributed to each memory when writing to each memory.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment of the present invention, display information distributed and written to each memory is simultaneously read out from each memory by a read control signal common to each memory and transferred to each display device. By controlling access to each memory in this manner, the update speed of the display content on each display device does not decrease. In addition, based on an address to which display information is to be written in any one of the memories and the bank address, a storage element to which display information is to be written, and a specific one of the storage elements constituting the plurality of memories. Generating position information (corresponding to the DRAM address MA <10: 0> in the embodiment) for designation, and generating and writing the write control signal for writing display information to each memory based on the position information Specify the address. The write control signal is generated by generating a selection signal for selecting a signal to be made valid as the write control signal. The selection signal can be generated, for example, by comparing the position information with a predetermined value and based on the result of the comparison. This predetermined value can be given from a host computer to which the device is connected.

[0010]

FIG. 1 is a block diagram of an entire information processing system including a display control device (display controller) according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a host C that controls the entire information processing system.
PU, 2 is a high-speed bus (PCI bus) having an address bus, data bus, control bus, etc., 6 is a host CP
It is a bridge that provides an interface between U1 and a high-speed bus (PCI bus) 2. Reference numeral 5 denotes a DRAM used as a main memory, which stores a control program executed by the host CPU 1 and is used as a work area when the host CPU 1 performs control processing. 3 is ISA
A medium speed bus such as a bus; 7 a bridge for connecting the high speed bus 2 and the medium speed bus 3; 4 a ROM for storing a program for performing initialization processing of the entire system; 19 a display device 20
Is a display controller, which is configured by a plurality of display devices.

Next, a portion connected to the medium speed bus 3 will be described. Reference numeral 11 denotes an I / O controller, which performs communication using a disk interface for the hard disk device 12 and the floppy disk device 13, a parallel interface used for controlling the printer device, and a public line or a dedicated line. And a serial interface used to control a communication modem for the communication. Reference numeral 16 denotes a keyboard (KBD) controller, which controls an interface between a keyboard 17 for inputting characters such as characters and numerals and the like, and a mouse 18 as a pointing device. Reference numeral 14 denotes a real-time clock, which also has a timer function for counting clocks and measuring time. 1
Reference numeral 5 denotes an audio subsystem, which inputs an audio signal from a microphone and outputs it to the medium speed bus 3, or outputs an audible signal to a speaker based on the signal from the medium speed bus 3.

In the information processing system having the above configuration, a user of the system generally performs an operation while responding to various information displayed on the display screen of the display device 20. That is, the information transmitted from the communication modem via the serial interface, the character and image information supplied from the hard disk 12, the floppy disk 13, the keyboard 17, the mouse 18, etc., the system ROM 4 and the main memory (DRAM) 5 The stored operation information related to the user's system operation is displayed on the display screen of the display device 20, and the user performs information editing and instructs the system while watching the display. Here, each of the above-described various devices and the like constitutes a display information supply unit for the display device 20.

Next, the configuration of the display controller 19 for controlling the display device 20 will be described. First, a conventional display controller will be described for comparison. FIG. 2 is a block diagram showing a configuration example when the display device 20 is controlled by a conventional display controller 291. In this example, four display devices 20
The display device 20 is constituted by 1 to 204. As shown in FIG.
It is controlled by an existing SVGA which is a display control circuit for RT. The display controller 291 has as many SVGAs as the number of display devices constituting the display device 20 (four in this example).
To 2914 are DRAM 29 as storage means for storing display information to be displayed on a corresponding display device.
15 to 2918 are connected. DRAM 2915-29
18 are generally inexpensive DRAMs (Dynami
cRandom Access Memory) is used.

According to the conventional display controller 291 having the above-described configuration, the display devices 201 to 204 constituting the display device 20 correspond to the respective SVs.
It will be controlled by GA2911-2914,
Display information for each of the SVGAs 2911 to 2914 is set from the host CPU 1 via the high-speed bus 2 for each SVGA. In FIG. 2, the display information set by the host CPU 1 or the SVGA register information read / written by the host CPU 1 is described so as to be individually set for each SVGA via the high-speed bus 2. Actually, these data are connected to the high-speed bus 2 via a common data bus signal line, and each SVGA obtains only necessary information by an address signal line on the high-speed bus 2.

Next, the configuration of the display controller in this embodiment will be described. FIG. 3 is a block diagram illustrating a configuration example of the display controller 19 in the present embodiment. As shown in the figure, the display controller 19 in the present embodiment is constituted by one SVGA 191, and the SVGA 191 has a DRAM 192 corresponding to each of the display devices 201 to 204 constituting the display device 20.
To 195 are connected. The display devices 201 to 204 constituting the display device 20 are controlled by a common control signal.
The display data read from M192 to 195 is supplied to each of the display devices 201 to 204. SVGA191
Will be described with reference to FIG. In the figure, the rewrite display data accessed by the host CPU 1 for writing in the display memory window area of the display controller 19 is transferred via the high-speed bus 2 and
It is temporarily stored in the IFO 1911. Bank address data for projecting the display memory window area to an arbitrary area of the DRAMs 192 to 195 is also transmitted to the high-speed bus 2.
Forwarded over. Commands from the host CPU 1 and control information such as the aforementioned bank address data are transferred in the form of register set data.
The register get data is transferred to the host CPU 1 in order to know the state of the SVGA 191 side. FIFO1
The register set data and display data stored in 911 are sequentially output, and set in each register in the bus interface unit 1912 and VGA 1916 according to the data. The VGA 1916 can know the bank address, its display data, and the control command according to the set state of these registers.

The VGA 1916 generates DRAM addresses in the DRAMs 192 to 195 corresponding to the display memory window area address and the bank address based on the address and the bank address.
Through the DRAMs 192 to 195. At this time, the display data to be rewritten is similarly transmitted to the DRAMs 192-1 through the memory interface unit 1915.
95. As a result, display data can be written to the DRAM address.

The SVGA 191 is further provided with a data manipulator 1913 and a graphic engine 1914 that perform an accelerator function. For example, if the host CPU 1
When data on the circle and its center and radius is set in the register 912 and drawing of the circle is instructed, the graphic engine 1914 generates the circle display data, and the data manipulator 1913 transmits this data via the memory interface unit 1915. DRAM 192-1
Write to 95.

Memory interface unit 1915
Corresponds to the DRAM address specified by the VGA 1916 or the data manipulator 1913,
The display data is written and read from and to the DRAMs 192 to 195, and refresh driving of the DRAMs 192 to 195 is performed. The display data read from the DRAMs 192 to 195 are temporarily stored in FIFOs 1917 to 1920, respectively.
And sent to the display device 20 in the order in which they are stored.

Next, the memory interface unit 19
The operation of controlling the DRAMs 192 to 195 with the use of No. 15 will be described. FIG. 5 is a timing chart showing an operation when the memory interface unit 1915 writes display data to the DRAMs 192 to 195. The DRAMs 192 to 195 are arranged in a row (row: Ro).
w) Address strobe signal RAS *, row (column:
Column) address strobe signal CAS *, and an address bus signal MA (0 to 10 bits in this example) for inputting address information of a column address and a row address.
Up to 11 bits wide), DRAM 19
Signals WE * and D indicating instructions to write data to 2-195
A signal OE * indicating a data read instruction from RAMs 192 to 195, and a bidirectional data bus signal MD for transmitting data to be written or read to DRAMs 192 to 195 (in this example, the data bus width of each DRAM is 16 bits from 0 bits to 15 bits). * Indicates a low active signal. The expression <a: b> in the signals MA and MD indicates signals from a to b,
For example, MA <10: 0> is 1 from MA0 to MA10.
Indicates that the signal is composed of one signal.

Here, the signal WE * is WE (1) *-W
Each of the DRAMs 192 corresponding to the display devices 201 to 204 configuring the display device 20 as E (4) *
~ 195, and the signal OE * is
Commonly used for all 195. In addition, since one DRAM has a bus width of 16 bits, the signal MD is operated by the memory interface unit 1915 as a 64-bit bus width including the signals MD for all the DRAMs 192 to 195. MD <15: 0> in FIG.
Is the data bus for the DRAM 192, MD <31: 1
6> is a data bus for the DRAM 193, MD <4
7:32> is the data bus for DRAM 194, MD
<63:48> is a data bus for the DRAM 195.

First, the column (RA) is placed on the signal MA <10: 0>.
S) The address is output, and when the output of the column (RAS) address is stabilized, the column (RAS) address is
The strobe signal RAS * for storing the data changes to low level "0". Next, a row (CAS) address is output on signals MA <10: 0>, and when the output of the row (CAS) address is stabilized, the row (CAS) address is changed to D.
The strobe signal CAS * to be stored in the RAM changes to low level "0". In a DRAM, storage elements are arranged in a matrix of columns and rows, and a column (RAS) determined at the time of falling of signals RAS * and CAS *.
The address and row (CAS) address determine the storage element to be operated.

Prior to the fall of signal CAS *, DR
Whether a write operation or a read operation to AM is performed is indicated by a WE * signal or an OE * signal. Since the example of FIG. 5 shows the timing of the write operation to the DRAM, the signal WE * changes to low level “0”. In the first access cycle, the signal WE
(1) Since * changes to low level “0”, DR
A write operation to AM 192 is performed, and the write data at that time is output onto MD <15: 0>. In the next access cycle, as in the first access cycle, the column (RA
S) Address and row (CAS) address are determined. In the access cycle here, the signal WE (2) *
Has changed to the low level “0”.
3 is performed, and the write data at that time is output on MD <31:16>. Although not shown in FIG. 5, the write operation to the DRAM 194 and the DRAM 195 is also performed by the signals WE (3) * and MD <47: 3, respectively.
2> or WE (4) * and MD <63:48>.

Next, the memory interface unit 19
The operation of reading display data from the DRAMs 192 to 195 by using the F.15 will be described with reference to the timing chart of FIG. Determination of the column (RAS) address and row (CAS) address of the DRAM is performed by signals RAS * and CAS *, as in the write operation.
Prior to the fall of the signal CAS *, the signal OE * is changed to low level "0", and all the DRAMs 192 to 19
5 indicates a display data read operation.
From the DRAMs 192 to 195, the output of the display data is started when the column (RAS) address and the row (CAS) address are determined by the fall of the signal CAS *, and the display is performed while the signal OE * is at the low level “0”. Data continues to be output.

Next, the memory interface unit 19
15, the operation of selecting the write signals WE (1) * to WE (4) * for each of the DRAMs 192 to 195 will be described. FIG. 7 shows the configuration of the display device 20. Display device 2
0 has a resolution of 512 pixels in the vertical direction and 1024 pixels in the horizontal direction,
When they are combined, 1024
Pixels have a resolution of 2048 pixels in the horizontal direction. Also,
The vertical direction of each display panel corresponds to the row of DRAMs (RA
S) address, and the horizontal direction corresponds to a row (CAS) address. “512” corresponding to the number of pixels in the vertical direction
Is represented as “200h” in hexadecimal, and “1024” corresponding to the number of pixels in the horizontal direction is represented as “40” in hexadecimal.
Therefore, the column (RAS) addresses of the DRAMs 192 to 195 are changed from “0” to “1ff”.
h ”corresponds to the DRAM 192 or the DRAM 193, and“ 200h ”to“ 3ffh ”corresponds to the DRAM 19
4 or the DRAM 195. Line (C
As for the AS) address, "0" to "3ffh" correspond to the DRAM 192 or the DRAM 194,
"400h" to "7ffh" correspond to the DRAM 193 or the DRAM 195. That is,
Address bus MA <10 to DRAMs 192-195:
0> on the column (RAS) address and row (CA)
S), the column (RAS) address is “0”
9th bit from “1ffh” to “1ffh”, and the 10th bit is the DRAM 192 and DRAM 193 or DRAM
194 and DRAM 195 are used. Line (CA
S) For the address, 10 bits from "0" to "3ffh" are output, and the 11th bit is
And DRAM194 or DRAM193 and DRAM1
Used to select 95.

FIG. 8 shows the memory interface unit 1
At 915, a configuration of a circuit for generating signals WE1SEL, WE2SEL, WE3SEL and WE4SEL for selecting the write signals WE (1) * to WE (4) * of the DRAMs 192 to 195 is shown. In the figure, 151 and 152 are inverter elements for inverting the logic of a signal, and 153 to 156 are 2-input AND elements.

In this circuit, the column (RAS) address 1
Each signal WE1SEL, WE2SEL, WE3 is determined by a combination of a signal Raddr9 indicating the 0th bit and a signal Caddr10 indicating the 11th bit of the row (CAS) address.
SEL and WH4SEL are generated. Each signal WE
1SEL, WE2SEL, WF3SEL and WE4S
EL represents the write signals WE (1) * to WE (4) *, respectively.
And the memory interface unit 191
5, when the write operation to the DRAMs 192 to 195 is performed, at the timing of outputting the signal WE *, the signal corresponding to the signal which has changed to the high level "1" among the signals WE1SEL, WE2SEL, WE3SEL and WE4SEL. WE * is output as a low level “0”.

The display data written to the DRAMs 192 to 195 in this manner is read out from the DRAMs 192 to 195 by the signal OE * in the DRAM 1
It is read out simultaneously from 92 to 195. DRAM 192
In the read operation from .about.195, since the signal OE * and the address bus MA <10: 0> are common to each DRAM, the position of the storage element read for each DRAM is also the same. The display data read from the DRAMs 192 to 195 are transferred to the display device 20 via the FIFOs 1917 to 1920, respectively.

FIG. 9 is a timing chart showing an operation of transferring display data read from the DRAMs 192 to 195 to the display device 20. The display data read from the DRAMs 192 to 195 and stored in the FIFOs 1917 to 1920 is PEN indicating that the display data is valid.
While the ABLE signal is at the high level “1”, the FIFOs 1917 to 1919 are stored in the order stored in synchronization with the PCLK signal.
20 and the display data (1) <1
5: 0> to (4) <15: 0>.

In this embodiment, the display device 20 is composed of four display devices 201 to 204, and storage means DRAM 192 to 195 for storing display information to be displayed on each display device are connected to the SVGA 191. However, the number of display devices constituting the display device 20 is four.
The number of sheets is not limited to the number of sheets, and the number of sheets may be an arbitrary number, and the SVGA may have a storage unit corresponding to each number.

[Second Embodiment] In the first embodiment, a display device constituted by a combination of a plurality of display devices is controlled by one display control device and storage means corresponding to each display device. The number of pixels in the vertical and horizontal directions is set to 512 and 1024, respectively, so as to be well-divided in hexadecimal notation.
A write signal to the storage means corresponding to each display device is generated by a combination of the upper bits of the (AS) address and the row (CAS) address. However, even if the number of pixels in each of the vertical and horizontal directions of each display device is an arbitrary value, a circuit for selecting a write signal to the storage means corresponding to each display device includes a column (RAS) address and a row (CAS). It is possible to cope with this by using a circuit for comparing the magnitudes, instead of using a combination of the upper bits of the address. Therefore, in this embodiment, the circuit for selecting the write signal to the storage means corresponding to each display device is configured by a circuit for comparing the magnitude.

In this embodiment, the display device 20 has the configuration shown in FIG. That is, the display devices 201 to 204
Has a resolution of 768 pixels in the vertical direction and 1280 pixels in the horizontal direction, and when combined, has a resolution of 1536 pixels in the vertical direction and 2560 pixels in the horizontal direction. The vertical direction of each display panel corresponds to the column (RAS) address of the corresponding DRAM, and the horizontal direction corresponds to the row (CAS) address. “7” corresponding to the number of pixels in the vertical direction
68 is “300h” when expressed in hexadecimal, and 1280 corresponding to the number of pixels in the horizontal direction is “5” when expressed in hexadecimal.
00h, that is, with respect to the column (RAS) address of the DRAM, DRA is from "0" to "2ffh".
"300h" corresponding to M192 or DRAM193
From "5ffh" to DRAM 194 or DRAM
195. For the row (CAS) address:
“0” to “4ffh” correspond to the DRAM 192 or D
Corresponding to the RAM 194, "500h" to "9ffh"
Up to correspond to the DRAM 193 or the DRAM 195.

The memory interface unit 1915 has the structure shown in FIG.
To 195 each of the write signals WE (1) * to WE
(4) Signals WE1SEL, WE2S for selecting *
Generate EL, WE3SEL and WE4SEL. In the figure, 157 and 158 compare the magnitude of the two input signals a and b, and when the signal a is smaller than b, output the signal a <b as a high level “1”, and output the signal a b
Or when the signal a is larger than b, the comparator a outputs the signal a ≧ b as a high level “1”.

In the comparator 157, the signal Raddr <10: 0> corresponding to the column (RAS) address is set to a fixed value "3".
00h ", and the line (CAS) is output from the comparator 158.
The signal Caddr <11: 0> corresponding to the address is compared with a fixed value “500h”. Comparator 157 and comparator 15
8, the signals WE1SEL, WE2S
EL, WE3SEL and WE4SEL are generated.
The signals WE1SEL, WE2SEL, WE3SEL and WE4SEL are the write signals WE (1) * to WE, respectively.
(4) *, and when the memory interface unit 1915 performs a write operation to the DRAMs 192 to 195, the signals WE1SEL, WE2SEL, WE3SEL,
Among the WE4SELs, a signal WE * corresponding to a signal that has changed to a high level “1” is output as a low level “0”.

Here, all bits of the signal Raddr <10: 0> corresponding to the column (RAS) address and the signal Caddr <11: 0> corresponding to the row (CAS) address are compared. Alternatively, the comparison may be made only for the upper few bits that can be determined by the storage means corresponding to each display device.

[Third Embodiment] In the second embodiment, a display device constituted by a combination of a plurality of display devices is controlled by one display control device and storage means corresponding to each display device. By configuring a circuit for selecting a write signal to the storage means corresponding to each display device with a circuit for comparing the magnitudes, the number of pixels in the vertical direction and the horizontal direction of each display device can be any value. In addition, a value to be compared with a signal corresponding to a column (RAS) address and a signal corresponding to a row (CAS) address is a fixed value. On the other hand, in the present embodiment, the value to be compared with the signal corresponding to the column (RAS) address and the signal corresponding to the row (CAS) address is M
It can be set arbitrarily by a programming device such as a PU.

That is, in this embodiment, the display controller 19 has the configuration shown in FIG. 12, and the memory interface unit 1915 has the configuration shown in FIG.
(1) * Signal WE1S for selecting WE (4) *
EL, WE2SEL, WE3SEL and WE4SEL
Generate As means for setting a value to be compared with a signal corresponding to a column (RAS) address and a signal corresponding to a row (CAS) address, a microprocessor (MPU) 1
96 is used.

In the first embodiment, the signal Raddr corresponding to the column (RAS) address is a 10-bit width signal from 0 to 9 bits, and the signal Caddr corresponding to the row (CAS) address is changed from the 0 bit to 10 bits. In the second embodiment, a signal having a width of 11 bits up to the
S) The signal Raddr corresponding to the address was a 11-bit width signal from 0 to 10 bits, and the signal Caddr corresponding to the row (CAS) address was a 12-bit width signal from 0 to 11 bits. In the embodiment, the signal Raddr corresponding to the column (RAS) address is used.
And a signal Caddr corresponding to a row (CAS) address
Are 12-bit signals from 0 bits to 11 bits, and writing to each of the DRAMs 192 to 195 can be freely set beyond the number of pixels of each display device constituting the display device.

Thus, the display content of each display device constituting the display device is not only a continuous display among the display devices, but also a signal and a row (CAS) corresponding to a column (RAS) address set by the MPU 196. )
An arbitrary space can be displayed according to the value to be compared with the signal corresponding to the address.

The MPU 196 receives a signal Raddr <11: 0> corresponding to a column (RAS) address and a signal Caddr <11: corresponding to a row (CAS) address in the form of a register set from the host CPU 1 via the high-speed bus 2.
0>, the values are used as the signal Rcomp and the signal Ccomp as SVGA, respectively.
191. Signal R output from MPU 196
The comp and the signal Ccomp are respectively input to the comparator b 157 and the input b of the comparator 158 of the memory interface unit 1915 in the SVGA 191, and the signal Raddr <11 corresponding to the column (RAS) address:
0> and a signal Cad corresponding to the row (CAS) address
dr <11: 0>, and the comparator 157 and the comparator 1
58, the signals WE1SEL, WE2
SEL, WE3SEL and WE4SEL are generated. The signals WE1SEL, WE2SEL, WE3SEL and WE4SEL are respectively write signals WE (1) * to
WE (4) *, and when the memory interface unit 1915 performs a write operation to the DRAMs 192 to 195, at the timing of outputting the signal WE *, the signals WE1SEL, WE2SEL, and WE3SE are output.
Out of L and WE4SEL, the signal WE * corresponding to the signal changing to the high level "1" is the low level "0".
Will be output as

According to this embodiment, a signal Raddr <11: 0> corresponding to a column (RAS) address and a signal Caddr <11: 0> corresponding to a row (CAS) address are compared by a programming device such as an MPU. Values can be set arbitrarily, so that the display content on each display device of a display device composed of a combination of a plurality of display devices is not limited to a continuous display between the display devices, According to the instructions,
Arbitrary space can be displayed, and the display area can be expanded.

[0041]

As described above, according to the present invention, the display information is distributed to each memory by the write control signal for each memory, so that a display device composed of a plurality of display devices is provided. It can be controlled by one display control device. Further, since the display information is simultaneously read from each memory by a read control signal common to each memory, each display device can be controlled without lowering the update speed of the display content of each display device.

[Brief description of the drawings]

FIG. 1 is a block diagram of an entire information processing system including a display control device (display controller) according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a conventional display controller for a display device including a plurality of display devices.

FIG. 3 is a block diagram showing a configuration of a display controller in the system of FIG.

FIG. 4 is a block diagram of the display controller of FIG. 3;
It is a block diagram which shows the example of a structure of VGA.

5 is a timing chart showing a write operation to a DRAM by the SVGA of FIG. 4;

FIG. 6 is a timing chart showing a read operation from a DRAM by the SVGA of FIG. 4;

FIG. 7 is a configuration diagram showing a configuration of a display device in the system of FIG. 1;

8 is a circuit diagram showing a circuit for generating a selection signal in the memory interface unit of the SVGA of FIG.

9 is a timing chart showing an operation of transferring data read from a DRAM by the SVGA of FIG. 4 to a display device.

FIG. 10 is a configuration diagram illustrating a configuration of a display device according to a second embodiment of the present invention.

FIG. 11 is a circuit diagram showing a circuit for generating a selection signal in the memory interface unit of the second embodiment.

FIG. 12 is a block diagram illustrating a configuration of a display controller for a display device including a plurality of display devices according to a third embodiment of the present invention.

13 is a circuit diagram showing a circuit for generating a selection signal in a memory interface of the display controller of FIG.

[Explanation of symbols]

1: host CPU, 2: high speed bus, 3: medium speed bus, 4:
System ROM, 5,192-195,2915-29
18: DRAM, 6, 7: bridge, 11: I / O controller, 12: HDD, 13: FDD, 14: RT
C, 15: audio subsystem, 16: keyboard controller, 17: keyboard, 18: mouse, 1
9, 291: display controller, 20: display device, 201, 202, 203, 204: display device,
191, 291-11: SVGA, 2911, 1
917 to 1920: FIFO, 1912: bus interface unit, 1913: data manipulator, 1
914: graphic engine, 1915: memory interface unit, 1916: VGA, 151, 15
2: Inverter, 153 to 156: AND element, 15
7, 158: comparator, 196: MPU.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/36 G09G 3/36 F-term (Reference) 2H093 NC21 NC29 NC50 ND60 5C006 AF06 BB11 FA51 5C080 AA10 BB05 DD07 DD27 GG12 GG15 GG17 JJ01 JJ02 JJ03 JJ04 5C082 AA34 AA36 BD07 DA53 DA63 DA76 DA87 MM07 MM10

Claims (10)

[Claims] 1. A display device comprising a plurality of display memories respectively corresponding to a plurality of display devices constituting a display device, wherein received display information is transmitted via each memory in accordance with the bank address of the corresponding display device. A display control apparatus for supplying to a device, wherein the display control apparatus includes memory control means for generating a write control signal for each memory for distributing and writing the display information to each corresponding memory. 2. The memory control means according to claim 1, wherein said memory control means generates a read control signal common to each memory for simultaneously reading from said memories in order to transfer display information distributed and written to each memory to each display device. The display control device according to claim 1, wherein: 3. A storage element to which said display information is to be written, based on an address to which said display information is to be written in any one of said memories and said bank address, among storage elements constituting said plurality of memories. Means for generating position information for designating a specific one of the above. Based on the position information, the memory control means generates the write control signal for writing the display information to each memory and a write address. The display control device according to claim 1, wherein the display control device is configured to specify the following. 4. The memory control means includes a selection means for generating a selection signal for generating the write control signal for each memory by selecting an effective write control signal. The display control device according to claim 1. 5. The storage device according to claim 1, wherein the selecting unit is configured to store position information and a predetermined value for designating a specific one of the storage elements constituting the plurality of memories. The display control device according to claim 4, further comprising a comparison unit configured to generate the selection signal based on a result of the comparison. 6. The display control device according to claim 5, wherein the predetermined value is provided from a host computer connected to the device. 7. A display for supplying received display information to a corresponding display device via a plurality of display memories respectively corresponding to a plurality of display devices constituting a display device according to the bank address. In the control method, when distributing and writing the display information to each memory, the distributing is performed by a write control signal for each memory. 8. The display control according to claim 7, wherein display information distributed and written to each memory is simultaneously read out from each memory by a read control signal common to each memory and transferred to each display device. Method. 9. A write control signal for each memory,
The display control method according to claim 7, wherein the write control signal is generated by generating a selection signal for selecting a valid write control signal. 10. A method for generating the selection signal based on a result of comparing positional information for designating a specific one of storage elements constituting the plurality of memories with a predetermined value, and based on a result of the comparison. The display control method according to claim 9, wherein: