JPH11109937A - Display controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a shared memory so as to be used by giving priority to CPU access over the access of a display refresh in the case a program is needed to be operated at high speed like in a printing in a system in which the shared memory is used as a main RAM and an RAM for display. SOLUTION: When a CPU performs a processing in which it is needed to perform access to a VRAM at high speed, it transmits a display refresh stopping signal 68 to the VRAM access cycle generating part 46 of a display control part. When the part 46 receives the display refresh stopping signal 68, the part outputs a selection signal 50 selecting a CPU address A to a selector 52 and, consequently, a display refresh is made so as not to be performed. That is, CPU addresses are made so as to be supplied from the selector 52 to the VRAM and CPU access is continuously performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device for controlling display of data on a display device.

[0002]

2. Description of the Related Art In a conventional display control device, a main R
In a system that uses the AM and the display RAM in common,
A method called cycle stealing in which CPU access to the memory is performed between display refreshes in which display data is written to a memory and the written display data is sequentially read and displayed on a display device has been used.

[0003]

In the conventional display control device, the CPU access is performed between display refreshes as described above. Therefore, the RAM can be used by giving priority to the display refresh access over the CPU access. Was like that.

For this reason, even when the program must be operated at a high speed such as printing, there is a problem that the CPU access is not prioritized and the programmer processing cannot be performed in time.

Therefore, in order to operate the printing process at high speed, it is necessary to provide a special circuit or the like, and there is a problem that the circuit scale becomes large. SUMMARY OF THE INVENTION An object of the present invention is to provide a system that uses a shared memory as a main RAM and a display RAM when a program must be operated at a high speed, such as printing, by giving priority to CPU access over display refresh access. Is to be able to use

[0006]

Means of the present invention are as follows. The memory stores display data and is shared as a main RAM of the CPU. The selection means alternately selects access for display refresh processing for sequentially writing display data to the memory and sequentially reading the written display data and displaying the display data on a display device, and access from the CPU to the memory. Do. When the CPU performs a predetermined process that requires continuous access to the memory, the selection control unit causes the selection unit to perform an alternate selection between the access for the display refresh process and the access from the CPU. , Only the access from the CPU is selected.

The operation of the means of the present invention is as follows. Display data is stored and the main RA of the CPU is stored.
When the CPU executes predetermined processing that requires continuous access to the memory shared as M, the selection control means writes display data to the memory, sequentially reads out the written display data, and displays the display data. By controlling a selection means for alternately selecting access for display refresh processing to be displayed on the device and access to the memory from the CPU, the access between the display refresh processing and the access from the CPU is controlled. Instead of the alternate selection, only access from the CPU is selected.

Therefore, when a program must be operated at a high speed such as printing, the shared memory can be used with priority given to CPU access over display refresh access.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described.
This will be described with reference to FIGS. FIG. 1 is a diagram showing a configuration of a display data control unit as an embodiment of a display control device of the present invention and an information processing device such as a personal computer to which the display data control unit is applied.

[0010] Reference numeral 10 in the figure denotes a CPU as a control unit for controlling the entire information processing apparatus. Reference numeral 12 denotes an input device such as a keyboard and a mouse, and 14 denotes a printing device such as a printer. Reference numeral 16 denotes a storage device such as a hard disk or a ROM in which an operation processing program and data of the information processing device executed by the CPU 10 are stored in advance. Reference numeral 18 denotes a storage medium such as a floppy disk or an optical (magnetic) disk which is mounted on the information processing apparatus and supplies programs and data stored in the storage device.
Reference numeral 20 denotes a communication line (wired or wireless) for transferring programs and data stored in the storage device.

Reference numeral 22 denotes a display unit such as a CRT or a liquid crystal display. Reference numeral 24 is used as a display memory in which display data displayed on the display unit 22 is written, and as a main RAM of the CPU 10 such as a document memory. Is also used VRAM. 26 is this VRAM 24
A display data control unit that controls access to
Reference numeral 28 denotes a color pallet RAM for storing color display data.

The display data control unit 26 is connected to the CPU 10 via a data bus 30 and a control bus 32. CP
U10 transmits display data such as line drawing data and character data to the display data control unit 26 via the data bus 30.
And outputs various control signals such as a transfer start address to the display data control unit 26 via the control bus 32.

The display data control unit 26 is a VRAM
The display data controller 26 is connected to the VRAM 24 by an address bus 34 and a data bus 36. The display data control unit 26 addresses and expands the display data input from the CPU 10 in the VRAM 24, and sequentially displays the display data expanded in the VRAM 24. It is read out and output to the display unit 22. The display unit 22 and the display data control unit 26 are connected by a data bus 38 and a control bus 40. The display data control unit 26 is a VRAM
The display data read from 24 is output to the display unit 22 together with the control signal, and the display unit 22 outputs the display data.

Such a display data control unit 26 is provided in FIG.
The circuit configuration is as shown in FIG. That is, the display refresh controller 42 controls the display refresh address generator 44 by a control signal provided from the CPU 10 via the control bus 32. The VRAM access cycle generator 46 sends a select signal 50 for selecting either the CPU address A given from the CPU 10 via the address bus 48 or the output B from the display refresh address generator 44 to the selector 52. Output. Thus, an address is given from the selector 52 to the VRAM 24 via the address bus 34 in a cycle as shown in the upper part of FIG. 3A, and cycle stealing is performed.

On the other hand, the selector 54 receives one of the input data from the VRAM 24 via the data bus 36 and the input data from the color pallet RAM 28 via the data bus 56 to the CPU 10 via the data bus 30.
To allow the CPU 10 to read the contents of the VRAM 24 and the color palette RAM 28.

As shown in FIG. 3B, the fixed display control unit 58 sets the address where the display data is stored to the selector 60 when the area on the display is to display the character, as shown in FIG. By outputting 62 and outputting the select signal 64, the address can be selected and output to the color palette RAM 28 via the address bus 66. When writing color data to the color pallet RAM 28 according to the settings of the CPU 10, BIT (bits) 1 to 8 of the CPU address bus 48 are used.
Is output to the selector 60. The color palette RAM 28 has 256 words x
It is a 24-bit RAM, and the color of each 8 bits of RGB is 2
56 types of display can be performed.

Next, the operation in such a configuration will be described with reference to FIG.
This will be described with reference to the flowchart of FIG. First,
The CPU 10 determines whether or not to perform a process that needs to access the VRAM 24 at high speed, such as printing (step S10). When printing is not performed, normal display is performed, and the display data control unit 26 performs normal cycle stealing.

That is, the display data control unit 26 sets the address output from the display refresh address generation unit 42 to V
The display data is read to the RAM 24, and the display data is read by cycle stealing with the CPU address.
2 is displayed on the screen. At this time, the color palette RA
Since M28 is used on a 24-bit bus, it is accessed in units of double words, so only 24 bits out of 32 bits are used.

On the other hand, when it is determined in step S10 that printing is being performed, the CPU 10 executes the VRAM access cycle generation unit 46 of the display data control unit 26.
, A display refresh stop signal 68 is transmitted (step S20).

When receiving the display refresh stop signal 68, the VRAM access cycle generation unit 46 of the display data control unit 26 outputs a select signal 50 for selecting the CPU address A to the selector 52. Will not be refused. That is, the selector 5
2, the CPU address is supplied to the VRAM 24, and as shown in the lower part of FIG.
Access is performed continuously.

In this case, the CPU 10 causes the fixed display control unit 58 to output a select signal for selecting 0 from BIT7 of the CPU address, and writes an arbitrary character to be displayed in the color palette RAM 28. At this time, 16
Access is performed in bit units, and a 256 word × 24 bit RAM is used in 256 word × 16 bit. Further, the display position to be displayed on the display screen is set in the fixed display control unit 58. The fixed display control unit 58 includes:
When the set display position is reached, the count-up of the address is started and is output to the selector 60, and the select signal 64 for selecting the address is output. Thus, in the set fixed display area, the data of the character to be displayed is output from the color palette RAM 28. In addition, the fixed display control unit 58 controls the color palette RAM 28 in the set fixed display area.
Is output to the color display control circuit 70,
In other areas, the color data set by the CPU 10 is output and displayed.

In the above description, printing has been described as an example of processing that needs to access the VRAM 24 at high speed. However, it is needless to say that other processing such as scanner input and calculation may be performed.

[0023]

According to the first aspect of the present invention, the main RAM
In a system using a shared memory as a display RAM, when a program must be operated at a high speed such as printing, the shared memory can be used with priority given to CPU access over display refresh access. That is, the shared memory (VR) for display refresh
AM) Since the setting for not performing the access can be performed, there is an effect that the VRAM can be accessed at a high distance.

According to the second aspect of the present invention, the number of characters and the background color can be arbitrarily set in the set area so that the user can grasp the situation without performing display refresh. There is an effect that can be.

According to the third aspect of the present invention, the color pallet RAM can be used as a memory for storing the display data of the fixed screen, so that it can be realized with a small number of circuits.

According to the fourth aspect of the invention, the number of bits when used as a color palette RAM and the number of bits when used as a RAM for storing fixed-screen character data can be used with different bit numbers. By
There is an advantage that the use of software is improved and the display speed is improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a display data control unit as an embodiment of a display control device of the present invention and an information processing device such as a personal computer to which the display data control unit is applied.

FIG. 2 is a diagram illustrating a configuration of a display data control unit in FIG. 1;

3A is a diagram showing respective timings in a cycle stealing process of the VRAM and a VRAM high-speed access in FIG. 1, and FIG. 3B is a diagram showing a fixed screen display;
(C) is a flowchart for explaining the operation of the embodiment.

[Explanation of symbols]

 Reference Signs List 10 CPU 12 input device 14 printing device 16 storage device 18 storage medium 20 communication line 22 display unit 24 VRAM 26 display data control unit 28 color pallet RAM 30, 36, 38, 56 data bus 32, 40 control bus 34, 48, 66 Address bus 42 Display refresh controller 44 Display refresh address generator 46 VRAM access cycle generator 50, 64 Select signal 52, 54, 60 Selector 58 Fixed display controller 62 Address 68 Display refresh stop signal 70 Color display control circuit

Claims (4)

[Claims] 1. A memory which stores display data and is shared as a main RAM of a CPU, and a display refresh process for writing the display data to the memory, sequentially reading the written display data, and displaying the read display data on a display device. Selecting means for alternately selecting access to the memory and access from the CPU to the memory; and displaying the display on the selecting means when the CPU executes a predetermined process requiring continuous access to the memory. A selection control means for selecting only access from the CPU instead of alternate selection between access for refresh processing and access from the CPU. 2. The apparatus according to claim 1, further comprising: fixed display means for displaying an arbitrary character string at a set display position on the display and displaying a set background color in a portion other than the display position. 2. The display control device according to claim 1, wherein when the selection unit selects only access from the CPU, the fixed display unit displays an arbitrary character string and a background color. 3. The display control device according to claim 2, wherein said fixed display means uses a color pallet RAM as a memory for storing said arbitrary display data. 4. The data bus of the color pallet RAM can access different numbers of bits when used as a color pallet RAM and when used for storing fixed display data. The display control device according to claim 3, wherein: