JPH0535209A - Divided screen driving system for liquid crystal display device - Google Patents

Abstract

PURPOSE:To drive a liquid crystal display device by a frame memory whose capacity is a half as large as the number of picture elements of one screen. CONSTITUTION:This driving system is equipped with the frame memory 1 whose capacity is a half as large as the number of picture elements of one screen, a memory address generation part 4, a memory control signal generation part 8, and a data control part 5, which includes a display data holding part 1 (10) for holding data read out of the frame memory 1 and a display data holding part 2 (11) for holding inputted display data; and the data control part 5 reads the data of one divided screen (3A) out of the frame memory 1 and holds the data, and inputs and holds the display data of the other divided screen (3B), and while the inputted display data are stored in the addresses of the frame memory 1 where the data are read out, the read display data and inputted display data are outputted together.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a screen division driving system of a liquid crystal display device for inputting CRT video data and displaying a still image on a liquid crystal display screen divided into two.

[0002]

2. Description of the Related Art Conventionally, when CRT video data is input and displayed on a liquid crystal screen, a memory having a capacity equal to the number of display pixels on one screen has been used.

FIG. 5 is an explanatory diagram of a conventional technique. Figure (a)
Shows a conventional device configuration, which is a device configuration for inputting a CRT video signal and displaying it on a vertically divided liquid crystal screen.

In the figure, reference numeral 100 denotes a frame monitoring unit, which monitors a frame state and controls a frame memory on the basis of a synchronizing signal of video data, and a memory address generating unit 103 and a memory control signal generating unit 102. ，
It manages the operation of the data control unit 112 (both will be described later). Reference numeral 101 denotes a data control unit that reads out data on an addressed frame memory based on a signal from the frame monitoring unit 100 and outputs it as display data, and inputs the input video data to an addressed position. It is something to write. A memory control signal generator 102 performs frame memory control such as output enable and chip select based on a signal from the frame monitor 100. Reference numeral 103 denotes a memory address generator, which generates write and read addresses of the frame memory based on a signal from the frame monitor 100. A frame memory 104 stores display data of pixels for one screen. A driving unit 105 drives the liquid crystal display screen for the display data output from the data control unit 101. Reference numeral 106 denotes a liquid crystal display screen, which is divided into upper and lower parts and displays the upper screen data and the lower screen data at the same time.

Reference numeral 110 is a write address counter, and 11
Reference numeral 1 is a read address counter, 112 is an upper screen data holding unit, 113 is a lower screen data holding unit, and 114 is a write data holding unit.

FIG. 1B is a diagram showing a storage state of the frame memory. In the figure, 104 is a frame memory. The figure shows the storage state of the frame memory in the case of a 400-line liquid crystal screen, and conventionally, pixel data for one display screen was stored in the frame memory.

The operation of the configuration shown in FIG. 1A will be described. The frame monitoring unit 100 recognizes which line of video data is currently input based on the synchronization signal and generates a signal for controlling the data control unit 101, the memory control signal generation unit 102, and the memory address generation unit 103. To do.

The memory address generator 103 generates a write or read address of the frame memory by the write address counter 110 and the read address counter 111 based on the signal from the frame monitoring unit 100. The write address is sequentially designated from the leftmost digit to the rightmost digit in the line, and the line selection is sequentially designated from 1 line to 400 lines. The upper and lower screens are alternately specified as the read addresses, and the screens are sequentially specified from the highest line to the lowest line for each screen, and are specified sequentially from the leftmost digit to the rightmost digit in each line. To be done.

The memory control signal generator 102 generates a control signal for output enable, input enable, chip select, etc. based on a signal from the frame monitor 100, and controls or writes video data to the frame memory. Control to read the data that is stored.

The data control unit 101 reads out the addressed data in the frame memory and holds it in the upper screen data holding unit 112 and the lower screen data holding unit 113. Then, each display data is output to the drive unit 105 of the liquid crystal display screen in accordance with the output timing.
Further, the data control unit 101 inputs the video data and holds the video data in the write data holding unit 114, and inputs the video data to a specified address of the frame memory 104 at the timing of the write control signal of the memory control signal generation unit 102. Write video data.

The drive unit 105 drives the liquid crystal display screen divided into two parts for the display data of the upper screen and the display data of the lower screen output from the data control unit. LCD display screen 10
6 displays the upper screen display data on the upper screen and the lower screen display data on the lower screen.

FIG. 6 shows a timing chart of a conventional driving method. FIG. 6 is a timing chart in the case of horizontal 80 digits and vertical 400 lines. In the figure, the horizontal direction timing represents the delimiter for each character time on the display screen, and represents the timing of writing (W) and reading (R) of 1 character data to the frame memory. For convenience, the order of the character time is represented by a number in parentheses.

In the frame memory cycle, W represents a write cycle (write cycle) to the frame memory, and R represents a read cycle (read cycle). The address of the memory in the frame memory cycle is represented by "line number-digit number". For example, the character time in the figure
The address 1-1 of (1) indicates that the data is displayed in one digit of one line.

Similarly, the write data and the read data respectively represent the write data and the read data at the display position represented by "line number-digit number". The upper screen data is the data to be displayed on the divided upper screen of the liquid crystal screen,
The lower screen data represents the data displayed on the lower screen.

Vertical timing (write cycle)
Represents the timing of the write cycle in the vertical direction by the line number for vertical scanning. The vertical direction timing (read cycle) represents the timing of the vertical read cycle by a line number for performing vertical scanning.

Details of FIG. 6 will be described later. FIG. 7 is a diagram showing the relationship between the addressing sequence for reading and writing data on the conventional frame memory and the display position.

In the figure, the vertical direction corresponds to the line number of the display screen, and the horizontal direction corresponds to the digit number. Hereinafter, an address is represented by a line number / digit number pair ("line number-digit number").

The numbers in parentheses correspond to the numbers of character times in FIG. The numbers in parentheses above each address represent the write cycle (W), and the numbers below the address represent the read cycle (R). For example, the address "1-
"2" indicates that writing is done at character time (2) and reading is done at character time (3).

As shown in the drawing, writing moves from the upper left of the screen to the right on the line, and writing is performed in order from the uppermost line to the lowermost line. In addition, the upper screen and the lower screen are alternately specified for reading, and while moving to the right from the first line (201 line for the lower screen) of each, the order is from the top line to the bottom line of each screen. Read out.

The timing of the conventional drive system shown in FIG. 6 will be described. If necessary, refer to FIG. Description will be given in the order of the character times shown.

(1) Address 1-1 of frame memory
The write data of the display position 1-1 (hereinafter referred to as write data 1-1) is written in (hereinafter referred to as 1-1). Next, the data 1-1 of the frame memory is read (see 1-1 in FIG. 7).

(2) Write the write data 1-2 into the frame memory 1-2. Next, 201 of the frame memory
The data of -1 is read (see 1-2 and 201-1 in FIG. 7).

(3) Write the write data 1-3 into the frame memory 1-3. Next, the data in the frame memory 1-2 is read (see 1-2 and 1-3 in FIG. 7).
In the two character time of (3) to (4), the read data 1-1 read in (1) is shifted to be upper screen data, and the data of the frame memory 201-1 read in (2) is lower screen data. The upper screen data and the lower screen data are output as.

(4) Write the write data 1-4 into the frame memory 1-4. Next, 201-of the frame memory
The data of No. 2 is read (see 1-4 and 202-2 in FIG. 7). (5) Write data 1-5 in frame memory 1-5
Write. Next, the data 1-3 of the frame memory is read (see 1-5 and 1-3 in FIG. 7). (5) ~
The data of 1-2 read in (3) in (6) and the data of 201-2 read in (4) are output as upper screen data and lower screen data, respectively.

(6) to (79) saves labor. (80) Write data 1 to 1-80 of the frame memory
Write -80. Next, the data in the frame memory 201-40 is read.

As described above, writing of one line and reading of data up to the 40th digit of the 1st line and up to the 40th digit of the 201st line are performed and displayed. Similarly, the data of the second line is written with the character time numbers (81) to (160), and 41 to 80 digits and 201 of one line are written.
The data of 41 to 80 digits of the line is read out,
Is displayed.

[0027]

In the conventional driving method of the liquid crystal display device divided into two screens, it was necessary to store the data for one screen in the frame memory. Therefore, if the number of pixels of the liquid crystal screen is increased in order to improve the accuracy of screen display, it is necessary to increase the memory capacity. Since increasing the size of the memory also increases the load on the memory peripheral circuits, it is desirable to display the screen with as little memory capacity as possible.

It is an object of the present invention to provide a liquid crystal drive system in which two screens are divided by a frame memory having a half of the storage capacity necessary to store the display data of pixels of one screen.

[0029]

According to the present invention, display data read from a frame memory and display data of the other screen corresponding to the display data are input from a video input section and liquid crystal is used as display data for each of the two divided screens. Output to the screen. On the other hand, by writing the input display data to the address from which the data is read, the liquid crystal screen can be displayed with a memory having a half capacity of the storage capacity corresponding to the number of pixels of one screen.

The basic configuration of the present invention is shown in FIG. In the figure, 1 is a frame memory for storing 1/2 display data of one screen, and 1 and 2 represent one memory state 1 and one state 2. State 1 represents a state in which the data at position 1-1 on the display screen is stored in address 1-1, and state 2 indicates that the data at position 1-1 in the display screen is displayed at address 1-1 after reading the data at address 1-1. It represents a state in which -1 data is stored. A liquid crystal display screen 3 is divided into a divided screen A and a divided screen B, and the liquid crystal display is driven. Reference numeral 4 denotes a memory address generation unit for designating an address for writing video data in the frame memory and an address for reading as display data. A data control unit 5 writes video data to an address designated by the memory address generation unit 4 or reads data at a designated address. A drive unit 6 drives the display data of the split screen A and the display data of the split screen B output from the data control unit 5 so as to be displayed on the respective split screens of the liquid crystal display screen. A video data input unit 7 inputs video data to the frame memories 1 and 2. A memory control signal generator 8 generates control signals for the frame memories 1 and 2 such as output enable, input enable, and chip select.

A display data holding unit 1 holds the display data read from the frame memory states 1 and 2, and comprises a register. Reference numeral 11 denotes a display data holding unit 2 which is composed of a register and which inputs and holds video data to be displayed on a split screen different from the split screen which displays the display data held by the display data holding unit 1 (10). The display data holding unit 1 (10) outputs the display data to the liquid crystal display screen at the timing of output. Then, the data held in the display data holding unit 2 (11) is output as display data and is stored in the address from which the display data held in the display data holding unit 1 (10) is read.

[0032]

The operation of the configuration shown in FIG. 1 will be described. Address 1-1
Writing (upper left corner in frame memory 1 in the figure),
In the case of reading, the operation will be described according to the circled numbers in the figure.

The memory address generator 4 specifies the address 1-1 of the frame memory 1. The memory control signal generation unit 8 generates a read control signal, and the data control unit 5 reads the data at address 1-1 of the frame memory 1 to display the display data holding unit 1 (1
Hold at 0).

The data control unit 5 displays the display position 201-1.
The display data of 1 is fetched from the video data input unit 7 and held in the display data holding unit 2 (11). The data control unit 5 aligns the display data of the display position 1-1 held in the display data holding unit 1 (10) with the display data of the display position 201-1 held in the display data holding unit 2 (11) to drive the driving unit. Output to 6.

The data control unit 5 stores the data of the display position 201-1 held in the display data holding unit 2 (11) at the address 1-1. The drive unit 6 displays the data of the display position 1-1 (split screen A) output from the data control unit 5 and the display position 201-1.
The data of (divided screen B) is displayed at each display position.

Next, similarly, the data control unit 5 reads out and holds the data of the address 1-2, and the display position 201-
The display data of 2 is input and held, the data of the display position 1-2 and the data of the display position 201-2 are output, and the data of the display position 201-2 is stored in the address 1-2.

Thereafter, similarly, the process proceeds for each line. FIG. 2 shows the relationship between the read position, the write address designation sequence, and the display position of the frame memory of the present invention.

FIG. 6A shows the operation of the first line. The figure is
A frame memory for a display screen having 400 lines in the vertical direction and 80 digits in the horizontal direction is shown. The vertical direction corresponds to the line number, and the horizontal direction corresponds to the digit number.

The upper number of each address indicates the display position of the read data, and the lower data indicates the display position of the written data. The numbers in parentheses in the figure represent the order of the character time (see FIG. 6).

Hereinafter, the way of expressing the address is the same as the case of FIG. 7 (represented by "line number-digit number"). At the character time (1), the data at address 1-1 is read out, displayed at display position 1-1, and after reading out, the display data at display position 201-1 is written at the same address. At character time (2), the data at address 1-2 is read and displayed at display position 1-2, and after reading, the display data at display position 201-2 is written at the same address.
Similarly, the processing is sequentially performed for each digit of one line, the data at the address 1-80 is read at the character time (80), displayed at the display position 1-80, and after being read, the display position 201-80 at the same address. Write the display data of.

Similarly, for the second and subsequent lines, the data is read from the frame memory and held, and the data to be displayed on the other split screen different from the split screen for displaying the read data is input from the video input unit to split the data into two split screens. Align the screen data and output. Then, the process of writing the data of the other split screen input from the video input unit to the read address is repeated.

FIG. 6B shows the state of the frame memory at the end of the operation of one line. Data on the first line is display position 2
The state in which the data is replaced by data of line 01 (first line of divided screen B) is shown.

FIG. 6C shows the state of the frame memory after the end of one frame. The data of all the lines are replaced with the data of the lines of the divided screen B. In the next frame,
The data on the frame memory in Figure (c) is read out, and the data read from the frame memory is displayed on the split screen B together with the display data input from the video input section.
The display data input from the video input unit is displayed on the split screen A. Further, the display data input from the video input section is written in the address read immediately before in the frame memory, and the data in the frame memory is replaced with the data in the divided screen A.

[0044]

FIG. 3 shows the configuration of an embodiment of the present invention. In the figure, 30 is a frame monitoring unit and 31 is an initial operation control unit, which stores data of 1 to 200 lines in a frame memory at the start of operation. A memory control signal generator 32 has a control cycle (access time) that is twice that of the conventional method. A memory address generator 33 outputs a write address and a read address of the same address. A data control unit 34 includes a display data holding unit 1 and a display data holding unit 2, and the display data held in the display data holding unit 2 is written in a frame memory and is output as display data. is there. A frame memory 35 has a storage capacity of 1/2 of the number of pixels of the display screen. An address counter 40 generates the same write address and read address.
Reference numeral 41 denotes a display data holding unit 1, which temporarily holds the read data from the frame memory,
The display data is output to the drive unit (not shown) of the liquid crystal display screen at the same timing as the display data stored in the display data. 42
Is a display data holding unit 2 for inputting video data and outputting it to the drive unit of the liquid crystal display screen at the same timing as the display data held in the display data holding unit 1 (41). The display data held in the display data holding unit 2 is written in the address from which the data in the display data holding unit 1 (41) is read.

The operation of the configuration of FIG. 3 will be described with reference to FIG.
FIG. 4 is a timing diagram of the driving method of the present invention. The CRT video signal is sent to the data control unit 34 by 1 /
It is input at a frame frequency of 2. Then, the write and read timing cycle of the memory control signal generator 32 is doubled as compared with the conventional method, and the character time (1) to (16)
In 0), the display data of one line is written and the display data of one line is read.

First, the initial operation control section 31 writes the data of 1 to 200 lines of the frame memory at the start of the operation. Hereinafter, FIG. 4 will be described according to the numbers in parentheses indicating the order of the character times (see FIG. 1).

(1) The data control section 5 reads the data at address 1-1 (hereinafter simply referred to as 1-1) of the frame memory and holds it in the display data holding section 1 (10). At the same time, the video data of the display position 201-1 is fetched and stored in the display data holding unit 2 (11) (write data 201-1).

(2) The data control section 34 writes the write data 201-1 in the frame memory 1-1. (3) The data control unit 5 reads out the data in the frame memory 1-2 and holds it in the display data holding unit 1 (10). At the same time, the video data of the display position 201-2 is fetched and held in the display data storage unit 2 (11) (write data 201-2).

(4) The data control section 5 stores the display data of the display position 201-2 held in the display data storage section 2 (11) in the frame memory 1-2. During the character time (3) to (4), the display data held in the display data holding unit 1 (10) and the display data holding unit 2 (11) are output as upper screen data and lower screen data, respectively.

The steps (5) to (79) will be omitted (the processing will proceed in the same manner). (80) The data control unit 5 uses the display data holding unit 2 (1
In 1), the video data (write data 201-40) to be displayed at the held display position 201-40 is written in 1-40 of the frame memory. Character time (79) ~
At (80), the lower screen data of the display position 201-39 and the upper screen data of the display position 1-39 are output.

(81) The data control unit 5 reads the data 1-41 in the frame memory and holds it in the display data holding unit 1 (10). The data control unit 5 fetches the video data into the display data holding unit 2 (11) and holds it (write data 201-41).

(82) The data control section 5 stores the data (write data 201) stored in the display data storage section 2 (11).
-41) is written in 1-41 of the frame memory. During the character time (81) to (82), the data control unit 5 displays the upper screen data of the display position 1-40 held in the display data holding unit 1 (10) and the display position 201 held in the display data holding unit 2 (11). -40 lower screen data is output.

Thereafter, the same processing is carried out ((83) to (1)
59) is omitted). (160) The data control unit 5 uses the frame memory 1-
The data of 79 is read (not shown) and held in the display data holding unit 1 (10). The data control unit 5 inputs the video data and stores it in the display data holding unit 2 (11).
Character time (161), (1
In 62), it is output together with the data held in the display data holding unit 1 (10).

At the vertical timing (write cycle), as shown in the figure, the data of 201 lines of the display screen is written in the character time of (1) to (160). At the same time, in the vertical timing (read cycle), the display data of one line is read from the frame memory at the character time of (1) to (160).

[0055]

According to the present invention, it is possible to perform screen division driving of a liquid crystal display device with a frame memory having a storage capacity that is half the storage capacity required to store display data for pixels of one screen. Become. Therefore, the configuration of the memory peripheral device is simplified, the liquid crystal display device can be downsized, and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing a relationship between a read / write address designation order and a display position of the frame memory of the present invention.

FIG. 3 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 4 is a timing diagram of the driving method of the present invention.

FIG. 5 is an explanatory diagram of a conventional technique.

FIG. 6 is a timing diagram of a conventional driving method.

FIG. 7 is a diagram showing a relationship between a reading / writing address designation order of a conventional frame memory and a display position.

[Explanation of symbols]

 1: frame memory (state 1) 2: frame memory (state 2) 3: liquid crystal display screen 3A: split screen A 3B: split screen B 4: memory address generation unit 5: data control unit 6: drive unit 7: video data Input unit 8: Memory control signal generation unit

Claims (1)

Claim: What is claimed is: 1. A frame memory having a storage capacity which is half the storage capacity required to store display data of one display screen in a screen division drive system of a liquid crystal display device divided into two.
(1), a memory address generation unit (4) for generating an address for accessing the frame memory (1), and a frame memory
Memory control signal generator that generates the control signal of (1) (8)
And a data control unit (5) that controls input / output of display data and controls writing and reading to and from the frame memory (1)
And a video data input section (7) for inputting video data to be written in the frame memory (1), and a data control section
(5) includes a display data holding unit 1 (10) that holds the data read from the frame memory (1) and a display data holding unit 2 (11) that holds the input display data, and a data control unit
(5) reads the display data of one split screen (3A) from the frame memory (1) at the address specified by the memory address generator (4) and holds it, and the other split screen (3)
The display data of B) is input and held, and the display data input from the video data input section (7) is stored in the above address of the frame memory (1) and the frame memory (1)
A screen division drive method for a liquid crystal display device, characterized in that the display data read from the display data and the input display data are output together and displayed on the divided screens (3A) and (3B), respectively.