KR100833190B1 - Response Time Accelerator and method thereof in LCD Timing Controller - Google Patents

Abstract

A reaction time accelerator provided in the LCD time controller is provided. The response time accelerator according to the present invention reads the response time acceleration values from a ROM, and generates and outputs an interpolation coefficient in each of the R, G, and B channels by using the read data and a constant equation. An internal memory for storing coefficients according to R, G, and B channels, respectively, and an interpolator for obtaining a response time acceleration value for performing interpolation using interpolation coefficients, current pixel data, and previous pixel data. The reaction time acceleration values stored in the ROM are read out in a zigzag order in predetermined columns. The response time accelerator according to the present invention may read ROM data in a zigzag order, thereby reducing the number of logic gates and reducing power consumption.

Description

Response Time Accelerator and method in LCD Timing Controller

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a view showing a conventional reaction time accelerator.

2 is a diagram illustrating a frame signal input for display of an LCD device.

FIG. 3 is a diagram for describing ROM data read by the conventional reaction time accelerator of FIG. 1.

4 is a view showing a reaction time accelerator according to the present invention.

FIG. 5 is a diagram illustrating ROM data read by the reaction time accelerator of FIG. 4.

** Description of the symbols for the main parts of the drawings **

110: ROM (Read Only Memory)

120: interface control unit (I2C Controller)

125: First Internal Memory

130: interpolation coefficient generator (Interpolation Parameter)

150: second internal memory

160: Interpolation

201, 205, and 210: frame signal

310: ROM data structure

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reaction time accelerator and a method thereof, and more particularly, to a reaction time accelerator and a method provided in an LCD time controller and capable of reducing area and power consumption.

1 is a view showing a conventional reaction time accelerator.

The LCD (Liquid Crystal Display) device includes a time controller (LCD Timing Controller) that controls the time for outputting the image data signal output through the source driver and various control signals output through the gate driver. Equipped.

In the LCD device, since the liquid crystal constituting the pixels of the LCD panel has a slow response speed, various problems occur in response to the response speed, such as afterimages, when a moving picture is applied to a TV. .

The liquid crystal cell constituting the LCD panel blocks or transmits light while the grating rotates when biased at both ends. However, the time that the liquid crystal rotates in response to the bias is relatively slow at several tens of milliseconds (msec), but since the LCD device operates at a frequency of 60 Hz, the rotation of the liquid crystal should be completed within 16.7 msec. That is, there is a problem in that the liquid crystal does not sufficiently respond to data changing in real time. For example, when the bias applied to the liquid crystal of the LCD panel is 256 gray voltages of 8-bit image data, the luminance characteristics actually displayed in response to the liquid crystal fall short of 256 gray levels, which causes afterimages in moving vertical line patterns and the like. .

In order to solve the problem related to the response speed, a response time accelerator (RTA-Response Time Accelerator) for accelerating the reaction time is usually provided at the front end of the source driver for driving the liquid crystal panel. The response time accelerator (RTA) outputs an interpolation value (RTA_OUT) that can accelerate the current frame data.

Referring to FIG. 1, a conventional reaction time accelerator (RTA) may include an interface controller (I2C controller) 120, a first internal memory 125, an interpolation coefficient generator 130, A second intermal memory 150, and an interpolation 160. The RTA 100 compares the previous frame data with the current frame data and interpolates the current frame data with other values so that the response time may be accelerated according to the difference. Try to match the frame data.

The interface controller 120 is a device that enables communication between the ROM 110 and the integrated circuit 100. ROM 110 stores some of the response time acceleration values associated with current and previous frame data. When the system starts to boot, the integrated circuit 100 reads data stored in the ROM 110 in synchronization with a clock. At this time, the device for interfacing the data to be read from the ROM 110 is the interface controller 120 (I2C). The interface controller 120 (I2C) sequentially reads all the reaction time acceleration values ROM_DATA stored in the ROM 110 and transmits them to the first internal memory 125.

The first internal memory 125 stores all the reaction time acceleration value ROM_DATA transmitted through the interface controller 120. That is, the frame data stored in the ROM 110 is copied and stored again as it is. The signal stored and read in the first internal memory 125 is referred to as first memory data MEM_DATA1.

The interpolation coefficient generator 130 receives the first memory data MEM_DATA1 and generates and outputs interpolation coefficients in each of the R, G, and B channels by using the first memory data MEM_DATA1 and a constant equation. do.

Only some reaction time acceleration values are stored in the ROM 110. Therefore, all remaining reaction time acceleration values should be obtained to obtain the total reaction time acceleration values RTA_OUT. In order to obtain a response time acceleration value (RTA_OUT) used to accelerate the response speed of the liquid crystal, an interpolation parameter must first be obtained. The interpolation coefficient PARAM can be obtained by substituting the first memory data MEM_DATA1 into various equations (first equation). The first equation used herein is implemented through logic logic provided in the interpolation coefficient generator 130.

The equation used to find the interpolation coefficient depends on the LCD device used. Therefore, these equations are extracted by experiments and experience, and it is impossible to limit them to certain equations. In addition, since it will be apparent to those skilled in the art to extract such an equation empirically, a detailed description thereof will be omitted.

Here, the interpolation coefficients are obtained from R (red) color, G (green) color, and B (blue) color, respectively. In other words, three interpolation coefficients (R color interpolation coefficient, G color interpolation coefficient, B color interpolation coefficient) are obtained using the frame data of one pixel.

The second internal memory 150 stores the interpolation coefficients obtained by the interpolation coefficient generator 130. Since three interpolation coefficients must be stored for each color per pixel, the second internal memory is divided into three memory units according to colors. That is, there is a second internal memory 152 that stores the R color interpolation coefficient, a second internal memory 154 that stores the G color interpolation coefficient, and a second internal memory 156 that stores the B color interpolation coefficient. will be. The upper part bits CF [A: B] of the current frame data and the upper part bits PF [A: B] of the previous frame data are received and stored. The interpolation coefficient (PARAM) value stored in the second internal memory 150 and output, and the upper part bits PF [A: B] and CF [A: B] of the current and previous frame data are stored in the second memory data MEM_DATA2. Is called.

The interpolator 160 uses the second memory data MEM_DATA, the lower part bits CF [C: D] of the current frame data, and the lower part bits PF [C: D] of the previous frame data. The interpolation value (RTA_OUT) to be used for accelerating the reaction time of the present liquid crystal is obtained. In an LCD device having a resolution of 1920 x 1080, all 1920 x 1080 pixels are interpolated and output. If one pixel is implemented with color of 8 bits of frame data per panel, too many bits of data must be stored to store interpolated values of current and previous data for all pixel values as ROM data. That is, the capacity of the memory (ROM) to be provided is increased, resulting in damage in terms of cost, efficiency, and loading. Therefore, the second internal memory 150 of the RTA apparatus 100 stores only the upper few bits of the frame data so as to obtain information about the previous and current colors and use it for compensation.

CF [7: 4] may mean the current frame data signal including information on the upper 4 bits (4th to 7th bits) in 8-bit frame data. In addition, CF [3: 0] may refer to a current frame data signal including information about lower 0 bits (LSB) to lower 3 bits in 8-bit frame data. Here, illustrated C and D represent some upper bits, and A and B represent some lower bits.

In addition, the interpolator 160 performs the interpolation coefficient (MEM_DATA2) and the lower part bits (CF [C: D]) of the current frame data in order to perform interpolation. The response time acceleration value (RTA_OUT) is obtained by substituting, and lower bits (PF [C: D]) of previous frame data. Here, the second equation is implemented through logic logic as in the first equation described above, which is a value that can be obtained empirically according to the specifications of the LCD device.

In general, the step of reading frame data from the ROM 110 and storing the frame data in the second internal memory 150 is referred to as a system boot period, and an interpolation coefficient stored in the second internal memory 150. The time taken to read and generate the response time acceleration value (RTA_OUT) is called a normal operation period.

2 is a diagram illustrating a frame signal input for display of an LCD device.

Referring to FIG. 2, a frame signal is input in units of frames over time. If the LCD device has a resolution of 1920 x 1080, a frame signal composed of a combination of a horizontal 1920 pixel and a vertical 1080 pixel is received over time. If the current time is t2, the current frame signal becomes 205 and the previous frame signal becomes 201.

3 is a view for explaining the ROM data read by the conventional reaction time accelerator of FIG.

Referring to FIG. 3, the response time acceleration value stored in the ROM 110 correlates and stores current and previous frame signals. The numbers described in the first row represent the current frame signals, and the numbers described in the first column represent the previous frame signals. And the numbers 0 to 288 described in the table indicate the storage address at each location. That is, a signal combining the current color information from 0 to 15 pixels and the previous color information from 0 to 15 pixels is stored at address 0, and the previous color information from 48 to 63 pixels and the current 16 The signal combining the color information from 31 pixels to 31 pixels is stored in the 20th address. Although FIG. 3 illustrates a case in which frame data of 256 bytes is used, this will vary depending on the resolution and image quality of the LCD device.

In order to interpolate one pixel data, four ROM data including data at a corresponding address are required. To interpolate pixel data at address 20, ROM data at addresses 20, 21, 37, and 38 are required.

 The conventional first internal memory 125 shown in FIG. 1 sequentially reads and stores ROM 110 data having the structure of FIG. 3 from address 0 to address 288. The same data as that shown in FIG. 2 is stored. In order to interpolate the previous frame data according to the color change in the current frame data, the corresponding pixel of the ROM data stored in the first internal memory 125 and four data around the read data are read again. The interpolation coefficient PARAM is generated using the four data.

Since the memory existing in the RTA 100 is a random access memory (RAM), interpolation coefficients are generated by randomly reading four data adjacent to a point (address) necessary for obtaining the interpolation coefficients. Since the random access memory (RAM) accesses and reads necessary information every time, the random access memory (RAM) performs 4 random accesses to read the data of the addresses 20, 21, 37, and 38th.

As described above, the conventional reaction time accelerator 100 may include a first internal memory 125 that sequentially reads data stored in the ROM 110 and stores the data as it is, and upper-order bit values of the current and previous data and interpolation coefficients. All of the second internal memory 150 for storing the should be provided.

Therefore, there is a problem that the power consumption is relatively large, and the number of logic gates provided in using a memory cell of 1T1C (one storage element composed of one transistor and one capacitor) is also required.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a response time accelerator and a method for reducing power and reducing the number of logic gates provided by not including a conventional first internal memory.

A reaction time accelerator according to an embodiment of the present invention for achieving the above technical problem includes an interpolation coefficient generator, an internal memory, and an interpolator.

The interpolation coefficient generator reads out the response time acceleration values from the ROM, and generates and outputs interpolation coefficients in each of the R, G, and B channels using the read data and certain equations.

The internal memory stores interpolation coefficients according to the R, G, and B channels, respectively.

The interpolator calculates and outputs an interpolation value for accelerating response time using the interpolation coefficient, the current pixel data, and the previous pixel data.

Here, the reaction time acceleration values stored in the ROM may be read in a zigzag order in predetermined columns.

Preferably, reading in zigzag order reads two data sequentially from the specified address when the address of (n, m) is specified, moves to the next row and moves two (n + 1, m) from the address. This is done by reading the data sequentially.

In accordance with another aspect of the present invention, there is provided a method of generating a reaction time acceleration value, by reading reaction time acceleration values stored in a ROM in a ROM, using the read reaction time acceleration value, and a constant equation. Generating interpolation coefficients in each of the G and B channels, and generating an overall response time acceleration value using the interpolation coefficient, the current pixel data, and the previous pixel data.

Here, in the zigzag reading step, when an address of (m, n) is specified, two data are sequentially read from the designated address, and the next line is moved to the next line to start from (m + 1, n) address. This is done repeatedly by reading two data sequentially.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

4 is a view showing a reaction time accelerator according to the present invention.

4, a reaction time accelerator 400 interface controller 400, an interpolation coefficient generator 425, an internal memory 436, and an interpolator 440 are provided.

Since the operation and configuration of the interface controller 400, the internal memory 436, and the interpolator 440 are the same as those described with reference to FIG. 1, detailed descriptions thereof will be omitted.

The interface controller 400 enables data transmission between the ROM 410 and the response time accelerator 400.

The interpolation coefficient generator 425 reads the response time acceleration values stored in the ROM 410 to generate an interpolation coefficient PARAM. In order to obtain an interpolation coefficient used for one pixel, four adjacent reaction time acceleration values are required, which will be apparent to those skilled in the art.

Interpolation must be performed for all pixels displayed at the same time point t1. Therefore, the interpolation coefficient used for one pixel must be obtained over all the frame data. The reaction time accelerator 400 according to the present invention enables the interpolation coefficient (PARAM) to be immediately obtained while reading ROM data without using the conventional first internal memory 125. The structure for obtaining the interpolation coefficient (PARAM) immediately while reading the ROM data will be described in detail with reference to FIG. 5 below.

 FIG. 5 is a diagram illustrating ROM data read by the reaction time accelerator of FIG. 4.

Referring to FIG. 5, data of addresses 0, 1, 17, and 18 in 534 are required to obtain interpolation coefficients for 0 to 15 pixel data in current frame data and 0 to 15 pixel data in previous frame data. . In order to obtain interpolation coefficients for the previous 0 to 15 pixel data and the current 16 to 31 pixel data, data at addresses 17, 18, 34, and 35 in 536 are required.

Accordingly, when data stored in the ROM 410 is read in zigzag order (shown in solid line in FIG. 5) and transmitted to the interpolation coefficient generator 425, the interpolation coefficient for interpolating each pixel may be directly generated. have. That is, the interpolation coefficient generator 425 continuously reads the ROM data in the order of addresses 0, 1, 17, 18, 34, 35,... Therefore, interpolation coefficients for the 0 to 15 pixel data in the current frame data and the 0 to 15 pixel data in the previous frame data are obtained using the data of the addresses 0, 1, 17, and 18 read first. Then, interpolation coefficients for the previous 0 to 15 pixel data and the current 16 to 31 pixel data are obtained using the data of the addresses 17, 18, 34, and 35 read next. This reads ROM data and reads addresses 272, 273, 1, and 2 in the last line. Subsequently, the interpolation coefficient of the frame data is obtained by reading in a zigzag order. Here, the zigzag reading order may be controlled in software.

The reaction time accelerator according to the embodiment of the present invention sequentially reads the ROM data in the zigzag order and immediately obtains the interpolation coefficient. Therefore, the interpolation coefficient PARAM to be obtained can be obtained without having the conventional first internal memory 125. In the RTA device, since the most power consumption is the memory, the power consumption may be reduced by removing the first internal memory 125, and the area of the RTA device may be reduced since the logic gate required in the memory may be removed. Can be.

The interpolation coefficient PARAM thus obtained is transmitted to the internal memory 430. The detailed configuration and operation of the internal memory 430 are the same as the conventional second internal memory described with reference to FIG. 1.

The interpolator 440 calculates the response time acceleration value RTA_OUT to be used for the actual frame data by using the interpolation coefficient PARAM stored in the internal memory 430.

The method for generating a reaction time acceleration value according to an embodiment of the present invention has the same technical concept as the reaction time accelerator described above. Therefore, those skilled in the art will be able to understand the reaction time acceleration value generation method according to the present invention from the foregoing description, and thus a detailed description thereof will be omitted.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, these terms are only used for the purpose of describing the present invention and are not intended to limit the scope of the present invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the reaction time accelerator according to the present invention has an advantage of reducing the number of logic gates and reducing power consumption by reading ROM data in a zigzag order.

Claims (7)

In the LCD time controller, Interpolation coefficients that read out the response time acceleration values for the current and previous pixels from a ROM, generate interpolation coefficients in R, G, and B channels using the read data and the interpolation coefficient calculation equation, and output them to internal memory. Generation unit; An internal memory for storing the interpolation coefficients according to R, G, and B channels; And An interpolator for obtaining an overall response time acceleration value using interpolation coefficients, current pixel data, and previous pixel data stored in the internal memory; And the reaction time acceleration values stored in the ROM are read out in a zigzag order in predetermined columns. The method of claim 1, wherein the reading in the zigzag order is When an address of (n, m) is specified, two data are sequentially read from the specified address, the next row is moved, and two data are sequentially read from the (n + 1, m) address. Reaction time accelerator, characterized in that made by. The method of claim 2, wherein the interpolation coefficient calculation equation Reaction time accelerator, characterized in that implemented using the logic logic in the interpolation coefficient generator. The method of claim 2, wherein the reaction time accelerator And an interface controller for interfacing the ROM and the interpolation coefficient generator so that a signal can be transmitted in front of the interpolation coefficient generator. The ROM data of claim 2, wherein the ROM data A response time accelerator, characterized in that m current frame signals and m previous frame signals are associated with each other to form an m x m matrix structure. Reading the reaction time acceleration values stored in the ROM in a zigzag order; Receiving data read out in the zigzag order, and generating and storing interpolation coefficients in R, G, and B channels using the read ROM data and an interpolation coefficient calculation equation; And Generating an overall response time acceleration value using the stored interpolation coefficients, current pixel data, and previous pixel data, The reading in the zigzag order And generating the reaction time acceleration values stored in the ROM in a zigzag order in predetermined columns. The method of claim 6, wherein the reading in the zigzag order When an address of (m, n) is specified, two data are sequentially read from the specified address, the next row is moved, and two data are sequentially read from the (m + 1, n) address. Method for generating a reaction time acceleration value, characterized in that is done by.

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