KR101238006B1 - Liquid crystal display having column-gate driver - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having a column-gate driver, wherein one gate line of each liquid crystal display device is disposed at every two adjacent unit pixels in a row direction to supply a gate signal at the same time. The data lines of the liquid crystal display supply data signals to the unit pixels in synchronization with the gate signals supplied through the gate lines, and are arranged two by one between adjacent unit pixels in the column direction.

Liquid Crystal Display, Column-Gate Driver, Frame Memory, Low-Data Driver

Description

Liquid crystal display with column-gate driver {LIQUID CRYSTAL DISPLAY HAVING COLUMN-GATE DRIVER}

FIG. 1 is a configuration diagram of a liquid crystal display device having a general column-data driver.

2 is a block diagram of a liquid crystal display device having a column-gate driver according to the related art.

3 is a block diagram of a liquid crystal display device having a column-gate driver according to a first embodiment of the present invention.

4A and 4B are diagrams illustrating read and write areas of pixel data in a liquid crystal display having a column-gate driver according to a first embodiment of the present invention, respectively.

5A and 5D illustrate rearrangement of input data in a frame memory in a liquid crystal display having a column-gate driver according to a first embodiment of the present invention.

FIG. 6 is a configuration diagram of a row-data driver of a liquid crystal display having a column-gate driver according to a first exemplary embodiment of the present invention.

7 is a configuration diagram of a liquid crystal display device having a column-gate driver according to a second exemplary embodiment of the present invention.

8 is a diagram illustrating a layout of a liquid crystal display panel in a liquid crystal display having a column-gate driver according to a second embodiment of the present invention.

DESCRIPTION OF THE REFERENCE NUMERALS

310: liquid crystal display panel # 320: column-gate driver

330: low-data driver 340: timing controller

350: frame memory 351: read frame memory

352: write frame memory

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display having a column-gate driver.

The liquid crystal display adjusts the light transmittance of the liquid crystal using an electric field, thereby displaying an image corresponding to the video signal on the liquid crystal display panel. As such a liquid crystal display, a thin film transistor-liquid crystal display (TFT-LCD) is mainly used.

Specifically, the light transmittance is adjusted while the backlight, which is white light, passes through the liquid crystal pixels, and then passes through the color filter layers of red (R), green (G), and blue (B) disposed 1: 1 on each liquid crystal pixel. The color mixture of the TFT-LCD is produced by adding mixed color of the emitted light. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in an active matrix, and a driving circuit including a gate driver and a data driver for driving the liquid crystal display panel.

FIG. 1 is a configuration diagram of a liquid crystal display device having a general column-data driver.

Referring to FIG. 1, a general liquid crystal display device includes a liquid crystal display panel 110, a row-gate driver 120, a column-data driver 130, and a timing controller 140. And a frame memory 150 configured to store one frame data so as to process one frame data input from the outside (for example, a computer main body, a DVD, etc.) on a frame basis.

The gate driver of a general liquid crystal display device is disposed in a row direction of the liquid crystal display panel 110, and the data driver is disposed in a column direction of the liquid crystal display panel 110. For convenience, the low-gate driver 120 and the data driver will be referred to as a column-data driver 130.

Meanwhile, recently, a liquid crystal display including a column-gate driver having a structure in which positions of the gate driver and the data driver are interchanged has been developed, which is advantageous in terms of cost reduction when implementing a driving circuit. Because. In other words, in the liquid crystal display having the column-gate driver, the gate driver is disposed in the column direction of the liquid crystal display panel, and the data driver is disposed in the row direction of the liquid crystal display panel. In the present specification, such a gate driver will be referred to as a column-gate driver for convenience, and the data driver will be referred to as a row-data driver.

2 is a block diagram of a liquid crystal display having a column-gate driver according to the related art.

2, a liquid crystal display having a column-gate driver according to the related art includes a liquid crystal display panel 210, a column-gate driver 220, a low-data driver 230, and a timing controller 240. And a frame memory 250 for rearranging and outputting one frame data input from the outside in units of frames.

The liquid crystal display panel 210 includes a plurality of pixels arranged in a matrix form divided by gate lines and data lines that cross each other. For example, the liquid crystal display panel 210 having an n × m matrix arrangement may include a plurality of gate lines S ₁ to S _n , a plurality of data lines D ₁ to D _m , and a plurality of gate lines ( S ₁ to S _n ) and a switching element (not shown) formed at the intersection of each of the data lines D ₁ to D _m . In addition, a plurality of sub-pixels R, G, and B are formed in an area defined by the plurality of gate lines S ₁ to S _n and the data lines D ₁ to D _m .

Such a plurality of sub-pixels R, G, and B have a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B arranged alternately, and a red sub-pixel ( R), the green sub-pixel G and the blue sub-pixel B are combined to form one unit pixel. In other words, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B are formed in an area defined by one gate line and three data lines. (R), green sub-pixel G, and blue sub-pixel B constitute one unit pixel.

The timing controller 240 reads and rearranges one frame data input from the outside in units of one frame, and generates and outputs the pixel data, the gate control signal, and the data control signal of the rearranged one frame, respectively.

In this case, a frame memory 250 for storing pixel data of the one frame to be rearranged and pixel data of the rearranged one frame is required. Here, the frame memory 250 reads out one frame data input from the outside in units of frames and reads the read frame memory 251 for storing the one frame data, and the one frame data rearranged so as to be output to the row-data driver 230. It consists of a write frame memory 252 for storing.

However, as shown in FIG. 1, the frame memory 150 of the general liquid crystal display requires one frame memory because no realignment process of pixel data is required. However, as shown in FIG. Since a liquid crystal display having a gate driver undergoes a rearrangement process of pixel data, twice as much frame memory 250 is required as a general liquid crystal display.

Referring to FIG. 2 again, the column-gate driver 220 drives a gate in a column direction of the liquid crystal display panel 210 and the gate lines according to a gate control signal provided from the timing controller 240. Scan pulses are sequentially output to S ₁ to S _n .

The low-data driver 230 drives a source in a row direction of the liquid crystal display panel 210, and corresponds to data control signals provided from the timing controller 240 and data corresponding to the rearranged one-frame pixel data. The voltage is output to the data lines D ₁ to D _m line by line.

The column-gate driver 220 may provide a scan signal to the gate lines S ₁ to S _n in a scanning period (for example, 1/60 = 16.7 Hz when the driving frequency is 60 Hz) to provide a switching device. In this case, the switching element transfers the data signal provided by the low-data driver 230 to each of the sub-pixels R, G, and B according to the scan signal.

The read frame memory 251 and the write frame memory 252 each store one frame of data corresponding to several tens of megabytes. While the driving circuit of a conventional liquid crystal display requires one frame memory capable of storing one frame of data, the driving circuit of a liquid crystal display having a column-gate driver according to the related art is capable of storing two frame data. There is a problem that a frame memory is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display having a column-gate driver capable of reducing the size of the frame memory used in the liquid crystal display having the column-gate driver and reducing the data driving capacity of the low-data driver. It is for.

In addition, another object of the present invention is to provide a liquid crystal display device having a column-gate driver that can reduce the size of the frame memory used in the liquid crystal display device having the column-gate driver and ensure sufficient gate charging time. It is for.

The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an exemplary embodiment of the present invention, a liquid crystal display includes: a liquid crystal display panel including pixels arranged in a matrix formed by gate lines formed along a column direction and data lines formed along a row direction; A timing controller which reads the input one frame data in units of 1/2 frames and rearranges them, and generates pixel data, gate control signals, and data control signals of the rearranged 1/2 frames, respectively; A frame memory for storing pixel data of the rearranged 1/2 frame; A column-gate driver sequentially outputting scan pulses to the gate lines in response to the gate control signal; And a low-data driver configured to output data voltages corresponding to the rearranged half-frame pixel data to the data lines in response to the data control signal.
One gate line is disposed for every two unit pixels adjacent in the row direction to simultaneously supply the gate signal.
The data lines supply data signals to the unit pixels in synchronization with the gate signals supplied through the gate lines, and are disposed between the unit pixels adjacent to each other in the column direction.

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Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments make the disclosure of the present invention complete and the general knowledge in the technical field to which the present invention belongs. It is provided to fully convey the scope of the invention to those skilled in the art, the invention being defined only by the scope of the claims.

Hereinafter, a liquid crystal display having a column-gate driver according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

In general, a driving circuit of a liquid crystal display device includes a liquid crystal display panel having a plurality of gate lines and data lines arranged in a direction perpendicular to each other, and having a pixel area in a matrix form, and a driving circuit for supplying driving signals and data signals to the liquid crystal display panel. And a backlight unit for providing a constant light source to the liquid crystal display panel. In addition, the driving circuit of the liquid crystal display includes a data driver, a gate driver, a timing controller, a power supply, a gamma reference voltage unit, a DC / DC converter, and an inverter. In the description of the embodiment of the present invention, a detailed description of components that are not related to the embodiment of the present invention, such as the power supply unit, the gamma reference voltage unit, the DC / DC converter, and the inverter, will be omitted.

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The first embodiment of the present invention shows a liquid crystal display having a column-gate driver capable of reducing the size of the frame memory and at the same time reducing the data driving capacity of the data driver. A liquid crystal display device having a column-gate driver capable of reducing a size and securing a gate charge time is provided.

First Embodiment

3 is a block diagram of a liquid crystal display device having a column-gate driver according to a first embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display having the column-gate driver according to the first exemplary embodiment of the present invention includes a liquid crystal display panel 310, a column-gate driver 320, a low-data driver 330, and a timing. It includes a controller 340, and further includes a frame memory 350 for rearranging and outputting one frame data input from the outside in 1/2 frame unit.

As shown in FIG. 3, the liquid crystal display panel 310 includes a plurality of gate lines, a plurality of data lines, a plurality of sub-pixels R, G, and B, and switching elements (not shown) that cross each other. ).

In this case, the plurality of gate lines are arranged in parallel in the column direction, transmit a scan signal provided by the column-gate driver 320 to the switching element, and the plurality of data lines are arranged in parallel in the row direction, The signal provided by the data driver 330 is transmitted to the switching element. Here, the switching element is for transferring the analog data signal provided by the low-data driver 330 to each of the sub-pixels R, G, and B according to the scan signal.

Here, reference numerals 311 and 312 denote portions corresponding to 1/2 frames of the liquid crystal display panel 310, respectively.

As shown in FIG. 3, the timing controller 340 generates a driving control signal which is a timing control signal for driving the liquid crystal display panel 310 by using a vertical synchronization signal and a horizontal synchronization signal supplied from a digital video card. do.

That is, the timing controller 340 is a pixel data (R, G, B Data), clock signal (MCLK), horizontal synchronization signal (Hsync), vertical synchronization input from the outside (for example, computer main body, DVD, etc.) The driving timing of the column-gate driver 320 and the low-data driver 330 is controlled according to the signal Vsync and the data enable signal DE. That is, the timing controller 340 generates a gate shift clock, a gate start pulse, and the like in response to the clock signal MCLK, the horizontal sync signal Hsync, and the vertical sync signal Vsync to the column-gate driver 320. to provide.

In addition, the timing controller 340 generates a data clock signal, a data control signal, a polarity control signal, and the like in response to the clock signal MCLK, the horizontal synchronization signal Hsync, and the vertical synchronization signal Vsync. The digital data signal input from the outside in synchronization with the data clock signal is provided to the low-data driver 330 in ½ frame unit.

In other words, the timing controller 340 reads and rearranges 1 frame data input from the outside in units of 1/2 frames, and generates pixel data, gate control signals, and data control signals of the rearranged 1/2 frames, respectively. Will print. In this case, the timing controller 340 controls to repeat reading and writing of pixel data in units of 1/2 frames. In detail, the timing controller 340 reads the RGB pixel data of the horizontal lines of 1/2 frame from the RGB pixel data of the horizontal lines of one frame input from the outside, and stores the RGB pixel data of the horizontal lines of the 1/2 frame in the read frame memory 351. After rearranging the RGB pixel data for each vertical line of the 1/2 frame and storing the same in the write frame memory 352, the rear frame data is output to the row-data driver 330. FIG.

As illustrated in FIG. 3, the frame memory 350 stores pixel data of the half-frame to be rearranged and pixel data of the rearranged half-frame. In this case, the frame memory 350 temporarily stores the read frame memory 351 for temporarily storing the pixel data of the half-frame to be rearranged, and temporarily outputs the pixel data of the rearranged half-frame. It consists of a write frame memory 352. Therefore, only one frame memory is required because the read frame memory 351 and the write frame memory 352, which are each reduced by one half, are used.

In addition, the frame memory 350 may be embedded in the timing controller 340 or separately provided in the predetermined space of the driving circuit.

As shown in FIG. 3, the column-gate driver 320 drives a gate in a column direction of the liquid crystal display panel 310, and sequentially outputs scan pulses to the gate lines according to the gate control signal. . That is, the column-gate driver 320 is arranged in the column direction on the liquid crystal display panel 310, and provides a scan signal to a plurality of gate lines during the scanning period under the control of the timing controller 340 to provide a switching device. Drive. Here, the switching element may be composed of a thin film transistor element.

As illustrated in FIG. 3, the low-data driver 330 converts a digital data signal from the timing controller 340 into an analog data signal and provides the data lines to the data lines under the control of the timing controller 340. . In this case, the switching element (not shown) transfers the analog data signal provided by the low-data driver 330 to each of the sub-pixels R, G, and B according to the scan signal.

In detail, the row-data driver 330 drives a source in a row direction of the liquid crystal display panel 310 and receives a data voltage corresponding to the data control signal and the rearranged 1 / 2-pixel pixel data. Output to data lines. That is, when the number of pixel in the column direction is n, the row-data driver 330 sequentially sequentially the pixel data of the rearranged 1/2 frame by n / 2 lines according to the scan pulse of the column-gate driver 320. To run. In this case, the driving frequency of the low-data driver 330 is twice the driving frequency of the pixel data input in units of one frame.

Meanwhile, a driving method of the liquid crystal display device having the column-gate driver according to the first embodiment of the present invention is as follows. As described above, the liquid crystal display includes a liquid crystal display panel 310, a timing controller 340, a column-gate driver 320, and a low-data driver 330.

First, the timing controller 340 reads and rearranges 1 frame data input from the outside in 1/2 frame units, and generates and outputs the rearranged 1/2 frame pixel data, gate control signal, and data control signal, respectively. do.

In other words, the RGB pixel data of the horizontal lines of 1/2 frames is read from the RGB pixel data of the horizontal lines of one frame input from the outside, and then the RGB pixel data of the horizontal lines of the 1/2 frames is read. The rearrangement is performed by RGB pixel data for each vertical line of the frame, and the rearranged 1/2 frame pixel data is output to the low-data driver.

At this time, the rearranged half-frame pixel data is temporarily stored in the read frame memory 351, and the rearranged half-frame pixel data is temporarily stored in the write frame memory 352 to output the pixel data. That is, after storing the horizontal pixel RGB pixel data of the 1/2 frame in the read frame memory 351 and storing the rearranged 1/2 frame pixel data in the write frame memory 352, the row- Output to the data driver. Such reading and writing is repeatedly performed in 1/2 frame units under the control of the timing controller 340.

Next, scan pulses are sequentially output to the gate lines according to the gate control signal, and then data voltages corresponding to the data control signal and the rearranged 1/2 frame pixel data are output to the data lines. Done.

4A and 4B are diagrams illustrating read and write areas of pixel data in a liquid crystal display having a column-gate driver according to a first embodiment of the present invention, respectively.

4A shows an original data structure input from the outside into a liquid crystal display having a column-gate driver according to the first embodiment of the present invention. When a liquid crystal display panel of a liquid crystal display device having a general column-data driver includes, for example, 800 gate lines (or channels) and 1280 × 3 = 3840 data lines, the first gate line to the 400th gate may be used. The data is read by dividing the first read area 410 up to the line and the second read area 420 from the 401th gate line to the 800th gate line.

In other words, when the pixel data is displayed on a liquid crystal display panel having a general m × n matrix arrangement, first, data of the first reading area 410 is read, and then data of the second second reading area 420 is read.

Next, as shown in FIG. 4B, the liquid crystal display panel 310 of the liquid crystal display device having the column-gate driver according to the first embodiment of the present invention is, for example, 800 gate lines and 1280 ×. When 3 = 3840 data lines, the data of the first read area 410 is rearranged, and then the rearranged data is written to the first write area 430 from the first data line to the 1200 data line. After rearranging the data of the second read area 420 again, the rearranged data is written to the second write area 430 from the second data line to the 1200 data line. Accordingly, the gate-on order proceeds for 1/2 frame from the first gate line of the first writing area 430 to the 1280 gate line for one frame, and then the second writing area 440 of the second writing area 440. The first gate line to the 1280 gate line are processed for 1/2 frame.

Therefore, as shown in FIG. 4A, data displayed on the liquid crystal display panel of the liquid crystal display device having general column data undergoes a rearrangement process, and as shown in FIG. 4B, the first embodiment of the present invention. The rearranged data is displayed on the liquid crystal display panel 310 of the liquid crystal display having the column-gate driver. In this case, the data are stored in the above-described read frame memory 351 and write frame memory 352, respectively.

5A and 5D illustrate rearrangement of input data in a frame memory in a liquid crystal display having a column-gate driver according to a first embodiment of the present invention.

FIG. 5A is a diagram illustrating a case in which pixel data input from the outside is displayed on a liquid crystal display having a general column-data driver, and FIG. 5B rearranges the data of FIG. 5A and stores the data in the read frame memory 351. An example of the form is shown. Here, R of R (m, n) represents a red sub-pixel, m represents a column line, n represents a row line, respectively, and the reading is performed in units of 1/2 frames.

That is, as shown in FIG. 5A, the RGB data of each pixel of the first reading area 510 is sequentially read based on the horizontal line, and then written in the area A of FIG. 5B, and then the second reading area 520. After reading the pixel-by-pixel RGB data on the horizontal line sequentially with respect to the horizontal line, and write to the area 'A' of FIG.

FIG. 5C is a diagram illustrating a case of displaying on a liquid crystal display having a column-gate driver, and FIG. 5D illustrates an example in which the data of FIG. 5C is rearranged and stored in the write frame memory 352. Here, in R (n, m), R denotes a red sub-pixel, n denotes a column line, m denotes a row line, and writing is performed in units of 1/2 frames.

That is, as shown in FIG. 5C, the RGB data of each pixel of the first reading area 530 is sequentially read based on the vertical line, and then written in the area B of FIG. 5D, and then the second reading area 540. After reading the pixel-by-pixel RGB data on the vertical line based on the vertical line, and write to the B 'region of FIG.

However, the above-described FIGS. 5A to 5D show only one example, and the data format stored in the frame memory 350 may vary according to the layout of the liquid crystal display panel 310.

6 is a configuration diagram of a low-data driver of a liquid crystal display having a column-gate driver according to a first embodiment of the present invention, and illustrates functional principles of an 8-bit digital low-data driver. It is a schematic block diagram.

Referring to FIG. 6, the low-data driver 300 of the liquid crystal display according to the first exemplary embodiment of the present invention may include a reduced swing differential signal (RSDS) receiver 610, a shift register 620, and an input register 630. , A storage register 640, a digital-to-analog converter 650, and an output buffer 660.

First, the image information signal is input to the RSDS receiver 610 of the low-data driver by the timing controller by RSDS digital signal transmission, and then converted into 8-bit digital data for each RGB. At this time, after all image data corresponding to one scan line selected as the start signal of the vertical synchronization signal Vsync for line-by-line driving are synchronized with the vertical synchronization clock Vclock, the shift register ( 620 is sequentially sampled into the input register 630.

Here, in the case of a liquid crystal display having a general column-data driver, a horizontal sync signal (Hsync) and a horizontal sync clock (Hclock) are used instead of the vertical sync signal (Vsync) and the vertical sync clock (Vclock). It is obvious to those skilled in the art.

Digital data corresponding to one selected scan line stored in the input register 630 is simultaneously transferred to and stored in the storage register 640 by a load control signal. The data stored in the storage register 640 is selectively converted into 256 different analog liquid crystal voltages corresponding to 8-bits based on the gamma reference voltage supplied from the outside from the digital / analog converter (DAC) 650. The output buffer 660 is provided with a current driving capability sufficient to drive the data signal wiring so as to be simultaneously output to all data signal wiring.

While the data stored in the storage register 640 is output through the digital / analog converter 650, the data corresponding to the next scan line are sequentially sampled in the input register 630, and the process as described above is performed. It is repeated continuously. Therefore, since the output voltage of the low-data driver is simultaneously applied to all pixels connected to the scan line, which is one selected gate signal line, the TFT-LCD operates in a line-by-line sequential driving manner.

As a result, the liquid crystal display having the column-gate driver according to the first exemplary embodiment of the present invention can reduce the frame memory in half and correspondingly reduce the driving capacity of the row-data driver 330 in half. do.

Second Embodiment

7 and 8, a configuration of a liquid crystal display device having a column-gate driver and a layout of a liquid crystal display panel according to a second embodiment of the present invention will be described.

7 is a configuration diagram of a liquid crystal display device having a column-gate driver according to a second exemplary embodiment of the present invention.

Referring to FIG. 7, the liquid crystal display according to the second exemplary embodiment of the present invention has an n × m matrix array and includes a plurality of pixels arranged in a matrix form divided by gate lines and data lines that cross each other. Liquid crystal display panel 710 having a; A timing controller 740 that reads and rearranges input one frame data in units of 1/2 frames, and generates and outputs pixel data, gate control signals, and data control signals of the rearranged 1/2 frames, respectively; A frame memory (750) for storing pixel data of the half-frame to be rearranged and pixel data of the rearranged half-frame; A column-gate driver 720 driving a gate in a column direction of the liquid crystal display panel 710 and sequentially outputting scan pulses to the gate lines according to the gate control signal; And a low-data driver driving a source in a row direction of the liquid crystal display panel 710 and outputting data voltages corresponding to the data control signal and the rearranged 1 / 2-frame pixel data to the data lines. 730, wherein the gate lines are arranged one by one in every two adjacent unit pixels in a row direction to simultaneously supply a gate signal, and the data lines intersect the gate lines and the gate lines The data signal is supplied to the unit pixel in synchronization with the gate signal supplied through the gate signal, and two data signals are disposed between adjacent unit pixels in the column direction.

7, the operation of the liquid crystal display panel 710, the timing controller 740, the frame memory 750, the column-gate driver 720, and the low-data driver 730 may be substantially performed. Since the same, detailed description thereof will be omitted. In this case, it is apparent to those skilled in the art that the layout of the liquid crystal display panel 710 connected to the column-gate driver 720 and the low-data driver 730 and the data line is changed.

Here, when the number of unit pixels in the column direction is n, the number of the gate lines is n / 2, and when the number of unit pixels in the row direction is m, the number of the data lines is 2 m.

In the liquid crystal display according to the second exemplary embodiment of the present invention, a plurality of gate lines and data lines in a display area of the liquid crystal display panel 710 are formed in a matrix form, and two data lines are disposed between unit pixels in a row line direction. One gate line is disposed between two unit pixels in the column line direction. Comparing FIG. 7 with FIG. 3, it can be seen that k gate lines corresponding to n / 2 and j data lines corresponding to 2m are disposed.

In this case, thin film transistors (TFTs) are formed at intersections of the plurality of gate lines and data lines, and positions where the transistors are formed in the column line direction of the unit pixel may be changed. The layout structure can be changed. That is, the position of each unit pixel connected to the thin film transistor may be changed.

Accordingly, the liquid crystal display having the column-gate driver according to the second embodiment of the present invention has a gate-on time approximately twice that of the liquid crystal display having the column-gate driver according to a conventional scheme. Since it can be ensured, the pixel can be charged more stably. Substantially, the liquid crystal display having the column-gate driver according to the second embodiment of the present invention can reduce the frame memory size and secure the gate-on time of the liquid crystal display having the general column-data driver. Can be.

8 is a diagram illustrating a layout of a liquid crystal display panel in the liquid crystal display device having the column-gate driver according to the second embodiment of the present invention.

Referring to FIG. 8, the liquid crystal display panel according to the second embodiment of the present invention, specifically, the thin film transistor substrate, includes the unit pixel 810, the gate lines 820-1 and 820-2, and the data line 830-1. 830-2, ..., 830-6), a thin film transistor (TFT), and the like. Here, reference numeral 850 denotes a source of the thin film transistor extending in the horizontal direction on the data line, and reference numeral 860 denotes a drain. In addition, reference numeral 840 denotes an insulator that insulates the gate line and the data line.

The unit pixel 810 has a two-dimensional array in the form of k × j and is made of a material such as indium tin oxide (ITO).

The gate lines 820-1 and 820-2 connected to the column-gate driver 720 described above sequentially supply gate signals to two adjacent lines in the column line direction of the unit pixel 810. That is, the first gate line 820-1 is formed between the unit pixel of the first column line and the unit pixel of the second column line to sequentially apply a gate signal to the unit pixel of the first column line and the second column line. Are simultaneously applied to the unit pixels of, and the last gate line is formed between the unit pixels of the k-th column line and the unit pixels of the k-th column line to sequentially apply the gate signals.

The data lines 830-1, 830-2,..., 830-6 are formed to cross the gate lines 820-1, 820-2, and are supplied through the gate lines 820-1, 820-2. The data signal is supplied to the unit pixel 810 in synchronization with the gate signal.

Since two lines of unit pixels adjacent in the column line direction are gated on at the same time by the gate lines 820-1 and 820-2, the data signal can also be supplied to the unit pixels by two lines.

The thin film transistor TFT is formed at an intersection of the gate lines 820-1 and 820-2 and the data lines 830-1, 830-2,..., 830-6, and corresponds to the gate signal. The transfer to the pixel electrode is switched. Therefore, since the thin film transistor TFT which is a switching element should be provided for each unit pixel 810, the unit pixels adjacent to the data lines 830-1, 830-2,. Two lines are arranged between 810.

In other words, two data lines are formed between the unit pixels of the first row line and the unit pixels of the second row line, and in this manner, between the unit pixels of the j-1 row line and the unit pixels of the j row line. Two data lines are formed. Here, one data line may be further formed before the unit pixel of the first row line and after the unit pixel of the j-th row line. In addition, when two data lines are initially formed between the unit pixels of the first row line and the unit pixels of the second row line, two data lines may be formed after the unit pixels of the jth row line.

If the number of unit pixels in the row line direction is odd, that is, when k, the number of gate lines, is odd, one gate line may be connected to the unit pixels of the first or last row line.

In addition, although not shown, the present invention may be applied to a case in which the gate driver is divided into two to drive odd / even gate lines, respectively.

As a result, the liquid crystal display having the column-gate driver according to the second embodiment of the present invention can reduce the frame memory in half without reducing the gate charging time in half.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

According to the present invention, by processing the pixel data in units of 1/2 frames, it is possible to reduce the size of the frame memory used in the liquid crystal display having the column-gate driver and to reduce the data driving capacity of the low-data driver. .

In addition, according to the present invention, it is possible to reduce the size of the frame memory used in the liquid crystal display having the column-gate driver and to sufficiently secure the gate charging time.

Claims (18)

delete delete delete delete delete delete A liquid crystal display panel including pixels arranged in a matrix form separated by gate lines formed along a column direction and data lines formed along a row direction; A timing controller which reads the input one frame data in units of 1/2 frames and rearranges them, and generates pixel data, gate control signals, and data control signals of the rearranged 1/2 frames, respectively; A frame memory for storing pixel data of the rearranged 1/2 frame; A column-gate driver sequentially outputting scan pulses to the gate lines in response to the gate control signal; And A low-data driver configured to output data voltages corresponding to the rearranged 1 / 2-frame pixel data to the data lines in response to the data control signal; The gate lines are arranged one by one in every two adjacent unit pixels in the row direction to supply the gate signal at the same time, The data lines are configured to supply data signals to the unit pixels in synchronization with a gate signal supplied through the gate line, and two liquid crystal lines are disposed between two adjacent unit pixels in a column direction. Display. The method of claim 7, wherein And n, the number of gate lines is n / 2, wherein the number of unit pixels in a column direction is n / 2. The method of claim 7, wherein And the number of data lines is 2 m when the number of unit pixels in a row direction is m. The method of claim 7, wherein The frame memory, A read frame memory for temporarily storing the rearranged 1/2 frame of pixel data; And A write frame memory which temporarily stores the rearranged 1/2 frame pixel data to output the pixel data; And the timing controller controls to repeat reading and writing of pixel data in 1/2 frame units. delete The method of claim 10, The timing controller reads the RGB pixel data of the horizontal lines of 1/2 frames from the RGB pixel data of the horizontal lines of one frame input from the outside, and stores the RGB pixel data of the horizontal lines of the 1/2 frame in the read frame memory, and stores the RGB pixels of the vertical lines of the 1/2 frames. And rearranging the data into the write frame memory and outputting the rearranged 1 / 2-frame pixel data to the low-data driver. The method of claim 7, wherein And the frame memory is embedded in the timing controller or separately provided to the outside. The method of claim 7, wherein The row-data driver is configured to sequentially drive the rearranged 1 / 2-frame pixel data by n / 2 lines according to a scan pulse of the column-gate driver when the number of pixel in the column direction is n A liquid crystal display device having a gate driver. delete delete delete delete

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