JPH03188492A - Data control system for image display device - Google Patents

Abstract

PURPOSE:To attain miniaturization and the reduction in cost by alternately writing a first screen data and a second screen data in image memory, succes sively reading out data from the image memory so that the read address is continued, and alternately classifying the read data into first and second screens. CONSTITUTION:The data BU of the first screen 22 and the data BL of the second screen 23 are alternately written in single image memory 12, so that the written address is continued. At this time, it is decided that the written data is the data BU of the first screen 22 or the data BL of the second screen 23 based on the address written in the image memory 12, and address conversion with respect to the written address is carried out based on this determined result. When the data BU and BL are read out from the image memory 12, they are read out so as to continue the read address, and alternately classified to the first and second screens 22 and 23. Thus, miniaturization and reduction in cost are attained.

Description

[Detailed Description of the Invention] [Summary] Regarding a data control method in an image display device using a large LCD panel, etc., an inexpensive single memory such as a dual-port DRAM can be used, and the device can be made smaller. The purpose of the present invention is to provide a data control method for an image display device that can reduce costs and reduce costs.The display screen of the display device is divided into a first screen and a second screen. In an image display device that displays the entire display screen by driving two screens in parallel, data on the first screen and data on the second screen are stored in the image memory alternately and with consecutive write addresses. Data is sequentially read from the image memory so that write and read addresses are continuous, and the read data is alternately distributed to the first screen and the second screen.

[Industrial application field]

The present invention relates to a data control method in an image display device using a large LCD panel or the like.

In recent years, with the demand for smaller and lighter image display devices, flat panels have begun to be used in place of conventional CRT displays, and among these, display devices using LCD panels are becoming increasingly popular.

LCD panels change the amount of light transmitted through the electro-optical effect and display images using the resulting contrast ratio, but as LCD panels do not have a memory function, they must be constantly refreshed, and as the display capacity increases, the amount of light transmitted per pixel decreases. The amount changing time becomes shorter and the contrast decreases. Therefore, in order to increase the contrast on large LCD panels,
The display screen is divided into two parts, a lower screen and a lower screen, and these lower screens are driven in parallel to display the entire display screen.

[Conventional technology]

FIG. 5 is a block diagram of a conventional image display device f50.

The image display device 50 includes a processor 51 that controls the whole;
Lower screen memory 52, lower screen memory 53, lower screen memory 5
2 or a display refresh control unit 54 that provides a read address of data for display to the lower screen memory 53;
, an address switching section 55, 56, which switches between an address from the display refresh control section 54 and an address from the processor 51, and a lower screen memory 52 or a lower screen memory 53.
A lower screen register 57 and a lower screen register 58 for temporarily storing data read from the lower screen registers 57 and 58, a display timing control section 59, an LCD panel 20 having a display screen 21 divided into two parts, a lower screen 22 and a lower screen 23, etc. It consists of

In the image display device 50 described above, the lower screen 22 and the lower screen 23
A lower screen memory 52 and a lower screen memory 53 are provided correspondingly, and data is written to the lower screen memory 52 or the lower screen memory 53 by address designation from the processor 51, and the data written to each is read out by addressing from the display refresh control unit 54, and the read data is stored in the lower screen register 5.
7 and the lower screen register 58, and then transferred to the lower screen X driver 24 and the lower screen X driver 25 for display.

In order to perform the reading and writing in a time-sharing manner, an expensive high-speed static RAM had to be used.

In view of the above-mentioned problems, the present invention provides a dual-port DRAM.
It is an object of the present invention to provide a data control method in an image display device that can use an inexpensive single memory such as the above, and can reduce the size and cost of the device.

[Problem to be solved by the invention]

The data control method in the image display device 50 described above requires two memory blocks corresponding to the lower screen 22 and the lower screen 23, and requires many parts including peripheral circuits for this, and the circuit configuration is In addition to being complicated, it also requires a large area on the printed circuit board, which has been a bottleneck in reducing the size and cost of the device.

Further, since it is necessary to constantly read data from the lower screen memory 52 and the lower screen memory 53 for display purposes, the reading and writing of data [Means for Solving the Problem] The present invention provides the above-mentioned In order to solve this problem, as shown in FIG.
In the image display device 1 which displays the entire display screen 21 by driving the first screen 22 and the second screen 23 in parallel, the data BU of the first screen 22 and The data BL of the second screen 23 are written to the image memory 1 alternately and with consecutive write addresses.
2 and sequentially read data BU and BL from the image memory 12 so that the read addresses are consecutive;
The configuration is characterized in that the read data Bυ, BL are distributed alternately to the first screen 22 and the second screen 23.

[For production]

Data BU on the first screen 22 and data BL on the second screen 23
means that these data BU,
The BLs are written alternately and the write addresses are consecutive.

At this time, it is determined whether the data is the data BU of the first screen 22 or the data BL of the second screen 23 based on the write address to the image memory 12,
Based on this determination result, address translation for the write address is performed.

When reading the data BU and BL from the image memory 12, the read addresses are read out consecutively, and the read data BU and BL are read out from the first screen 22.
and the second screen 23 alternately.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an image display device l according to the present invention.

The image display device 1 includes a processor 11 that controls the whole, an image memory 12, a screen determination section 13, an address conversion section 14,
A display refresh control unit 15 that provides a read address of data for display to the image memory 12, and an address switching unit 1 that switches between an address from the display refresh control unit 15 and an address from the address conversion unit I4.
6. Upper screen registers 17a, 17b and 18 that temporarily store data read from the image memory 12, display timing control unit 19, and L
It is composed of a CD panel 20 and the like.

The LCD panel 20 has a display screen 21 divided into two, an upper screen 22 and an upper screen 23,
Upper screen X driver 24 and upper screen X driver 25 for individually driving data electrodes in the direction (horizontal direction), and electrodes of the same rank among the scanning electrodes in the Y direction (vertical direction) of the upper screen 22 and upper screen 23 It consists of a Y driver 26 that simultaneously scans and drives the respective lines one by one.

The image memory 12 is a RAM that can be randomly accessed.
12a and serial memory 12b for serial access
This is a so-called dual port memory. D
The RAM 12a has a capacity corresponding to both the upper screen 22 and the upper screen 23, and is connected to the data bus D by address designation from the address converter 14.
Data BU and BL from B are written. The serial memory 12b reads out the data written in the DRAM 12a as a continuous data string of a fixed length and outputs it serially.

The screen determination unit 13 determines whether the data is data BU of the upper screen 22 or data BL of the upper screen 23 based on the address An output from the processor 11 to the address bus AB in order to write the data to the image memory 12. This determination is made, for example, by determining whether the address An is smaller or larger than a certain value.

Based on the determination result by the screen determination section 13, the address conversion section 14 causes the data BU of the upper screen 22 and the data BL of the upper screen 23 to be written into the image memory 12 alternately and at consecutive write addresses Ab. Then, address translation is performed on the address An from the processor 11.

The display refresh control unit 15 uses the image memory 1 to constantly refresh the data displayed on the display screen 21.
2, generates an address for reading data BU and BL.

The upper screen register 17a and the upper screen register 18 contain data BU read from the image memory 12.

BL is the latch signal S from the display timing control section 19.
1 alternately latches.

The data BU latched in the upper screen register 17a is transferred to the other lower screen register 17b and latched at the rough timing by the upper screen register 18. Data BU of lower screen register 17b and lower screen register 18
, BL are simultaneously output to the lower screen X driver 24 or the lower screen X driver 25, respectively.

Next, the operation of the above-described image display device 1 will be explained.

FIG. 2 is a diagram showing the pixel configuration of the display screen 21. As shown in FIG.

Data DU3 to 0 shown on the lower screen 22 of the display screen 21
, and data DL3 to DL0 shown on the lower screen 23 each indicate pixel data.

These four pixels constitute one block, and one block of data DU3 to 0. DL3 to 0 are each data BU
, BL and written into the image memory 12 at - time.

FIG. 3 is a diagram showing the order of data written into the image memory 12.

The address conversion unit 14 converts an address An specified by the processor 11 in correspondence to the position of the pixel on the display screen 21.
is converted into the address Ab on the image memory 12, and as a result, the image memory 12 contains the upper first block BUI, which is data DU3 to 0 of the first block of the lower screen 22, and the first block BUI of the lower screen 23. Data DL3-0 of the upper first block BL1, data DU of the second block of the lower screen 22
Data B for each block of the lower screen 22 and the lower screen 23, such as the upper first block BU2, which is 3 to O, and so on.
U and BL are written alternately and consecutively.

FIG. 4 is a timing diagram showing the timing of reading data BU and BL from the image memory 12.

The vertical synchronization signal FMR is a timing signal for displaying one frame of screen on the display screen 21. During one cycle of this signal, all the data on the lower screen 22 and the lower screen 23 are sequentially displayed in parallel, and the vertical The display on the display screen 21 is maintained by repeating the synchronization signal FMR.

The horizontal synchronization signal LOAD is a signal indicating the display timing of one line in the screen of one frame.

The data transfer signal CPX is a clock for data transfer from the image memory 12 to the lower screen registers 17a, 17b and the lower screen register 18, and further to the LCD panel 20. Data sampling at each stage is performed by this data transfer signal CPX.

After the serial memory transfer timing signal is output,
From the serial memory 12b of the image memory 12, BUI,
BLI, BU2. Data is output in the order of BL2... These data are latched into the lower screen register 17a when the data transfer signal CPX falls, and are latched into the lower screen register 18 when the data transfer signal CPX rises.

Therefore, the data BUI, BU2, . . . of the lower screen 22 are stored in the lower screen register 17a, and the data BLI, BL2, . . . of the lower screen 23 are stored in the lower screen register 18, respectively.

Data BU1, BU stored in the lower screen register 17a
2... are latched by the lower screen register 17b at the next rising edge of the data transfer signal CPX, and as a result, the timings of the data BU and BL of the lower screen 22 and the lower screen 23 are aligned, and they are simultaneously transferred to the lower screen X. It is transferred to the driver 24 or the lower screen X driver 25.

The above-mentioned vertical synchronization signal FMR1 horizontal synchronization signal LOAD, data transfer signal cpx, serial memory transfer timing signal, etc. are created by the display timing control section 19 and given to necessary devices.

According to the above embodiment, the data B to be displayed is displayed on the entire display screen 21 consisting of the lower screen 22 and the lower screen 23.
Since U and BL can be developed into a single image memory 12, one large-capacity dual-port DRAM can be used as the image memory 12, and the number of parts including peripheral circuits for this can be reduced. Therefore, it is possible to reduce the size and cost of the device.

In the above embodiment, data for four pixels DU3 to O
, DL3-0 as one block of data BU.

Although it is treated as BL, data with other numbers of pixels may be treated as one block.0 When the display screen 21 is not divided, for example when using a CRT display, address conversion by the address conversion unit 14 is required. The image display device 1 and its respective parts may have various configurations other than those described above.

〔Effect of the invention〕

The present invention provides dual port DR in an image display device including a large LCD panel configured to display the entire display screen by dividing it into an upper screen and a lower screen, for example.
A single inexpensive memory such as AM can be used,
It is possible to reduce the size and cost of the device.

FIG. 3 is a diagram showing the order of data written into the image memory, FIG. 4 is a timing diagram showing the timing of reading data from the image memory, and FIG. 5 is a block diagram of a conventional image display device.

In the figure, l is an image display device, 12 is an image memory, 20 is an LCD panel (display device), 21 is a display screen, 22 is an upper screen (first screen), 23 is a lower screen (second screen), BU, BL is data.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image display device according to the present invention;

Claims (1)

[Claims] (1) The display screen (21) of the display device (20) is divided into a first screen (22) and a second screen (23), and these first screen (22) and second screen (23) in parallel to display the entire display screen (21), data (BU) of the first screen (22) and data of the second screen (23). (BL) and the image memory (12
), read out the data (BU) (BL) sequentially from the image memory (12) so that the read addresses are consecutive, and write the read data (BU) (BL
) is alternately distributed between the first screen (22) and the second screen (23).