WO1992012510A1

WO1992012510A1 - Image data recording and displaying circuit

Info

Publication number: WO1992012510A1
Application number: PCT/JP1991/001750
Authority: WO
Inventors: Takao Horikoshi; Toshihiro Takimoto; Yuji Koshino
Original assignee: Pentel Kabushiki Kaisha
Priority date: 1990-12-27
Filing date: 1991-12-24
Publication date: 1992-07-23
Also published as: GB9216543D0; GB2257599B; GB2257599A; JPH04232993A

Abstract

An image data recording and displaying circuit for converting the address outputted for a display controller (2) for external video signals to access a video memory (4) by an image-write table memory (7) and the address outputted when the controller (2) reads image data from the video memory (4) by an image-read table memory (6), arranging image data on the video memory (4) using the above addresses, vertical magnification and scrolling the image data, and generating and controlling the addresses corresponding to a plurality of screen displays.

Description

Specification

Title of invention

Recording of image data · Display circuit

Field of the invention

According to the present invention, a video signal from the outside is temporarily written into a video memory as image data for one screen by a display controller, and the image data written in the video memory is read by the display controller, and the display is repeatedly displayed. Of image data used in the image display device to be displayed on the display-fighting the display circuit.

Background of the Invention

Conventionally, when a video signal from the outside is read and written by the display controller, the output address is read and written in the same order as when reading and writing. Therefore, the surface corresponding to the screen input from the outside on a one-to-one basis was displayed on the display. In such a state, a liquid crystal display of a two-screen split drive type is used to reduce flickering of the display. In such a liquid crystal display, the screen must be divided into two upper and lower screens and the pixel groups must be driven alternately. Therefore, when an image displayed in the upper half of the screen is accessed, an even address is output from the display controller, and when an image in the lower half is accessed, an odd address is output from the display controller. Was. As described above, in the conventional method, the even address of the video memory corresponds to the upper half of the screen, and the odd address corresponds to the lower half of the screen. However, the image data in the video memory is processed by the CPU, and the programmer However, if the image data is not arranged in the video memory at the same position as the arrangement of figures on the screen as seen by a human eye, it is inconvenient to handle. In other words, it is inconvenient to handle if the image data corresponding to the pixel group immediately to the right of the pixel group on the screen is not arranged at the address following the address in the video memory. In addition, it was impossible to combine another screen with the vertical double display of the screen, any scroll, and the screen.

Summary of the Invention

SUMMARY OF THE INVENTION An object of the present invention is to provide an image capable of simultaneously performing a problem of a data arrangement in a memory in a video memory, a double display of a screen, scrolling an arbitrary amount of a screen, and synthesizing a screen while displaying external image data. Data recording-To provide a display circuit.

In the image data recording and display circuit according to the present invention, the display controller temporarily writes an external video signal to a video memory as image data for one surface, and writes the image data written in the video memory to the display controller. In the display circuit, an address conversion table for setting an address to be output by the display controller to access the video memory; and And address generation control means for generating and controlling addresses corresponding to the arrangement of the image data, the vertical display of the image, scrolling, and a plurality of screen displays. Here, the address output when the display controller writes external image data to the video memory is converted by the image writing table memory. Further, when the image data is read from the video memory by the display controller, the output address is the image reading table. Is converted in the memory.

Therefore, by rewriting the contents of the image writing table memory from the CPU as necessary, it is possible to set the arrangement of image data in the video memory when external image data is written to the video memory. Become.

To combine screens, part of the contents of the table memory for image reading must be set so that an area other than the area used to display the current screen in the video memory is read. Thus, another screen can be combined with the currently displayed screen and displayed.

The image data recording and display circuit according to the present invention can arrange image data in a video memory linearly on an address when viewed from the CPU even when a display that is driven by being divided into upper and lower two screens is used. Because it is possible, image processing can be easily performed.

In addition, even when the external surface is a moving image, it is possible to display the image in double height, scroll vertically, and combine the surface. In screen composition, another screen is composed and displayed without destroying the image data of the currently displayed screen stored in the video memory. Examples of screen composition include arbitrary screen display, time display, and status display.

Brief description of drawings

FIG. 1 is a configuration diagram in a first embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

A first embodiment of the present invention will be described with reference to FIG. The decoder 1 outputs the memory read signal CPU- RD output from the CPU 3 and the memory write signal CPU-WR. The memory read output from the display controller 2 Decodes LCD C—RD, memory write signal LC DC—WR, address CPU output from CPU 3—AD RS, and bus switch signal SEL set in the program, and switches signals S 1 and S 2 1,

Outputs S22, S3, and S4.

The switching circuit SW 1 determines whether the display controller 2 accesses the video memory 4 or accesses the CPU 3 based on the switching signal S 1 from the decoder 1. The switching circuit SW2 determines a table memory to be accessed by the display controller 2 or the CPU 3 based on a combination of the switching signals S21 and S22 from the decoder 1. The switching circuit SW3 determines whether the display controller 2 or the CPU 3 accesses the video memory 4 or the CPU 3 accesses the address conversion table memory 5 based on the switching signal S3 from the decoder 1. The switching circuit SW4 determines whether the display controller 2 accesses the video memory 4 or the CPU 3 accesses the video memory 4 based on the switching signal S4 from the decoder 1.

In the above configuration, the arrangement of the data in the video memory 4 is determined by the contents of the address conversion table memory 5 for the memory matsa viewed from the display controller 2. In the memory map viewed from the CPU 3, the video memory 4, the image reading table memory 6, and the image writing table memory 7 are arranged at different addresses. When the display controller 2 accesses the video memory 4, the program sets SEL to the display controller 2 side, and the address output from the display controller 2 passes through SW1 and SW2 to read data. To the image reading table memory 6 when writing, and to the image writing table memory 7 when writing data. Is input to The output of the address conversion table memory 5, that is, the converted address is input to the video memory 4 through SW3, and the display controller 2 reads and writes image data through SW4.

When CPU 3 accesses video memory 4, the program sets SEL to CPU 3 and outputs the address to access video memory 4. This address passes through SW 1 and SW 2, passes through SW 3 without being input to the address conversion table memory 5, is input to the video memory 4, and the CPU 3 reads and writes image data through SW 4.

When the CPU 3 accesses the address conversion table memory 5, the program sets SEL to the CPU 3 side and outputs an address for accessing the address conversion table memory 5. This address passes through SW1 and SW2, is input to the address conversion table memory 5, and the CPU 3 reads and writes the table contents, that is, the address information, through SW3.

The liquid crystal display 8 used in the present embodiment is of a type that is driven by being divided into two upper and lower screens as described above. The display controller 2 used here has two upper and lower screen operation modes set according to the liquid crystal display 8 to be used, and when the upper half of the screen is accessed, the lower half of the even address is displayed from the display controller 2. An odd address is output when is accessed.

Therefore, when address conversion is not performed, the pixel address of the LCD 8 and the data configuration of the video memory 4 are related to the even address of the video memory 4 corresponding to the upper half of the screen and the 'odd address corresponding to the lower half of the screen. I do. On the other hand, when the CPU 3 processes the image data in the video memory 4, it is easier to handle the image data if the image data is linearly arranged on the address in the video memory 4 as viewed from the CPU 3.

To solve this problem, the CPU 3 writes an address table into the image writing table memory 7 and the image reading table memory 6 such that the image data is linearly arranged on the address as viewed from the CPU 3. . As a result, the image data taken in from the outside by the display controller 2 is linearly arranged and stored in the video memory 4, and the image data read out from the video memory 4 by the display controller 2 It is displayed on the LCD display 8 in the same format as the signal VS.

Next, when an external screen is displayed vertically and vertically, the addresses in the table memory 7 for writing the image and the table memory 6 for reading the image are set twice each.

Further, when scrolling the screen displayed on the liquid crystal display 8 in the vertical direction, the entire contents of the image reading table memory 6 are rotated in the vertical direction for the ring-shaped scroll. For the scroll to be shifted, the entire contents of the image reading table memory 6 are shifted vertically. For an area where there is no screen from outside, prepare image data to be black pixels or white pixels on the entire surface and set an address to access this.

Further, when combining another surface (referred to as screen B) within one screen (referred to as screen A) and displaying the combined image, the image data of the screen B is written from the CPU 3 to another area of the video memory 4 in advance. So that screen B can be displayed Part of the image reading table memory 6 is rewritten. At this time, the rewriting location is determined according to the position where screen B is displayed on screen A. Even after the screen B is displayed, if the CPU 3 changes the contents of the area of the video memory 4 corresponding to the screen B, the change is reflected on the screen B. Also, multiple screens can be combined as long as the capacity of the video memory 4 permits.

The same operation can be performed even if the CPU 3 fights not only with image data from the outside but also with the image to be written into the video memory 4.

Claims

The scope of the claims

The display controller temporarily writes an external video signal to the video memory as image data for one screen, reads the image data written in the video memory by the display controller, and returns the image data to be displayed on the display. An address conversion table for setting an address to be output by the display controller to access the video memory; an arrangement of image data on the video memory by the address; An image data recording-display circuit, comprising: address generation control means for generating and controlling addresses corresponding to scrolling and a plurality of screen displays.

2. The image data recording / display circuit according to claim 1, wherein said disk array is a liquid crystal display.