DESCRIPTION
TITLE OF THE INVENTIONRECORDING/DISPLAYING CIRCUIT OF IMAGE DATA
FIELD OF THE INVENTION
The present invention relates to a recording/ displaying circuit of image data which is used in an image displaying apparatus in which a video signal from the outside is once written into a video memory as image data of one picture plane by a display controller and the image data written in the video memory is read out by the display controller and is repeatedly displayed on a display.
BACKGROUND OF THE INVENTION
Hitherto, addresses which are generated in the case where a video signal from the outside is read and written by a display controller are read and written in accordance with the same order as that in the reading and writing operations. Picture planes corresponding ,in a one-to-one manner to picture planes which are supplied from the outside, therefore, are displayed on a display. In such a state, a liquid crystal display of the two-upper/lower picture plane division driving type is used in order to reduce a flickering of the display. In such a liquid.crystal display, the picture plane must be divided into two upper and lower picture planes and a pixel group must be alternately driven.
In the case where the image displayed in the upper half of the picture plane is accessed, therefore, even addresses are generated from the display controller.
In the case where the image in the lower half is accessed, odd addresses are generated from the display controller.
In the conventional method as mentioned above, there is a relation between the pixels of the display and the data construction of a video memory such that the even addresses in the video memory correspond to the upper half of the screen and the odd addresses correspond to the lower half of the screen.
In the case where the image data in the video memory is processed by a CPU and a programmer programs, however, there is an inconvenience in handling unless the imaga data is arranged in the video memory at the same position as that of an arrangement of figures and the like on the screen which is seen by the eyes of a human being. That is, there is an inconvenience in handling unless the image data corresponding to a pixel group on the just right side of the pixel group on the screen is arranged in the address next to the address in the video memory. It is also impossible to display the picture plane at a double vertical magnification, to arbitrarily scroll, and to synthesize another picture plane into the picture plane.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a recording/displaying circuit of image data in which a data arrangement in a memory in a video memory, the display of a picture plane at a double vertical magnification, the scroll of a picture plane by an arbitrary amount, and the synthesis of a picture plane can be simultaneously executed while displaying the image data from the outside.
According to the present invention, there is provided a recording/displaying circuit of image data in which a video signal from the outside is once written into a video memory as image data of one picture plane by a display controller, the image data written in the video memory is read out by the display controller, and the image data is repeatedly displayed on a display, wherein the recording/displaying circuit comprises: an address converting table to set addresses which are generated to access the video memory by the display controller; and address generating control means for controlling the arrangement of the image data in the video memory, the display of the picture plane at a double vertical magnification, the scroll, and the generation of addresses corresponding to a plurality of display picture planes on the basis of the addresses.
The addresses which are generated when the image data from the outside is written into the video memory by the display controller are converted in a table memory for writing the image. The addresses which are generated when the image data is read out from the video memory by the display controller are further, converted in a table memory for reading the image.
By rewriting the content of the table memory for writing the image from a CPU as necessary, therefore, the arrangement of the image data in the video memory can be set when the image data from the outside is written into the video memory.
In order to synthesize the picture planes, a part of the content of the table memory for reading the image is set so as to read out another region different from the region which is being used to display the present picture plane in the video memory, so that another picture plane can be synthesized and displayed in the picture plane which is being displayed at present.
According to the recording/displaying circuit of the image data of the invention, even when the display which is divided into two upper and lower picture planes and driven is used, the image data in the video memory can be linearly arranged on addresses when they are seen from the CPU, so that the image can be easily processed.
Even in the case where the picture plane from the outside is a moving image,- the display at a double vertical magnification, the vertical scroll, and the synthesis of picture planes can be performed.
In the synthesis of the picture planes, another picture plane is synthesized and displayed without breaking the image data of the picture plane which has been stored in the video memory and is being displayed at present. The display of an arbitrary picture plane, the time display, and the state display can be mentioned as an example of the synthesis of picture planes.
BRIEF DESCRIPTION OF THE DRAWING
Fig. 1 is a constructional diagram according to the first embodiment of the invention.
BEST MODE FOR CARRYING OUT THE INVENTION
The first embodiment of the invention will be described with reference to Fig. 1. A decoder 1 decodes a memory read signal CPU-RD and a memory write signal CPU-WR which are generated from a CPU 3, a memory read signal LCDC-RD and a memory write signal LCDC-WR which are generated from a display controller 2, an address CPU-ADRS which is generated from the CPU 3, and a bus switching signal SEL which is set by a program and generates switching.signals S1. S21, S22, S3, and S4.
A switching circuit SW1 determines whether the display controller 2 accesses a video memory 4 or the CPU 3 accesses on the basis of the switching singal S1 from the decoder 1. A switching circuit SW2 determines a table memory to be accessed by the display controller 2 or the CPU 3 on the basis of a combination of the switching signals S21 and S22 from the decoder 1. A switching circuit SW3 determines whether the display controller 2 or the CPU 3 accesses the video memory 4 or the CPU 3 accesses an address converting table memory 5 on the basis of the switching signal S3 from the decoder 1. A switching circuit SW4 determines whether the display controller 2 accesses the video memory 4 or the CPU 3 accesses on the basis of the switching signal 54 from the decoder 1.
In the above construction, as for a memory map when it is seen from the display controller 2, an arrangement of data in the video memory 4 is determined by the content of the address converting table memory 5. As for a memory map when it is seen from the CPU 3, the video memory 4, a table memory 6 for reading an image, and a table memory 7 for writing an image are arranged in different addresses, respectively.
In the case where the display controller 2 accesses the video memory 4, the program sets the SEL to the side of the display controller 2 and the addresses generated from the display controller 2 pass through the switching circuits SW1 and SW2 and are supplied to the table memory 6 for reading.the image in the data reading mode and are supplied to the table memory.7 for writing the image in the data writing mode. An output of the address converting table memory 5, namely, a converted address passes through the switching circuit SW3 and is supplied to the video memory 4. The display controller 2 executes the reading and writing operations of the image data through the SW4.
In the case where the CPU 3 accesses the video memory 4, the program sets the SEL to the side of the CPU 3 and the addresses to access the video memory 4 are generated. The addresses pass through the SW- and SW2 and pass through the SW3 without being supplied to the address converting table memory 5 and are supplied to the video memory 4. The CPU 3 executes the reading and writing operations of the image data through the SW4.
In the case where the CPU 3 accesses the address converting table memory 5, the program sets the SEL to the side of the CPU 3 and addresses to access the address converting table memory 5 are generated.
The addresses pass through the SW1 and SW2 and are supplied to the address converting table memory 5 and the CPU 3 executes the reading and writing operations of the table content, namely, address information through the SW3.
A liquid crystal display 8 which is used in the embodiment is a display of the type which is. divided into two upper and lower picture planes and driven as mentioned above. Two operating modes of two upper and lower picture planes are set into the display controller 2 which is used here in accordance with the liquid crystal display 8 used. When the upper half picture plane is accessed, even addresses are generated from the display controller 2. When the lower half picture plane is accessed, odd addresses are generated from the display controller 2.
In the case where the address conversion is not executed, therefore, there is a relation between the pixels of the liquid crystal display 8 and the data construction of the video memory 4 such that the even addresses in the video memory 4 correspond to the upper half picture plane and the odd addresses correspond to the lower half picture plane. On the other hand, in case of processing the image data of the video memory 4 by the CPU 3, it is easy to handle the image data when the image data is linearly arranged on addresses in the video memory 4 so long as they are seen from the CPU 3.
In order to solve the above problem, an address table such that the image data is linearly arranged on addresses when they are seen from the CPU 3 is written into the table memory 7 for writing the image and the table memory 6 for reading the image from the CPU 3. The image data fetched from the outside is linearly arranged and stored into the video memory 4 by the display controller 2. The image data read out from the video memory 4 is displayed on the liquid crystal display 8 by the display controller 2 by the same format as that of an image signal VS from the outside.
In case of displaying the picture plane from the outside at a double vertical magnification, the addresses in the table memory 7 for writing the image or in the table memory 6 for reading the image are overlappingly set every two times.
In the case where the picture plane which is displayed on the liquid crystal display 8 is further scrolled in the vertical direction, whole contents of the table memory 6 for reading the image are rotated in the vertical direction in order to perform the ring-shaped scroll. In order to perform a scroll such as to shift, the whole contents of the table memory.
6 for reading the image are shifted in the vertical direction. The image data such that the overall picture plane is constructed by black pixels or white pixels is prepared for a region in which the picture plane from the outside does not exist and the addresses'to access the image data are set.
Further, in case of synthesizing and displaying another picture plane (referred to as a picture plane B) in one picture plane (referred to as a picture plane A), image data of the picture plane B is previously written into another region in the video memory 4 from the CPU 3 and a part of data in the table memory 6 for reading the image is rewritten such that the picture plane B can be displayed. In this instance, a location for rewriting is determined in correspondence to the position to display the picture plane B on the picture plane A. When the content of the region in the video memory 4 corresponding to the picture plane B is changed by the CPU 3 even after the picture plane B was displayed, the changed content is reflected to the picture plane B. A plurality of picture planes can be also synthesized within a permitted limit of the capacity of the video memory 4.
The above point is not limited to only the image data from the outside but similar operations can be also executed with respect to the image which is written into the video memory 4 by the CPU 3.