JPS592076A - Image display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image display device, and more particularly to an image display device including a plurality of viewers and a memory for storing data for displaying images for the screens of these viewers.

Generally, in order to display characters on a C11 or T screen, which is a type of viewer, it is necessary to constantly operate the CRT to refresh this screen. For this reason, typical image display devices use a method in which data to be displayed on the screen is stored in a memory, and the screen is refreshed based on the content stored in the memory. Note that in this specification, data for image display is stored. The memory will be referred to as refresh memory.

Data is written into this refresh memory from the processing device. The written data is read out sequentially, but
At this time, the character pattern is read out in parallel for each row or column of dots via a symbol generator,
Convert this to a serial signal using a video control device, etc.
F? , T, etc., and display the image on the screen.

Incidentally, image display devices that have a plurality of viewers and display images on the plurality of viewers have been developed. A refresh memory provided in such an image display device stores image display data for a plurality of screens. For example, if the refresh memory has data for 4 screens, the configuration may be 2 screens horizontally x 2 screens vertically, 4 screens horizontally x 1 screen vertically, or 1 screen horizontally x 4 vertically. Possible. Note that a collection of multiple screens is referred to as a large screen. Furthermore, as a conventional technique, there is a system called multi-page in which there are multiple screens and an image is displayed on one of the screens. However, each of the conventional screen configurations with different configurations constitutes a separate invention, and there has been no organic connection between the above-mentioned screen configuration differences, and there has been no organic connection with the multi-page system. In other words, one device can have various screen configurations,
Moreover, there was no such device that could perform a multi-page method.

However, in recent years, user needs have become more diverse, and there is a demand for a display device that can freely change the configuration of a large screen and still be capable of a multi-page format. In order to meet this need, it is necessary to be able to dynamically switch to a large screen configuration or multi-page format.
In the prior art, no method has been found that can meet this requirement.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image display device in which the configuration of a large screen made up of a plurality of viewers can be arbitrarily changed according to the purpose.

The present invention includes a refresh memory that stores information to be displayed on a viewer, a timing generator that outputs display addresses, a processing device that updates display information, and a memory address generator that generates display addresses for the refresher memory. In the image display device having the above-mentioned memory address generator, the sum of the start address and the output of the timing generator is multiplied by the column addition value, which is a unique value determined by the screen configuration, by the number of rows when the image is projected on the screen. The above object is achieved by providing means for adding the added values and outputting the result to the refresh memory, and by allowing the start address and the column addition value to be arbitrarily set by the processing device.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of an image display device of the present invention, and is an example in which the present invention is applied to an image display device of a reed refresh type.

The address bus 110 and the data bus 120 are connected to the processing device 1
Connected to 0. In addition, the data on the address bus 110 and the data bus 120 is transferred to the processor address control device 2.
0 and memory address generator 30, and these processor address control device 20 and memory address generator 3
The output of 0 is input to the refresh memory 50 via the address switch 40. refresh memory 50
is connected to data bus 120 via bidirectional gate 60, and its output is input to video controller 80 via symbol generator 70. This video controller 80 is connected to a viewer 90.

The output of timing generator 100 is input to memory address generator 30 and also to video controller 80.

The processing device 10 writes to and reads from the refresh memory 50 via the processing device address control device 20 and the address switch 40. At this time, the data read from the refresh memory 50 and the data to be written are read into the processing device 10 via the data bus 120 via the bidirectional gate 60, and are still transferred from the processing device 10 via the data bus 120 and the bidirectional gate 60. The data is then sent to the refresh memory 50. timing generator 10
0 generates a display (memory) address, which is converted by the memory address generator 30 into a display address that sequentially reads the refresh memory 50, and the contents of the refresh memory 50 are read. Data for display read out from the refresh memory 50 is sent to a symbol generator 70, and characters read out line by line by the symbol generator 70 are converted into serial signals by a video control circuit 80. The serial signal is input to the viewer 90, and the viewer 90 displays an image on the screen based on this serial signal. The processing device address control device 20 and the memory address generator 30 will be described in detail later.

The display screen of the viewer 90 in this embodiment has 96 columns horizontally and 42 columns vertically.
It is assumed that there are lines and a total of 4032 characters are displayed.

The refresh memory 50 has data for 9 screens, and the display format of the large screen is 3 horizontal screens x 3 vertical screens as shown in FIG.
It is possible to arbitrarily realize the 9 horizontal screens x 1 vertical screen shown in FIG. 3, the 1 horizontal screen x 9 vertical screen shown in FIG. 4, and the multi-page system shown in FIG. 5. The screen shown in Figures 2 to 4 allows one screen to be moved freely, and the screen shown in Figure 5 does not move and can be moved freely among the 9 screens. One screen is displayed. Further, the addresses of the fresh memory 50 are allocated as shown in FIGS. 2 to 5 to correspond to each of the display formats described above. That is, when the display format is a large screen, addresses are allocated from left to right and from top to bottom. For example, in Figure 2, the top left is address 0 and the top right is 28.
7, the left end of the second line is address 288, the right end of the second line is address 575, and so on, and the lower right is 36287.
It is a street address. In addition, in the form in which the screens overlap as shown in FIG. 5, the addresses are continuously allocated from the first screen to the ninth screen.

The timing generator 100 shown in FIG. 1 always outputs continuous addresses as shown in FIG.

That is, it outputs a memory address for sequentially reading out 4032 characters of one screen starting from 0. Further, the display address of the refresh memory 50 constituting the large screen is determined from the start address of the display screen, the output of the timing generator 100, and a column addition value that takes a unique value depending on the screen configuration. Table 1 shows the memory addresses of the above-mentioned refresh memory 50 for large screen display. That is,
The 0th line is the start address and timing generator 10
The first row is determined as the sum of the start address, the output of the timing generator 100, and the column addition value multiplied by 1, and so on. In addition, the relationship between the column addition value and the screen configuration (screen format) described above is as follows: mode 1 is for the 3 x 3 screen configuration shown in Figure 2, and mode 2 is for the 1 x 9 screen configuration shown in Figure 3. If the 9×1 screen configuration shown in FIG. 4 and the multi-page screen configuration shown in FIG.
Mode 1 is 192, mode 2 is 768, and mode 3 is O. Note that the general formula for determining the memory address is shown as the following formula.

Memory address = start address + timing generator output + mode-specific column addition value x number of rows ... (1)
The first step is to implement the conversion control in Table 1 using software.
This is the memory address generator 30 shown in the figure, and FIG. 7 is a block diagram showing a detailed circuit of this memory address generator 30. address bus 110 and data bus 120
Data from is input to the start address register 301, column addition register 302, and page register 303. The output of the start address register 301 is directly input to the full adder 305, and the output of the page register 303 is input to the full adder 305 via the start address converter 304. The output of the column addition register 302 is input to a full adder 306, and the output of this full adder 306 is input to a full adder 307. The output from the timing generator 100 is also input to the full adder 307, and the output is input to the full adder 305. The output of timing generator 100 is input to row pulse generator 308 , and the output of row pulse generator 308 is input to register 309 .

The output of the full adder 306 is also input to this register 309, and this output is input to the full adder 306.

Start address register 301 and column addition register 3
02 is capable of writing data from the processing device 10 shown in FIG. 1 via an address bus 110 and a data bus 120. The start address register 301 can set the start address of the display screen.
Further, the column addition register 302 can set a unique column addition value depending on the screen configuration. row pulse generator 30
8 receives a signal for scanning the screen from the timing generator 100, generates a pulser and sends it to the register 309 every time the scanning line advances one character unit. The register 309 is a register for sequentially storing column addition values. The outputs of the column addition register 302 and the register 309 are added by a full adder 306, and the output is fed back to the register 309 and stored. Therefore, each time the number of rows increases, the column addition value is added, and the full adder 306 outputs the column addition value×the number of rows. The output of the full adder 306 and the output of the timing generator 100 are added by the full adder 307, and the value of the output child column added value of the timing generator 100 x the number of rows is multiplied by itX. The output of the full adder 307 and the output of the start address register 301 are added by the full adder 305, and the full adder 305 outputs the value of start address + output child column addition value of timing generator 100 x number of rows. and the first
The calculations shown in the table must be performed in hardware.

In addition, in the case of a multi-screen configuration as shown in FIG. 5, the page number is stored in the page register 303, and this is converted to the start address of the multi-page in the start address conversion 5304, and this is the start address of each multi-page. becomes.

Next, a method for writing to and reading from the paste fresh memory 30 from the processing device 10 will be explained.

Addressing of the display screen from the processing device 10 is specified by a mode indicating the screen configuration, a page, and an X address in the row direction and an X address in the column direction within the page. Figure 8 shows mode 1 with a 3x3 screen configuration, Figure 9 shows mode 2 with a 1x9 screen configuration, Maclo diagram shows a 9x1 screen configuration, and Figure 11 shows a multi-page screen configuration. Both figures are in mode 3.

The address on the refresh memory 50 is determined by the sum of the start address, the X address, and the X column addition value of the X address. Here, the start address is determined by the mode and page and is as shown in Table 3. Further, the column addition value is determined depending on the mode and is as shown in Table 4.

FIG. 12 is a block diagram showing details of the processing device address control device 20. As shown in FIG. Data from address bus 110 and data bus 120 is input to page register 201, X address register 202, and X address register 203. Furthermore, data on the address bus 110 is input to the mode register 204. Page register 2
The output of 01 and the output of the mode register 204 are input to a start address converter 205, and the output of this start address converter 205 is input to a full adder 206. The output of mode register 204 is output to column adder converter 207.
The output from the column addition converter 3 table 207 and the X address register 202 is input to the multiplier 2.
It is input in 08. The output of this multiplier 208 and the output of the X address register 203 are input to a full adder 209, and the output of this full adder 209 is input to a full adder 206. Mode register 204 is writable by processor 10 with a mode indicating the configuration of the screen. The page register 201 is capable of writing values from page 0 to page 9 by the processing device 1o. The values shown in Table 3 are set in the column adder 207 according to the value of the mode register 204. A Y address and an X address can be written to the X address register 202 and the X address register 203, respectively, from the processing device 10. A start address as shown in Table 3 is set in the start address converter 205 according to the values of the mode register 204 and page register 201.

Addresses on refresh memory 50 are calculated as follows. The output of the column addition converter 207 and the output of the X address register 202 are multiplied by the multiplier 208, and the output of this multiplier 208 and the output of the X address register 203 are added by the full adder 209, so that , X address + Y address X column addition value is calculated. On the other hand, the start address is output from the start address converter 205, and the output of the start address converter 205 and the output of the full adder 209 are added by the full adder 206, and the result is start address + X address + Y address
The column addition value, ie, the address on refresh memory 50, is calculated.

According to this embodiment, the memory address generator 30 includes a start address register 301 and a column addition register 302.
, page register 3o3, register 309, full adder 3
By providing 05, 306, 307, etc., formula (1)
Calculate the output child column addition value x number of rows of the start address route timing generator shown in , output the memory address shown in Table 1, and start address register 301, column addition register 302, etc. By rewriting the contents of the screen using the processing device 10, the configuration of the screen can be changed arbitrarily, and a multi-page format can also be adopted. By providing the processing device address control device 20 with a page register 2o1, a column adder 207, an X address register 202, an X address register 203, a mode register 204, a start address converter 20, etc.
When changing the buttock, one screen is regarded as one page, and access is possible using the page and row direction address (X address) and column direction address (Y address).
Access to large screens and multi-pages can be made very easy, and multi-page screens can be switched instantaneously by specifying a page.

As described above, the image display device of the present invention has the advantage that the configuration of the large screen consisting of a plurality of viewers can be arbitrarily changed according to the purpose.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the image display device of the present invention; FIGS. 2 to 4 are explanatory diagrams showing various screen configurations of the embodiment and corresponding refresh memory addresses; FIG. 5 is an explanatory diagram showing the multi-page method according to this embodiment and the addresses of the No. 7 retrieval memory in this method, and FIG. 6 is an explanatory diagram showing the addresses output by the timing generator 100 shown in FIG. 1. , FIG. 7 is a block diagram showing a detailed circuit example of the memory address generator shown in FIG. 1, FIGS. 8 to 11 are explanatory diagrams showing an addressing method for the refresh memory of the processing device, and FIG. FIG. 2 is a block diagram showing a detailed circuit example of the processing device address control device shown in FIG. 1; DESCRIPTION OF SYMBOLS 10... Processing device, 20... Processing device address control device, 30... Memory address generator, 50... Refresh memory, 90... Viewer, 100...
Timing generator, 201...Page register, 20
2...Y address register, 203...X address register, 204...mode register, 206, 20
9゜305.306,307...Full adder, 301.
...Start address register, 302...Column addition register, 303...Page register, 308...Row nokurusuneuhino G≧] 2 eyes 3 eyes $ 4 5 figures #2 8 Eye $9 Eye vomit 1 $IO Prisoner $ll Hard! $12/10 [-1[

Claims (1)

[Claims] 1. A refresh memory that stores display information for multiple sides, a timing generator that outputs a memory address for reading this refresh memory, and a refresh memory that converts the address of this timing generator. a memory address generator that generates the memory address to be sent to the memory address; a processing device that updates the information displayed on the screen; and a processing device address control device that converts the address of the processing device and rewrites the refresh memory. In the image display device which displays an image by inputting the output of the refresha-rumor-tshu memory into the bee1-:TA, the device outputs a start address of the display screen into the memory address generator; , a device that outputs a column addition value unique to each screen configuration, a device that outputs a value obtained by multiplying a column adder by the number of rows each time the number of rows on the screen increases, and a value obtained by multiplying the column addition value by the number of rows. A device that adds the output of the timing generator and the start address is provided, and the device that outputs the start address and the device that outputs the column addition value can have their contents rewritten by the processing device. An image display device characterized by: 2. The processing device address control device includes a mode register that indicates the configuration of the screen that can be written to by the processing device, a page register that stores the page number, an X address register that stores the address in the row direction of the screen, and a 2. The image display device according to claim 1, further comprising a Y address register for storing addresses in the column direction.