JPS54154230A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS54154230A
JPS54154230A JP6287478A JP6287478A JPS54154230A JP S54154230 A JPS54154230 A JP S54154230A JP 6287478 A JP6287478 A JP 6287478A JP 6287478 A JP6287478 A JP 6287478A JP S54154230 A JPS54154230 A JP S54154230A
Authority
JP
Japan
Prior art keywords
register
signal
bit
memory
coordinate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6287478A
Other languages
Japanese (ja)
Other versions
JPS5855584B2 (en
Inventor
Masumi Yoshida
Kiyoshi Iwata
Eiichiro Yamamoto
Takeshi Masui
Yukikazu Kaburayama
Shinichi Shimizu
Toshio Matsuura
Shigemi Osada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6287478A priority Critical patent/JPS5855584B2/en
Publication of JPS54154230A publication Critical patent/JPS54154230A/en
Publication of JPS5855584B2 publication Critical patent/JPS5855584B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To write the two-dimensional information featuring an optional vertical- horizontal ratio into the memory possessing the one-dimensional memory address through the simple circuit constitution and simple operation. CONSTITUTION:X-coordinate register 1 and Y-coordinate register 4 are provided to memorize temporarily the signals showing the X and Y coordinates of the two- dimensional picture information, along with address distribution register 2 to designate m-bits of the memory address. Furthermore, shift register 5 and 3 are installed to give the n-bit shift to X or Y coordinate signal Sx and Sy which is to be the higher-rank bit. Thus, signal Sx or Sy to be the higher-rank bit is shifted by n-bit, and then the sum is obtained between signal Sy and Sx which is to be the lower-rank bit to obtain the memory address signal through register 6 and 7. In addition to these registers, AND gate 10 and OR gate 11 are provided to supply the address signal to memory 9.
JP6287478A 1978-05-26 1978-05-26 Storage device Expired JPS5855584B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6287478A JPS5855584B2 (en) 1978-05-26 1978-05-26 Storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6287478A JPS5855584B2 (en) 1978-05-26 1978-05-26 Storage device

Publications (2)

Publication Number Publication Date
JPS54154230A true JPS54154230A (en) 1979-12-05
JPS5855584B2 JPS5855584B2 (en) 1983-12-10

Family

ID=13212840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6287478A Expired JPS5855584B2 (en) 1978-05-26 1978-05-26 Storage device

Country Status (1)

Country Link
JP (1) JPS5855584B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592076A (en) * 1982-06-28 1984-01-07 株式会社日立製作所 Image display
JPS5998366A (en) * 1982-11-29 1984-06-06 Nec Corp Address designating circuit
JPS59228697A (en) * 1983-06-10 1984-12-22 三菱電機株式会社 Access circuit for image memory
JPS60126689A (en) * 1983-12-14 1985-07-06 株式会社アスキ− Display controller
JPS60135988A (en) * 1983-12-26 1985-07-19 株式会社アスキ− Display controller
JPS60135987A (en) * 1983-12-26 1985-07-19 株式会社アスキ− Display controller
JPS61233776A (en) * 1984-07-23 1986-10-18 テキサス　インスツルメンツ　インコ−ポレイテツド Video apparatus
JPS61269752A (en) * 1985-05-23 1986-11-29 Rohm Co Ltd Control device for processing image

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592076A (en) * 1982-06-28 1984-01-07 株式会社日立製作所 Image display
JPH0425555B2 (en) * 1982-06-28 1992-05-01 Hitachi Seisakusho Kk
JPS5998366A (en) * 1982-11-29 1984-06-06 Nec Corp Address designating circuit
JPS6245628B2 (en) * 1982-11-29 1987-09-28 Nippon Electric Co
JPS59228697A (en) * 1983-06-10 1984-12-22 三菱電機株式会社 Access circuit for image memory
JPS60126689A (en) * 1983-12-14 1985-07-06 株式会社アスキ− Display controller
JPS60135988A (en) * 1983-12-26 1985-07-19 株式会社アスキ− Display controller
JPS60135987A (en) * 1983-12-26 1985-07-19 株式会社アスキ− Display controller
JPS61233776A (en) * 1984-07-23 1986-10-18 テキサス　インスツルメンツ　インコ−ポレイテツド Video apparatus
JPS61269752A (en) * 1985-05-23 1986-11-29 Rohm Co Ltd Control device for processing image

Also Published As

Publication number Publication date
JPS5855584B2 (en) 1983-12-10

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