JPS61269752A - Control device for processing image - Google Patents

Abstract

PURPOSE:To execute a highly speedy image processing and to handle the large capacity of frame memory by providing a frame memory, etc., to store an image at the address to make X and Y coordinates of the image correspond to the higher order byte and the lower order byte of the address. CONSTITUTION:The memory area of the program memory corresponds to a bank 0 and the memory of the frame memory corresponds to a bank 1. The lowest order bit only from the address space 0000 of the bank 1 to FFFF is used,and the bit from a bit D1 to D7 is not used. When the reading and writing are executed for the frame memory area, the aces can be executed by making the X and Y coordinates of the image correspond to the higher order byte and the lower order byte of the address as they are and executing the address designation. Namely, when the frame memory is accessed, the bank of the frame memory is automatically selected through a change-over circuit, etc., and the address can be designated as the address equivalent to the X and Y coordinates. Thus, the image information can be processed at a high speed and the comparatively large quantity of the frame memory can be handled.

Description

DETAILED DESCRIPTION OF THE INVENTION +a) Technical Field The present invention relates to an image processing control device that stores images in a memory and performs image processing.

(b) Prior art and its disadvantages In general, image processing control devices are equipped with a memory (hereinafter referred to as frame memory) that stores image information in some way, and perform image processing by reading and writing the contents as necessary. be. Conventionally, when storing, for example, a binary image in such an image information storage memory, each dot was associated with each bit of the memory. However, when accessing frame memory, for example 8
With a Pinto CPU, data is read and written in 8-bit units.

In such a method, the image coordinates and the memory address do not directly correspond, so when processing a predetermined dot, a conversion process is required to obtain the address each time the processing is performed.

For example, 8-bit CPtJ is 256x256 dots.
When dealing with digitized images, the memory map becomes as shown in FIG. On the same plane, the address space is address ooo
There are 64 bytes from o to FFFF, EOOO-
Eight bytes up to FFFF are used as a frame memory area (image information storage area).

FIG. 6 shows the correspondence between the addresses of the frame memory area and the coordinates of the image. The numbers in the X direction represent the lower 8 bits of the address, and the numbers in the Y direction represent the higher 12 bits of the address. For example (X, Y)=
Pixel P at (6,2) is represented by 40 bits (seventh bit) of address E040.

As described above, since the coordinates of the image and the address of the frame memory do not directly correspond, it is necessary to perform some kind of processing to establish the correspondence.

FIG. 7 shows an example of the processing program. Steps 01 to 04 are processes for writing dots at the coordinates is calling. This subroutine uses a conversion table to input an address into the register HL, and to input a value indicating which bit of the address it is into an accumulator. Therefore, in step 03, the contents of the memory addressed by HL are logically ORed into the accumulator, and then in step 04, the bits corresponding to the predetermined coordinates are set by writing to the memory again.

Steps 11 to 14 are processes for reading out dots at coordinates X and Y, and in steps 11 and 12 coordinate address conversion is performed in the same manner as above. In step 13, the contents of the memory addressed by T-(L are ANDed into the accumulator, and in step 14, the contents of the accumulator are set to 0.
If so, jump to @.

As described above, it was necessary to perform conversion every time the process was performed.

Therefore, this was inconvenient when processing at high speed. Furthermore, as is clear from FIG. 5, the area that can be used as the program memory area is limited to the size of the frame memory area, and it is not possible to handle a large amount of image information with a large number of constituent dots. (C) Purpose of the Invention An object of the present invention is to provide an image processing control device that allows image coordinates and frame memory addresses to correspond substantially one-to-one, and that can handle a relatively large-capacity frame memory. (d) Structure and effect of the invention To summarize, this invention provides a frame memory in a memory bank independent from a program memory, and sets the X and Y coordinates of an image to an upper byte and a lower byte or a lower byte and an upper byte of an address. It is characterized by reading and writing image information to and from corresponding frame memory addresses, and performing bank switching to the frame memory bank when a program command used in a program that accesses the frame memory is a specific data transfer command. .

According to this invention, since the coordinate information directly corresponds to the address of the frame memory, it is possible to read and write image information at high speed. Furthermore, since the frame memory is independent from the program memory, the program memory can be used without being limited by its capacity. Additionally, programs and conversion tables for coordinate and address conversion are no longer required, which simplifies the program.
This has the effect of making programming easier.

(El Embodiment FIG. 2 is a block diagram of an image processing control device which is an embodiment of the present invention.

In the figure, the CPU is an 8-bit CPU such as Z-80, the program memory is a memory configured by ROM or RAM, or a combination thereof, the frame memory is a memory that stores image information as described above, and the I10 interface circuit is a bank switchable mode. It outputs a signal representing the mode to the switching circuit.

The switching circuit is a logic circuit for switching banks between program memory and frame memory.

FIG. 1 shows a memory map of the program memory and frame memory. As is clear from the figure, the program memory area corresponds to bank O, and the frame memory area corresponds to bank 1. The frame memory area uses only the least significant bit (DO) from address space 0000 to FFFF of bar 1, and bits D1 to D7 are unused areas.

That is, the program memory area has a capacity of 64 bytes, and the frame memory area has a capacity of 64 bits with addresses from 0000 to FFFF.

When reading or writing from or to this frame memory area, it can be accessed by specifying the address by making the X and Y coordinates of the image directly correspond to the upper and lower bytes of the address.

For example, when reading the contents of (X, Y) = (6, 2), the address of the frame memory is 0602.The program memory area exists in a bank different from the frame memory area to be accessed by the program, so the program must be programmed in some way. It is necessary to switch banks each time during execution.

Figure 3 is a circuit diagram for automatically doing this. In the figure, bank O and bank 1 correspond to the areas shown in Figure 1, and ENA is an enable signal and is active L. Decoder 1 outputs a signal when the contents of data buses DO to D7 reach predetermined contents.When a specific data transfer instruction is fetched from the program memory, the instruction code is input to each decoder. Ml is the instruction fetch timing signal of the machine cycle, and when this signal falls, the latch circuit latches the output of the OR gate.When a specific data transfer instruction is fetched, this latch circuit latches the output. The I10 interface circuit is the same as that shown in FIG. 2, and by holding its output at the "H" level according to the program, the bank switchable mode is maintained. In other words, when the output of the latch circuit and the output of the I10 interface circuit both become "H" level, the enable terminal of bank 1 becomes valid, and the CPU accesses the memory of bank 1, that is, the frame memory.In other cases, The output of the latch circuit is “L”
” level or the output of the I10 interface circuit is “L”
``When it is at level, the enable signal of bank O becomes valid, so the CPU accesses the memory of bank O, that is, the program memory.

FIG. 4 shows a specific processing program for image processing when Z-80 is used as the CP IJ.

Steps 01 and 02 are for setting the bank switchable mode; step 01 loads the accumulator with 01, and step 02 outputs the contents of the accumulator to the I10 interface circuit. In the OUT instruction in step 02, operand 30 is I1
0 represents the port address of the interface circuit. This causes the I10 interface circuit to output code 0.
1 is received to set the bank switchable mode, and the output signal to the switching circuit is held at the "H" level.

Steps 11, 12, and 13 are dot writing processes. In step 11, 01 is loaded into the accumulator, and in step 12, the coordinates X and Yf to be written are
Load each into the cDE register. At step 13, the contents of the accumulator are loaded into the address indicated by register DE. For example, X=06. If Y=02, the least significant bit of address 0602 of the frame memory is sent.

The instruction in step 13 is one of the specific instructions, and its instruction code °IA' is decoded by the decoder l (
The launch circuit is set by decoding the signal (FIG. 3). At this time, since it is the bank switchable mode, the contents of the accumulator are loaded to address 0602 of bank 1.

Steps 21, 22 and 23, 24 are processes for reading dots, and in step 21, the steps 1
Similarly to step 2, the coordinate data X and Y to be read are loaded into the register DE, and in step 22, the contents of the memory addressed by the register DE are loaded into the accumulator. The instruction in step 22 is another specific instruction, and the latch circuit is set by decoding the instruction code "12°" by the decoder 2 (FIG. 3). At this time, since the bank is in the bank switchable mode, the bank will be switched to bank 1. Step 23 rotates the contents of the accumulator to the right together with the carry flag. If the contents of the accumulator are 1 in step 22, the carry flag is set in step 23. Therefore, if the carry flag is set in step 24, the process jumps to @; otherwise, the process proceeds to the next step. This allows processing to be performed according to the dot at the specified coordinates.

Steps 31 and 32 are processes for canceling the bank switching mode. In step 3J, OO is loaded into the accumulator, and in step 32, the contents of the accumulator are output to the I10 interface circuit. As a result, the output of the I10 interface circuit to the switching circuit becomes "L" level. Therefore, in the processing after t1, even if the specific command shown in step 12 or 22 is used, the memory in bank 0 will be accessed.

In the next M1 cycle after fetching a specific instruction, the latch circuit is sent when the signal M1 becomes 1L'' level (at the beginning of the M1 cycle).Therefore, in that M1 cycle, the instruction is sent from bank 0. It will be fetched.

When accessing the frame memory in the manner described above, the bank of the Frey's memo 11 is automatically selected, and the address at that time can be specified as an address corresponding to the X and Y coordinates.

In the above embodiment, a dot is represented by one pin point as a frame memory, but if, for example, three 64-bit memories are used and Do-D2 in bank 1 is configured as a frame memory, Can handle images with 8 tones.

Furthermore, in the embodiment, the memory capacity of bank 0 is set to 64 bytes, but if the program memory area is set to 56 bytes from oooo to Di'FF as shown in FIG. f; can be configured with 4 bits (8 bytes) and 1t of 64 bytes of memory. In other words, 5. There is also the effect that the memory capacity to be implemented does not increase at all.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a memory map of an image processing control device which is an embodiment of the present invention, Fig. 2 is a block diagram of an image processing control device which is an embodiment of the invention, and Fig. 3 is a diagram showing a specific example of a switching circuit. 4 is a diagram showing an example of an image processing program, FIG. 5 is a diagram showing a memory map of a conventional image processing device, and FIG. 6 is a diagram showing the correspondence between conventional frame memory addresses and images. FIG. 7 is a diagram showing an example of a conventional image processing program.

Claims (1)

[Claims] (1) A program memory that stores a program in a space corresponding to the first bank of memory space, and a program memory that stores the program in a space corresponding to the second bank of memory space, and stores the X and Y coordinates of the image in the upper byte and lower byte of the address or a frame memory that stores images at addresses corresponding to the lower byte and upper byte, holding means that holds a bank switchable mode set by the CPU, and a program memory that stores images when the bank switchable mode is held. an image processing control device comprising means for switching the first bank to the second bank when a program command read from the computer is a specific data transfer command.