JPH0215343A - Central processing unit - Google Patents

Abstract

PURPOSE:To shorten the data width of a ROM to be accessed immediately after reset by allowing a CPU to compose instructions respectively consisting of 8 bits in the ROM to a 32-bit instruction immediately after reset, transfer the composed 32-bit instruction to a RAM and then execute the instruction. CONSTITUTION:The CPU 20 reads out the upper 8 bits of an address in the ROM 22 storing an instruction to be transferred from the ROM 22 as the lower 8 bits of the 32-bit data. The CPU 20 sends the 32-bit data to an ALU 1, the ALU 1 masks the upper 24 bits of the data and a shifter 2 shifts the 24 bits. The shifted data are sent to the ALU 1 again, OR operation between the lower 24 bits stored in an internal register 3 and effective data is found out and the OR result is returned to the register 3. Then, the CPU 20 composes instructions to be transferred from the address space of the ROM 22 and instructions stored by 8-bit width to an instruction with 32-bit width and transfers the composed instruction to the address space of the RAM 21 to be transferred. Then, instruction execution is started from the address of the instruction to be initially executed in the transferred RAM 21.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a central processing unit (hereinafter referred to as CPU: Ce) of a computer.
ntral ProcessingLlnit)
To be more specific, read-only memory (hereinafter referred to as ROM) that is accessed immediately after being reset.
This invention relates to a CPU that makes it possible to reduce the data width (referred to as 0nly Memory).

[Prior Art] FIG. 5 is a block diagram showing the configuration of a conventional computer system disclosed in, for example, Japanese Unexamined Patent Publication No. 60-215260.

In FIG. 5, 20 is a CPU, 21 is a memory for reading and writing at any time (hereinafter referred to as RAM: Random Access
ss Memory), 22 is ROM, 23
is a magnetic disk device as an auxiliary storage means. 24 is a data bus with a data width of 32 bits,
CPU20. All 32 bits are connected to the RAM 21 and the magnetic disk device 23, and only the lower 8 bits are connected to the ROM 22.

Note that in this computer system, addresses are allocated in units of 8 bits.

Now, when the computer's CPU executes a program while fishing on a boat, it first executes the program written on the ROM immediately after reset. The program written in this ROFI is a program for loading a program for the original operation into the RAM from an auxiliary storage device such as a magnetic disk.

Therefore, after this original program is loaded into the RAM, the CPU executes the program on the R11M.

For example, in the conventional computer system shown in FIG.
Immediately after reset, the PU 20 accesses the ROM 22 and executes the program written therein, thereby loading the program for the original operation recorded on the magnetic disk 23 into the RAM 21.
Execute the program loaded on 21.

At this time, in this computer system, the CPU 20 is I? A
When accessing l'121 or the magnetic disk device 23, as shown in FIG.
1a Allocate addresses so that one set constitutes one word data, and handle it as a data width of 32 bits.

However, since the program on ROM22 is only executed immediately after reset, the data width for ll0M22 is set to 8 bits, and addresses are allocated as shown in Figure 7 to store the memory with an 8-bit data width. By accessing, the amount of hardware of ll0M22 is reduced.

[Problems to be Solved by the Invention] Conventional computer systems are configured as described above, so when the CPU reads and executes a program on the ROM, it accesses the memory with an 8-bit data width and uses the RA
When reading and executing a program on M, the memory will be accessed with a data width of 32 bits.

Therefore, in the conventional CPU of this type, as shown in FIG. 4, there is an ALUI, a shifter 2. Internal register group 3. In addition to the circuits included in a general CPU such as the external bus interface 4a and the control unit 5a, there is also a means 9 for accessing the memory with a data width of 8 bits, a means 10 for accessing the memory with a data width of 32 bits, and a memory access means 10 for accessing the memory with a data width of 32 bits. At the time of access, a means 11 for switching between the above two access means is required, and it is also necessary to specify whether the memory space to be accessed is 8 bits (that is, 120M space) or 32 bits (that is, RAM or magnetic disk device). A bit width determination means 12 is required inside or outside the CPU, and there is a problem in that the amount of hardware increases for each of these means.

In FIG. 4, 6 is an internal bus, 7 is an external data bus, and 8 is a microprogram l? included in the control section. Q
It is M.

The present invention was made in order to solve the problem of the increase in the amount of hardware of the conventional CPU as described above.
CPU without increasing the amount of CPU hardware.
The purpose of this is to reduce the amount of ROM hardware that is accessed only immediately after reset.

[Means for Solving Problem U] The CPt1 of the present invention combines a plurality of instruction data stored in 8-bit width on the ROM into 32-bit width data immediately after reset, and transfers the data to the RAM, and then transfers the data to the RAM. It is designed to execute the following.

[Operation] In the CPU of the present invention, memory access is always performed with a data width of 32 pints when executing an instruction.

[Embodiments of the Invention] Hereinafter, the present invention will be described in detail based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing a general configuration of a CPU according to the present invention, and the same or corresponding parts as in the process diagram of FIG. 4 showing the conventional example described above are given the same reference numerals.

The overall configuration of the calculator is the same as the conventional example shown in FIG.

In the figure, like the conventional CP[I, C2, 3, 6, and 7 are respectively ALI1, a shifter, an internal register group, an internal bus, and an external data bus.

The internal register group 3 takes in and stores data from the internal bus 6, and also outputs the data to the internal bus 6. Shifter 2 shifts a specific bit string of 32-bit data taken in from internal bus 6 and outputs it to internal bus 6 again. Also AL
The UI performs predetermined processing on the data taken in from the internal bus 6 and outputs it to the internal bus 6 again.

4b is an external bus interface, which always has a data width of 32 bits and is connected to a memory (not shown), ie, RAM 21. The ROM 22 and the magnetic disk device 23 as an auxiliary storage t1 means are accessed.

5b is a control unit, 8.13 is a microprogram ROM included in this control unit 5b, and 8 is a conventional C
, the first part stores a microprogram for controlling the execution of general instructions like the PU, and the second part 13 stores a microprogram for controlling the execution of the procedures described below. This is the part.

The CPLI of the present invention is similar to the conventional computer system,
As shown in FIG. 5, the RAM 21. ROM22. It is in contact with the magnetic disk device 23.

As shown in FIG. 2, this ROM 22 has an RO in which instructions to be transferred are stored in the part that the CPII first reads.
The address of M22, and then the forwarding destination I? The address of AM21, the number of instructions to be transferred, and the address of AM21- to be executed first among the instructions transferred to the RAM are stored.

The operation of the CPU of the present invention configured as described above is as follows. Note that FIG. 3 is a schematic diagram showing the data processing procedure.

■(al Immediately after resetting, the CPU reads the address of the ROM 22 determined in advance by the hardware. There,
As explained above, the lower 8 bits of the address on the ROM 22 where the instruction to be transferred to the RAM 21 is stored are stored. part) contains that value, and the upper 24 bits are undefined. Therefore, the CPU sends the upper 24 bits of the read value to ALI via the internal bus 6.
After sending it to II and masking it, it is stored in any register of the internal register group 3 again via the internal bus 6. As a result, the internal register stores valid data in the lower 8 bits with hunting added and mask data in the upper 24 bits, that is, data of all "0#".

■(bl, fcl, (dl) Next, the CPU transfers the instructions to the ROM that stores the instructions to be transferred.
Bits 8 to 15 of address 22 from ROM 22 to 32
(Read as the lower 8 bits of bit data). CPU
sends this 32-bit data to the ALtll and sends it to the upper 24
After masking the bits (C1, shifter 2 shifts 8 bits to the left, sends it to ALtll again, performs a logical OR with the data previously stored in the internal register, and returns the result to the internal register. As a result, td in the internal register)
As shown in , the lower 16 hatched bits are valid data, and the upper 16 bits are mask data, that is, all "O" data is stored (dl.

■(el try, fgl Next, the CPU uses 110 where the instructions to be transferred are stored.
Bits 16 to 23 of the address of M are sold as the lower 8 bits of 32-bit data from the ROM (el.CPU
sends this 32-bit data to the ALtll and sends it to the upper 24
The bits are masked l&(fl, shifted 16 bits to the left by shifter 2, sent to ALUI again, stored in the internal register first, then logically ORed with the data for which the lower 16 bits are valid, and the result is stored in the internal register. As a result, the lower 24 hatched bits are significant data and the upper 8 bits are mask data, that is, all "0" data is stored in the internal register fgl.

■(hl, +IL fJl Finally, the CPU stores I? the instruction to be transferred.
Read the upper 8 pins of the 0-1 address from the ROM as the lower 8 bits of 32-bit data (hl.CPII
will send this 32 Bisotodek to ALIII and get the top 24
Masked bits l&fl are shifted to the left by 24 bits using shifter 2, sent to ALUI again, stored in the internal register first, then logically ORed with data for which the lower 24 bits are valid, and the result is stored in the internal register. return.

As described above, the CPU synthesizes 32-bit data from the data divided into 8-bit units on the ROM, in this case, the "ROM address where the instruction to be transferred is stored".
It was obtained by synthesizing (Jl.

Similarly, each CPU is 32 bits.
The "address of the RAM to be transferred", "the number of instructions to be transferred", and "the address of the transferred instruction in the RAM to be executed first" are obtained. Thereafter, the CPU synthesizes the instructions stored in 8-bit width into a 32-bit width by the same method as the number of instructions to be transferred from the address space of the ROM where the instructions to be transferred are stored, and transfers them to the transfer destination. R.A.
Transfer to M's address space. Thereafter, execution of the instruction is started from the address of the instruction to be executed first on the transferred RAM.

Note that these operations require an ALU, a shifter, an internal register, and a control means to perform the operations sequentially, but the ALU, shifter, and internal register are originally provided for the CPU to execute instructions. and you can use it. In addition, since the above-mentioned control is performed by a microprogram, the only increase in hardware in the CPU of the present invention is the area of the microprogram ROM 13 that stores the microprogram for the control, and the hardware is relatively small. This is a small increase.

In addition, in the above embodiment, the data width of the CPU is 32 bits,
I? Although an example in which the data width of the OM is 8 bits has been described, similar effects can be obtained even when the respective data widths are other values. For example, the data width of the CPU may be 16 bits or 64 bits. Furthermore, the data width of the ROM can be set to 16 bits.

Alternatively, it is also possible to provide a part for specifying the data width of the ROM in the contents of the ROM at the address first negotiated by the CPU.

Furthermore, the transferred I? It is also possible to use the same value as the address of the transfer destination RAM for the address of the first instruction to be executed on the AM, and in this case, it is also possible to omit the word data synthesis operation once. be.

[Effects of the Invention] As described above, in the CPII of the present invention, the daily bit instruction on the ROM is synthesized into 32 bits immediately after resetting, and the instruction is executed after being transferred to the RAM.
The CPU can always access memory with a 32-bit data width, without requiring hardware to access memory with different data widths.
It becomes possible to reduce the data width of the ROM that is accessed immediately after reset.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the general configuration of CPt1 of the present invention, FIG. 2 is a schematic diagram showing information stored in the ROM of a computer system using the CPU of the present invention, and FIG. 3 is a block diagram showing the general configuration of CPt1 of the present invention. 3 from the data divided into 8 CPU units
FIG. 4 is a schematic diagram showing the general configuration of a conventional CPU; FIG. 5 is a schematic diagram showing the configuration of the present invention and a conventional computer system; FIG. 7 is a schematic diagram showing address allocation when a conventional CPU accesses memory with a data width of 32 bits.
The figure is a schematic diagram showing address allocation when a conventional CPU accesses memory with an 8-bit data width. 1...-ALU 2...Shifter 3...Internal register group 5b...Control unit 21...RAM
22... [? 0? I23...Magnetic disk device Note that the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. In a central processing unit of a computer configured to load a program from an auxiliary storage means to a RAM according to data read from a predetermined address of a ROM after a reset, a plurality of programs read from a plurality of different addresses of the memory are loaded. A bit string extracting means for extracting arbitrary bit strings contained in each of the data; a data synthesizing means for synthesizing the plurality of bit strings extracted by the bit string extracting means into one word data; and the bit string extracting means. and controlling the data synthesizing means to obtain a plurality of word data information from a predetermined address space of the ROM immediately after reset, and data in the memory space of the address value of the auxiliary storage means included in the word data information. is converted into program data using the bit string extraction means and the data synthesis means, and then transferred to the memory space of the first address value of the RAM included in the word data information, and after this data transfer is completed, the 1. A central processing unit for a computer, comprising: control means for starting execution of an instruction from a second address value of a RAM included in word data information.